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| author | Ashish Singhal <ashishsingha@nvidia.com> | 2019-01-02 23:46:48 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2019-01-03 10:40:39 +0800 |
| commit | b5547b9ce97e80c3127682a2a5d4b9bd14af353e (patch) | |
| tree | 8a8e138e73d2839420740142024f336cf3716321 /BaseTools/Source/Python/Workspace | |
| parent | 19b0fc0a6b66f83154047a8ac43e66086e63610e (diff) | |
| download | edk2-b5547b9ce97e80c3127682a2a5d4b9bd14af353e.tar.gz edk2-b5547b9ce97e80c3127682a2a5d4b9bd14af353e.tar.bz2 edk2-b5547b9ce97e80c3127682a2a5d4b9bd14af353e.zip | |
MdeModulePkg/SdMmcPciHcDxe: Add SDMMC HC v4 and above Support.
Add SDMA, ADMA2 and 26b data length support.
If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
SDMA registers supporting 64 bit addresses.
If V4 64 bit address mode is supported in capabilities register,
program controller to enable V4 host mode and use appropriate
ADMA descriptors supporting 64 bit addresses.
If host controller version is above V4.0, enable ADMA2 with 26b data
length support for better performance. HC 2 register is configured to
use 26 bit data lengths and ADMA2 descriptors are configured appropriately.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1359
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace')
0 files changed, 0 insertions, 0 deletions