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| author | Chasel Chiu <chasel.chiu@intel.com> | 2019-06-14 17:39:34 +0800 |
|---|---|---|
| committer | Chasel Chiu <chasel.chiu@intel.com> | 2019-06-20 12:11:22 +0800 |
| commit | 4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1 (patch) | |
| tree | d6d3762bb3acc91146539879a86a2a6e1d6845d1 /BaseTools/Source/Python | |
| parent | 8a08dc5486f1a96c91b0ce86fc88a674ca0d8272 (diff) | |
| download | edk2-4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1.tar.gz edk2-4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1.tar.bz2 edk2-4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1.zip | |
IntelFsp2Pkg: add TempRamExitPpi.h.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883
Add header file for FSP_TEMP_RAM_EXIT_PPI which is
defined by FSP 2.1 spec.
Test: Build successfully.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'BaseTools/Source/Python')
0 files changed, 0 insertions, 0 deletions