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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2015-11-24 08:40:33 +0000
committerabiesheuvel <abiesheuvel@Edk2>2015-11-24 08:40:33 +0000
commit3164361121526318f278a7c1b84bdcc475d4ad95 (patch)
tree2aa270ffa4080035b7ea86f23fae839547d49d08 /BaseTools
parent2cde2696f5cd252c48fe250d44590869dae7a1e9 (diff)
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BaseTools/GenFw ARM: allow R_ARM_REL32 relocations
R_ARM_REL32 are relative relocations, so we don't need to do anything special when performing the ELF to PE/COFF conversion, since our memory layout is identical between the two binary formats. So just allow them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18931 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BaseTools')
-rw-r--r--BaseTools/Source/C/GenFw/Elf32Convert.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/GenFw/Elf32Convert.c
index a7b077873b..469394540e 100644
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -716,6 +716,7 @@ WriteSections32 (
// break skipped
case R_ARM_PC24:
+ case R_ARM_REL32:
case R_ARM_XPC25:
case R_ARM_THM_PC22:
case R_ARM_THM_JUMP19:
@@ -844,6 +845,7 @@ WriteRelocations32 (
// break skipped
case R_ARM_PC24:
+ case R_ARM_REL32:
case R_ARM_XPC25:
case R_ARM_THM_PC22:
case R_ARM_THM_JUMP19: