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author | Ronald Cron <ronald.cron@arm.com> | 2014-08-19 13:29:52 +0000 |
---|---|---|
committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-19 13:29:52 +0000 |
commit | 3402aac7d985bf8a9f9d3c639f3fe93609380513 (patch) | |
tree | 67b11334dc45181581aaaac236243fe72c7f614c /BeagleBoardPkg/Sec/Sec.c | |
parent | 62d441fb17d59958bf00c4a1f3b52bf6a0b40b24 (diff) | |
download | edk2-3402aac7d985bf8a9f9d3c639f3fe93609380513.tar.gz edk2-3402aac7d985bf8a9f9d3c639f3fe93609380513.tar.bz2 edk2-3402aac7d985bf8a9f9d3c639f3fe93609380513.zip |
ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BeagleBoardPkg/Sec/Sec.c')
-rw-r--r-- | BeagleBoardPkg/Sec/Sec.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/BeagleBoardPkg/Sec/Sec.c b/BeagleBoardPkg/Sec/Sec.c index eea9455e3f..0708396d97 100644 --- a/BeagleBoardPkg/Sec/Sec.c +++ b/BeagleBoardPkg/Sec/Sec.c @@ -2,7 +2,7 @@ C Entry point for the SEC. First C code after the reset vector.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -93,9 +93,9 @@ UartInit ( MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);
// Clear & enable fifos
- MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);
+ MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);
- // Restore MODE_SELECT
+ // Restore MODE_SELECT
MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);
}
@@ -153,7 +153,7 @@ CEntryPoint ( // Start talking
UartInit ();
-
+
InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE);
@@ -179,7 +179,7 @@ CEntryPoint ( // Load the DXE Core and transfer control to it
LoadDxeCoreFromFv (NULL, 0);
-
+
// DXE Core should always load and never return
ASSERT (FALSE);
}
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