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author | Leahy, Leroy P <leroy.p.leahy@intel.com> | 2016-05-10 15:34:22 -0700 |
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committer | Prince Agyeman <prince.agyeman@intel.com> | 2016-05-12 15:55:16 -0700 |
commit | b18f91c0c5a4f40fee7f104de295de3754636b5d (patch) | |
tree | f685ee85c706a779afa43dbfe7a445f6d21204c6 /CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | |
parent | 5a38784b745900ad9fbd687ac0d827e2f5fdc888 (diff) | |
download | edk2-b18f91c0c5a4f40fee7f104de295de3754636b5d.tar.gz edk2-b18f91c0c5a4f40fee7f104de295de3754636b5d.tar.bz2 edk2-b18f91c0c5a4f40fee7f104de295de3754636b5d.zip |
CorebootPayloadPkg: Use correct BaseSerialPortLib16550
Use the BaseSerialPortLib16550 which sets RTS and DTR during
initialization. This fixes the mis-matched flow control issue when
the flow control signals are connected between the host and target
and the host has flow control enabled.
Change-Id: I3505e129b2de3c5c17fff23c62553f15cd892dca
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Diffstat (limited to 'CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc')
-rw-r--r-- | CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 06e9b319dd..450a483954 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -160,7 +160,7 @@ #
TimerLib|CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
- SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+ SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
PlatformBdsLib|CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
|