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| author | Leahy, Leroy P <leroy.p.leahy@intel.com> | 2016-05-10 15:34:11 -0700 |
|---|---|---|
| committer | Prince Agyeman <prince.agyeman@intel.com> | 2016-05-12 15:54:42 -0700 |
| commit | 5a38784b745900ad9fbd687ac0d827e2f5fdc888 (patch) | |
| tree | 7b31193b7d87f387c9af4f0f81354e11bea17f11 /CorebootPayloadPkg | |
| parent | 1fee349aeb4e80f29780963daf2621d4514f5299 (diff) | |
| download | edk2-5a38784b745900ad9fbd687ac0d827e2f5fdc888.tar.gz edk2-5a38784b745900ad9fbd687ac0d827e2f5fdc888.tar.bz2 edk2-5a38784b745900ad9fbd687ac0d827e2f5fdc888.zip | |
CorebootPayloadPkg: Assume no PCI serial devices
Set the vendor to 0xffff which indicates the end of the list.
Change-Id: If6475e04d3675f0a932571a85d1dd3f301416b6a
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
eviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Diffstat (limited to 'CorebootPayloadPkg')
| -rw-r--r-- | CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 4 | ||||
| -rw-r--r-- | CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 907e952022..06e9b319dd 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -67,10 +67,10 @@ # UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
- # Vendor 0000 Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000)
+ # Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000) #
# [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]
- DEFINE PCI_SERIAL_PARAMETERS = {0x00,0x00, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}
+ DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff} #
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 90a484d55c..286d886d62 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -67,10 +67,10 @@ # UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
- # Vendor 0000 Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000)
+ # Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000) #
# [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]
- DEFINE PCI_SERIAL_PARAMETERS = {0x00,0x00, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}
+ DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff} #
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
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