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| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-09-04 09:28:26 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-09-06 12:11:16 +0800 |
| commit | 60794ee6b0c86c103ab227b0d9c2968c9c74810e (patch) | |
| tree | 77d6328da66c19d9bb7a1c59081bfecaa957b649 /IntelFrameworkModulePkg | |
| parent | 94fb621d370e7397e988038f28eede05b40ee6e5 (diff) | |
| download | edk2-60794ee6b0c86c103ab227b0d9c2968c9c74810e.tar.gz edk2-60794ee6b0c86c103ab227b0d9c2968c9c74810e.tar.bz2 edk2-60794ee6b0c86c103ab227b0d9c2968c9c74810e.zip | |
IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support.
If IOMMU is enabled, the legacy BIOS need allow the legacy memory
access by the legacy device.
The legacy memory is below 1M memory and HighPmm memory.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'IntelFrameworkModulePkg')
3 files changed, 73 insertions, 1 deletions
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf index 4ca412a344..48473a0713 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf @@ -137,6 +137,7 @@ gEfiLegacyBiosProtocolGuid ## PRODUCES
gEfiSerialIoProtocolGuid ## CONSUMES
gEfiSioProtocolGuid ## CONSUMES
+ gEdkiiIoMmuProtocolGuid ## CONSUMES
[Pcd]
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion ## CONSUMES
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h index 069646b518..fe9dd7463a 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h @@ -47,6 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include <Protocol/PciRootBridgeIo.h>
#include <Protocol/SerialIo.h>
#include <Protocol/SuperIo.h>
+#include <Protocol/IoMmu.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c index c4c77ec344..8ffdf0c1ff 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c @@ -41,7 +41,7 @@ BOOLEAN mIgnoreBbsUpdateFlag; BOOLEAN mVgaInstallationInProgress = FALSE;
UINT32 mRomCount = 0x00;
ROM_INSTANCE_ENTRY mRomEntry[ROM_MAX_ENTRIES];
-
+EDKII_IOMMU_PROTOCOL *mIoMmu;
/**
Query shadowed legacy ROM parameters registered by RomShadow() previously.
@@ -2697,6 +2697,61 @@ Done: }
/**
+ Let IOMMU grant DMA access for the PCI device.
+
+ @param PciHandle The EFI handle for the PCI device.
+ @param HostAddress The system memory address to map to the PCI controller.
+ @param NumberOfBytes The number of bytes to map.
+
+ @retval EFI_SUCCESS The DMA access is granted.
+**/
+EFI_STATUS
+IoMmuGrantAccess (
+ IN EFI_HANDLE PciHandle,
+ IN EFI_PHYSICAL_ADDRESS HostAddress,
+ IN UINTN NumberOfBytes
+ )
+{
+ EFI_PHYSICAL_ADDRESS DeviceAddress;
+ VOID *Mapping;
+ EFI_STATUS Status;
+
+ if (PciHandle == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = EFI_SUCCESS;
+ if (mIoMmu == NULL) {
+ gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu);
+ }
+ if (mIoMmu != NULL) {
+ Status = mIoMmu->Map (
+ mIoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ (VOID *)(UINTN)HostAddress,
+ &NumberOfBytes,
+ &DeviceAddress,
+ &Mapping
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuMap - %r\n", Status));
+ } else {
+ ASSERT (DeviceAddress == HostAddress);
+ Status = mIoMmu->SetAttribute (
+ mIoMmu,
+ PciHandle,
+ Mapping,
+ EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuSetAttribute - %r\n", Status));
+ }
+ }
+ }
+ return Status;
+}
+
+/**
Load a legacy PC-AT OPROM on the PciHandle device. Return information
about how many disks were added by the OPROM and the shadow address and
size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
@@ -2978,6 +3033,21 @@ LegacyBiosInstallPciRom ( RuntimeImageLength = Pcir->MaxRuntimeImageLength * 512;
}
}
+
+ //
+ // Grant access for below 1M
+ // BDA/EBDA/LowPMM and scratch memory for OPROM.
+ //
+ IoMmuGrantAccess (PciHandle, 0, SIZE_1MB);
+ //
+ // Grant access for HiPmm
+ //
+ IoMmuGrantAccess (
+ PciHandle,
+ Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemory,
+ Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemorySizeInBytes
+ );
+
//
// Shadow and initialize the OpROM.
//
|