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| author | Chasel Chiu <chasel.chiu@intel.com> | 2022-07-25 12:03:51 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-31 16:48:07 +0000 |
| commit | df25a5457f04ec465dce97428cfee96f462676e7 (patch) | |
| tree | 7ebc2087c7473f98f8c7cd8832c2633c1788c6bd /IntelFsp2Pkg/Tools/SplitFspBin.py | |
| parent | 4b7bd4c591a81a290b31e9d1a94c4b8be787989e (diff) | |
| download | edk2-df25a5457f04ec465dce97428cfee96f462676e7.tar.gz edk2-df25a5457f04ec465dce97428cfee96f462676e7.tar.bz2 edk2-df25a5457f04ec465dce97428cfee96f462676e7.zip | |
IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916
Provide FSP 2.4 MultiPhase interface and scripts
support.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/Tools/SplitFspBin.py')
| -rw-r--r-- | IntelFsp2Pkg/Tools/SplitFspBin.py | 48 |
1 files changed, 25 insertions, 23 deletions
diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFspBin.py index ddabab7d8c..419e5ba985 100644 --- a/IntelFsp2Pkg/Tools/SplitFspBin.py +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py @@ -103,29 +103,31 @@ class FSP_COMMON_HEADER(Structure): class FSP_INFORMATION_HEADER(Structure):
_fields_ = [
- ('Signature', ARRAY(c_char, 4)),
- ('HeaderLength', c_uint32),
- ('Reserved1', c_uint16),
- ('SpecVersion', c_uint8),
- ('HeaderRevision', c_uint8),
- ('ImageRevision', c_uint32),
- ('ImageId', ARRAY(c_char, 8)),
- ('ImageSize', c_uint32),
- ('ImageBase', c_uint32),
- ('ImageAttribute', c_uint16),
- ('ComponentAttribute', c_uint16),
- ('CfgRegionOffset', c_uint32),
- ('CfgRegionSize', c_uint32),
- ('Reserved2', c_uint32),
- ('TempRamInitEntryOffset', c_uint32),
- ('Reserved3', c_uint32),
- ('NotifyPhaseEntryOffset', c_uint32),
- ('FspMemoryInitEntryOffset', c_uint32),
- ('TempRamExitEntryOffset', c_uint32),
- ('FspSiliconInitEntryOffset', c_uint32),
- ('FspMultiPhaseSiInitEntryOffset', c_uint32),
- ('ExtendedImageRevision', c_uint16),
- ('Reserved4', c_uint16)
+ ('Signature', ARRAY(c_char, 4)),
+ ('HeaderLength', c_uint32),
+ ('Reserved1', c_uint16),
+ ('SpecVersion', c_uint8),
+ ('HeaderRevision', c_uint8),
+ ('ImageRevision', c_uint32),
+ ('ImageId', ARRAY(c_char, 8)),
+ ('ImageSize', c_uint32),
+ ('ImageBase', c_uint32),
+ ('ImageAttribute', c_uint16),
+ ('ComponentAttribute', c_uint16),
+ ('CfgRegionOffset', c_uint32),
+ ('CfgRegionSize', c_uint32),
+ ('Reserved2', c_uint32),
+ ('TempRamInitEntryOffset', c_uint32),
+ ('Reserved3', c_uint32),
+ ('NotifyPhaseEntryOffset', c_uint32),
+ ('FspMemoryInitEntryOffset', c_uint32),
+ ('TempRamExitEntryOffset', c_uint32),
+ ('FspSiliconInitEntryOffset', c_uint32),
+ ('FspMultiPhaseSiInitEntryOffset', c_uint32),
+ ('ExtendedImageRevision', c_uint16),
+ ('Reserved4', c_uint16),
+ ('FspMultiPhaseMemInitEntryOffset', c_uint32),
+ ('FspSmmInitEntryOffset', c_uint32)
]
class FSP_PATCH_TABLE(Structure):
|