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| author | Yarlagadda, Satya P <satya.p.yarlagadda@intel.com> | 2016-07-26 09:14:17 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-07-27 10:00:03 +0800 |
| commit | fb713b1d3757f2c24afcee03584b02b0fd4cc220 (patch) | |
| tree | fa3d6205d5c13248752ec4176efeeddbc50dbd6a /IntelFsp2Pkg | |
| parent | 4035704a8b6cb8da1a28df2fd938aceba745d7ec (diff) | |
| download | edk2-fb713b1d3757f2c24afcee03584b02b0fd4cc220.tar.gz edk2-fb713b1d3757f2c24afcee03584b02b0fd4cc220.tar.bz2 edk2-fb713b1d3757f2c24afcee03584b02b0fd4cc220.zip | |
IntelFsp2Pkg: Skip loading Microcode if MicrocodeCodeSize is zero
During asm to Nasm conversion, we missed the code to skip loading the
microcode and return success if the size is zero. Added additional check to
report error if the microcode size is not zero but less than 2 kB.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
(cherry picked from commit 4c53eb72d539f5ca61f949235014f7e43f0e6354)
Diffstat (limited to 'IntelFsp2Pkg')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 55ee85a06e..6e860238fd 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -172,7 +172,15 @@ ASM_PFX(LoadMicrocodeDefault): cmp eax, 0
jz ParamError
mov esp, eax
-
+
+ ; skip loading Microcode if the MicrocodeCodeSize is zero
+ ; and report error if size is less than 2k
+ mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
+ cmp eax, 0
+ jz Exit2
+ cmp eax, 0800h
+ jl ParamError
+
mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
cmp esi, 0
jnz CheckMainHeader
|