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| author | Chasel Chiu <chasel.chiu@intel.com> | 2019-06-14 17:39:34 +0800 |
|---|---|---|
| committer | Chasel Chiu <chasel.chiu@intel.com> | 2019-06-20 12:11:22 +0800 |
| commit | 4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1 (patch) | |
| tree | d6d3762bb3acc91146539879a86a2a6e1d6845d1 /IntelFsp2Pkg | |
| parent | 8a08dc5486f1a96c91b0ce86fc88a674ca0d8272 (diff) | |
| download | edk2-4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1.tar.gz edk2-4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1.tar.bz2 edk2-4c12dcace99dba96a9d4f7d0e259c0231e8fe6f1.zip | |
IntelFsp2Pkg: add TempRamExitPpi.h.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883
Add header file for FSP_TEMP_RAM_EXIT_PPI which is
defined by FSP 2.1 spec.
Test: Build successfully.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg')
| -rw-r--r-- | IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h | 52 | ||||
| -rw-r--r-- | IntelFsp2Pkg/IntelFsp2Pkg.dec | 15 |
2 files changed, 63 insertions, 4 deletions
diff --git a/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h new file mode 100644 index 0000000000..0db54dfa45 --- /dev/null +++ b/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h @@ -0,0 +1,52 @@ +/** @file
+ This file defines the Silicon Temp Ram Exit PPI which implements the
+ required programming steps for disabling temporary memory.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
+#define _FSP_TEMP_RAM_EXIT_PPI_H_
+
+///
+/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
+///
+#define FSP_TEMP_RAM_EXIT_GUID \
+ { \
+ 0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52 } \
+ }
+
+//
+// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
+//
+typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
+
+/**
+ Silicon function for disabling temporary memory.
+ @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters structure.
+ This structure is normally defined in the Integration
+ Guide. If it is not defined in the Integration Guide,
+ pass NULL.
+ @retval EFI_SUCCESS - FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER - Input parameters are invalid.
+ @retval EFI_UNSUPPORTED - The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR - Temporary memory exit.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_EXIT) (
+ IN VOID *TempRamExitParamPtr
+ );
+
+///
+/// This PPI provides function to disable temporary memory.
+///
+struct _FSP_TEMP_RAM_EXIT_PPI {
+ FSP_TEMP_RAM_EXIT TempRamExit;
+};
+
+extern EFI_GUID gFspTempRamExitPpiGuid;
+
+#endif // _FSP_TEMP_RAM_EXIT_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index cc17164742..60d40ab6b9 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -42,13 +42,23 @@ # PPI to indicate FSP is ready to enter notify phase
# This provides flexibility for any late initialization that must be done right before entering notify phase.
#
- gFspReadyForNotifyPhasePpiGuid = { 0xcd167c1e, 0x6e0b, 0x42b3, { 0x82, 0xf6, 0xe3, 0xe9, 0x6, 0x19, 0x98, 0x10}}
+ gFspReadyForNotifyPhasePpiGuid = { 0xcd167c1e, 0x6e0b, 0x42b3, {0x82, 0xf6, 0xe3, 0xe9, 0x06, 0x19, 0x98, 0x10}}
#
# PPI as dependency on some modules which only required for API mode
#
gFspInApiModePpiGuid = { 0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}
+ #
+ # PPI for Architectural configuration data for FSP-M
+ #
+ gFspmArchConfigPpiGuid = { 0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}
+
+ #
+ # PPI to tear down the temporary memory set up by TempRamInit ().
+ #
+ gFspTempRamExitPpiGuid = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
+
[Guids]
#
# GUID defined in package
@@ -64,9 +74,6 @@ gFspPerformanceDataGuid = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
gFspEventEndOfFirmwareGuid = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
-[Ppis]
- gFspmArchConfigPpiGuid = { 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
-
[PcdsFixedAtBuild]
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001
|