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authorYao, Jiewen <jiewen.yao@intel.com>2014-12-06 00:29:04 +0000
committerjyao1 <jyao1@Edk2>2014-12-06 00:29:04 +0000
commit975f1c64174967c6e1e26d63892b630a6bea8b23 (patch)
treea30d55b2f6b23e77b1695328f50109428fddeef7 /IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
parent54190e8366e79b5b2baacb07dc43b481fd54baa0 (diff)
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Updated FspApiEntry.asm/.s to auto detect the size of the MCU region.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16478 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm')
-rw-r--r--IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm11
1 files changed, 8 insertions, 3 deletions
diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
index 8ad9744ab4..219b0ee9c1 100644
--- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
+++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
@@ -214,16 +214,21 @@ advance_fixed_size:
check_address:
; Is valid Microcode start point ?
- cmp dword ptr [esi], 0ffffffffh
+ cmp dword ptr [esi].ucode_hdr.version, 0ffffffffh
jz done
+ ; Is automatic size detection ?
+ mov eax, [esp].LOAD_UCODE_PARAMS.ucode_code_size
+ cmp eax, 0ffffffffh
+ jz @f
+
; Address >= microcode region address + microcode region size?
- mov eax, [esp].LOAD_UCODE_PARAMS.ucode_code_addr
- add eax, [esp].LOAD_UCODE_PARAMS.ucode_code_size
+ add eax, [esp].LOAD_UCODE_PARAMS.ucode_code_addr
cmp esi, eax
jae done ;Jif address is outside of ucode region
jmp check_main_header
+@@:
load_check:
; Get the revision of the current microcode update loaded
mov ecx, MSR_IA32_BIOS_SIGN_ID