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| author | Yao, Jiewen <Jiewen.Yao@intel.com> | 2015-04-23 08:52:21 +0000 |
|---|---|---|
| committer | jyao1 <jyao1@Edk2> | 2015-04-23 08:52:21 +0000 |
| commit | 9da591867c0bad1abbe17a321dc5b16d95226c6a (patch) | |
| tree | d73d5eefb589fec2196b92e1cb741317300f16e0 /IntelFspPkg/IntelFspPkg.dec | |
| parent | 3b7f0a488be0ca7a2a8e4c352b0e10496bee9530 (diff) | |
| download | edk2-9da591867c0bad1abbe17a321dc5b16d95226c6a.tar.gz edk2-9da591867c0bad1abbe17a321dc5b16d95226c6a.tar.bz2 edk2-9da591867c0bad1abbe17a321dc5b16d95226c6a.zip | |
Update IntelFspPkg to support FSP1.1
-- Add BootLoaderTolumSize support
-- Extend FspApiCallingCheck with ApiParam for BootLoaderTolumSize
-- Rename all Bootloader to BootLoader as official name
-- Rename Ucode to Microcode
-- Remove FspSelfCheck API, because it is merged into SecPlatformInit
-- Add GetFspVpdDataPointer() in FspCommonLib.h
-- Document FspSecPlatformLib.h
-- Reorg FSP_PLAT_DATA data structure to let it match FSP spec.
-- Move helper function in FspSecCore to reduce platform enabling effort
-- Fix LibraryClasses declaration in DEC file.
-- Enhance PatchFv to check if it is valid FSP bin.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17196 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFspPkg/IntelFspPkg.dec')
| -rw-r--r-- | IntelFspPkg/IntelFspPkg.dec | 31 |
1 files changed, 19 insertions, 12 deletions
diff --git a/IntelFspPkg/IntelFspPkg.dec b/IntelFspPkg/IntelFspPkg.dec index 1f286c1c7d..6f8a6306ab 100644 --- a/IntelFspPkg/IntelFspPkg.dec +++ b/IntelFspPkg/IntelFspPkg.dec @@ -24,22 +24,25 @@ [LibraryClasses]
## @libraryclass Provides cache-as-ram support.
- CacheAsRamLib|IntelFspPkg/Include/Library/CacheAsRamLib.h
+ CacheAsRamLib|Include/Library/CacheAsRamLib.h
## @libraryclass Provides cache setting on MTRR.
- CacheLib|IntelFspPkg/Include/Library/CacheLib.h
+ CacheLib|Include/Library/CacheLib.h
## @libraryclass Provides debug device abstraction.
- DebugDeviceLib|IntelFspPkg/Include/Library/DebugDeviceLib.h
+ DebugDeviceLib|Include/Library/DebugDeviceLib.h
## @libraryclass Provides FSP related services.
- FspCommonLib|IntelFspPkg/Include/Library/FspCommonLib.h
+ FspCommonLib|Include/Library/FspCommonLib.h
## @libraryclass Provides FSP platform related actions.
- FspPlatformLib|IntelFspPkg/Include/Library/FspPlatformLib.h
+ FspPlatformLib|Include/Library/FspPlatformLib.h
## @libraryclass Provides FSP switch stack function.
- FspSwitchStackLib|IntelFspPkg/Include/Library/FspSwitchStackLib.h
+ FspSwitchStackLib|Include/Library/FspSwitchStackLib.h
+
+ ## @libraryclass Provides FSP platform sec related actions.
+ FspSecPlatformLib|Include/Library/FspSecPlatformLib.h
[Guids]
#
@@ -52,6 +55,7 @@ gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }
gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }
gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
+ gFspBootLoaderTolumHobGuid = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1
# Guid defined by platform
gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }
@@ -59,12 +63,15 @@ gFspReservedMemoryResourceHobMiscGuid = { 0x00d6b14b, 0x7dd0, 0x4062, { 0x88, 0x21, 0xe5, 0xf9, 0x6a, 0x2a, 0x1b, 0x00 } }
[PcdsFixedAtBuild]
- gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00108|UINT32|0x00000001
- gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001
- gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT32|0x10001002
- gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x1000|UINT32|0x10001003
- gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry | 32|UINT32|0x00002001
- gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry | 5|UINT32|0x00002002
+ gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001
+ gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001
+ gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT32|0x10001002
+ gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x1000|UINT32|0x10001003
+ gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry | 32|UINT32|0x00002001
+ gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry | 6|UINT32|0x00002002
+ gIntelFspPkgTokenSpaceGuid.PcdFspAreaBaseAddress |0xFFF80000|UINT32|0x10000001
+ gIntelFspPkgTokenSpaceGuid.PcdFspAreaSize |0x00040000|UINT32|0x10000002
+ gIntelFspPkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003
[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]
gIntelFspPkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000
|