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authorStar Zeng <star.zeng@intel.com>2014-08-22 01:23:28 +0000
committerlzeng14 <lzeng14@6f19259b-4bc3-4df7-8a09-765794883524>2014-08-22 01:23:28 +0000
commitfa7fadf78e064d1d73d21d0487e2a31a394a88ae (patch)
tree7728a00768a68ae5314c4063cfd1d18e90fbd5e5 /IntelFspPkg/Library
parentacedecdd5ec4f45c9b7d456d01017c43e9fd2fb2 (diff)
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IntelFspPkg BaseCacheLib: State CacheAsRamLib in its inf, because it consumes DisableCacheAsRam() that is the interface of CacheAsRamLib.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15877 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFspPkg/Library')
-rw-r--r--IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf1
1 files changed, 1 insertions, 0 deletions
diff --git a/IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf b/IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf
index d76a32bc4f..fb8d5f6083 100644
--- a/IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf
+++ b/IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf
@@ -29,4 +29,5 @@
[LibraryClasses]
BaseMemoryLib
+ CacheAsRamLib