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authorJiewen Yao <jiewen.yao@intel.com>2018-03-18 23:39:13 +0800
committerJiewen Yao <jiewen.yao@intel.com>2018-03-20 08:51:54 +0800
commit8d8c487fb9845685a2d7d0489bc0e2b3cca4d5ff (patch)
tree10bdd5687b2b28ac26dd26a120c698994d0d7655 /IntelSiliconPkg
parent5aef7ba3ce31089d9f8e57b242e3b3d589404309 (diff)
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IntelSiliconPkg/Vtd: Add more debug info.
Add more debug info for reason code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'IntelSiliconPkg')
-rw-r--r--IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
index bc9f427a36..8dbc83fa2d 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
@@ -481,7 +481,7 @@ DumpVtdRegs (
SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID;
DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write"));
- DEBUG((DEBUG_INFO, " Reason - %x\n", FrcdReg.Bits.FR));
+ DEBUG((DEBUG_INFO, " Reason - %x (Refer to VTd Spec, Appendix A)\n", FrcdReg.Bits.FR));
}
}