diff options
| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-09-08 13:39:43 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-09-16 09:18:01 +0800 |
| commit | ffe77707a320077373d35029ba5b43253da6fd05 (patch) | |
| tree | 8862a5adfad24a9e1f4d0ce634d5c181659296e5 /IntelSiliconPkg | |
| parent | 40cc2270556ec5e49d184c946bb58981f7155cf3 (diff) | |
| download | edk2-ffe77707a320077373d35029ba5b43253da6fd05.tar.gz edk2-ffe77707a320077373d35029ba5b43253da6fd05.tar.bz2 edk2-ffe77707a320077373d35029ba5b43253da6fd05.zip | |
IntelSiliconPkg/VTdDxe: Disable PMR
When VTd translation is enabled, PMR can be disable.
Or the DMA will be blocked by PMR.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'IntelSiliconPkg')
| -rw-r--r-- | IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 51 |
1 files changed, 50 insertions, 1 deletions
diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c index 7402d81876..1404af7cd7 100644 --- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c +++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c @@ -196,6 +196,39 @@ PrepareVtdConfig ( }
/**
+ Disable PMR in all VTd engine.
+**/
+VOID
+DisablePmr (
+ VOID
+ )
+{
+ UINT32 Reg32;
+ VTD_CAP_REG CapReg;
+ UINTN Index;
+
+ DEBUG ((DEBUG_INFO,"DisablePmr\n"));
+ for (Index = 0; Index < mVtdUnitNumber; Index++) {
+ CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
+ if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
+ continue ;
+ }
+
+ Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
+ if ((Reg32 & BIT0) != 0) {
+ MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0);
+ do {
+ Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
+ } while((Reg32 & BIT0) != 0);
+ DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index));
+ } else {
+ DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index));
+ }
+ }
+ return ;
+}
+
+/**
Enable DMAR translation.
@retval EFI_SUCCESS DMAR translation is enabled.
@@ -259,6 +292,11 @@ EnableDmar ( DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));
}
+ //
+ // Need disable PMR, since we already setup translation table.
+ //
+ DisablePmr ();
+
mVtdEnabled = TRUE;
return EFI_SUCCESS;
@@ -502,7 +540,7 @@ DumpVtdIfError ( for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
- if ((FrcdReg.Uint64[0] != 0) || (FrcdReg.Uint64[1] != 0)) {
+ if (FrcdReg.Bits.F != 0) {
HasError = TRUE;
}
}
@@ -511,6 +549,17 @@ DumpVtdIfError ( DEBUG((DEBUG_INFO, "\n#### ERROR ####\n"));
DumpVtdRegs (Num);
DEBUG((DEBUG_INFO, "#### ERROR ####\n\n"));
+ //
+ // Clear
+ //
+ for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
+ FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
+ if (FrcdReg.Bits.F != 0) {
+ FrcdReg.Bits.F = 0;
+ MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.Uint64[1]);
+ }
+ MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG));
+ }
}
}
}
|