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| author | Star Zeng <star.zeng@intel.com> | 2018-10-24 19:27:22 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-10-28 21:20:07 +0800 |
| commit | 4f792685e476dfd1e777033492207335ea804c9f (patch) | |
| tree | a34acc5dd1ad6c185bbe2a65abd19c24dc87bd2a /MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c | |
| parent | 6681582dcce3a08ce3cb3042b2f4a09e9d3c9d72 (diff) | |
| download | edk2-4f792685e476dfd1e777033492207335ea804c9f.tar.gz edk2-4f792685e476dfd1e777033492207335ea804c9f.tar.bz2 edk2-4f792685e476dfd1e777033492207335ea804c9f.zip | |
MdeModulePkg EhciDxe: Extract new EhciInsertAsyncIntTransfer function
V3:
Match function parameter name and description between
EhciSched.c and EhciSched.h.
V2:
Add the missing "gBS->FreePool (Data);".
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1274
Extract new EhciInsertAsyncIntTransfer function from
EhcAsyncInterruptTransfer.
It is code preparation for following patch,
no essential functional change.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c index 168280be81..ec8d796fab 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c @@ -814,6 +814,82 @@ EhciDelAllAsyncIntTransfers ( }
}
+/**
+ Insert a single asynchronous interrupt transfer for
+ the device and endpoint.
+
+ @param Ehc The EHCI device.
+ @param DevAddr The device address.
+ @param EpAddr Endpoint addrress & its direction.
+ @param DevSpeed The device speed.
+ @param Toggle Initial data toggle to use.
+ @param MaxPacket The max packet length of the endpoint.
+ @param Hub The transaction translator to use.
+ @param DataLen The length of data buffer.
+ @param Callback The function to call when data is transferred.
+ @param Context The context to the callback.
+ @param Interval The interval for interrupt transfer.
+
+ @return Created URB or NULL.
+
+**/
+URB *
+EhciInsertAsyncIntTransfer (
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
+ )
+{
+ VOID *Data;
+ URB *Urb;
+
+ Data = AllocatePool (DataLen);
+
+ if (Data == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: failed to allocate buffer\n", __FUNCTION__));
+ return NULL;
+ }
+
+ Urb = EhcCreateUrb (
+ Ehc,
+ DevAddr,
+ EpAddr,
+ DevSpeed,
+ Toggle,
+ MaxPacket,
+ Hub,
+ EHC_INT_TRANSFER_ASYNC,
+ NULL,
+ Data,
+ DataLen,
+ Callback,
+ Context,
+ Interval
+ );
+
+ if (Urb == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: failed to create URB\n", __FUNCTION__));
+ gBS->FreePool (Data);
+ return NULL;
+ }
+
+ //
+ // New asynchronous transfer must inserted to the head.
+ // Check the comments in EhcMoniteAsyncRequests
+ //
+ EhcLinkQhToPeriod (Ehc, Urb->Qh);
+ InsertHeadList (&Ehc->AsyncIntTransfers, &Urb->UrbList);
+
+ return Urb;
+}
/**
Flush data from PCI controller specific address to mapped system
|