diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:02 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 1436aea4d5707e672672a11bda72be2c63c936c3 (patch) | |
| tree | 370c9d5bd8823aa8ea7bce71a0f29bff71feff67 /MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | |
| parent | 7c7184e201a90a1d2376e615e55e3f4074731468 (diff) | |
| download | edk2-1436aea4d5707e672672a11bda72be2c63c936c3.tar.gz edk2-1436aea4d5707e672672a11bda72be2c63c936c3.tar.bz2 edk2-1436aea4d5707e672672a11bda72be2c63c936c3.zip | |
MdeModulePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the MdeModulePkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c index 68bfade9c2..ac42b1b796 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c @@ -11,7 +11,7 @@ EDKII_UFS_HOST_CONTROLLER_PPI mUfsHostControllerPpi = { GetUfsHcMmioBar };
-EFI_PEI_PPI_DESCRIPTOR mPpiList = {
+EFI_PEI_PPI_DESCRIPTOR mPpiList = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiPeiUfsHostControllerPpiGuid,
&mUfsHostControllerPpi
@@ -31,9 +31,9 @@ EFI_PEI_PPI_DESCRIPTOR mPpiList = { EFI_STATUS
EFIAPI
GetUfsHcMmioBar (
- IN EDKII_UFS_HOST_CONTROLLER_PPI *This,
- IN UINT8 ControllerId,
- OUT UINTN *MmioBar
+ IN EDKII_UFS_HOST_CONTROLLER_PPI *This,
+ IN UINT8 ControllerId,
+ OUT UINTN *MmioBar
)
{
UFS_HC_PEI_PRIVATE_DATA *Private;
@@ -66,8 +66,8 @@ GetUfsHcMmioBar ( EFI_STATUS
EFIAPI
InitializeUfsHcPeim (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_BOOT_MODE BootMode;
@@ -97,7 +97,7 @@ InitializeUfsHcPeim ( return EFI_SUCCESS;
}
- Private = (UFS_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (UFS_HC_PEI_PRIVATE_DATA));
+ Private = (UFS_HC_PEI_PRIVATE_DATA *)AllocateZeroPool (sizeof (UFS_HC_PEI_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((DEBUG_ERROR, "Failed to allocate memory for UFS_HC_PEI_PRIVATE_DATA! \n"));
return EFI_OUT_OF_RESOURCES;
@@ -119,7 +119,7 @@ InitializeUfsHcPeim ( //
// Get the Ufs Pci host controller's MMIO region size.
//
- PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
+ PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16) ~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
@@ -135,8 +135,8 @@ InitializeUfsHcPeim ( // Memory space: anywhere in 64 bit address space
//
MmioSize = Size & 0xFFFFFFF0;
- PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
- Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
+ PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
+ Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
//
// Fix the length to support some specific 64 bit BAR
@@ -146,7 +146,7 @@ InitializeUfsHcPeim ( //
// Calculate the size of 64bit bar
//
- MmioSize |= LShiftU64 ((UINT64) Size, 32);
+ MmioSize |= LShiftU64 ((UINT64)Size, 32);
MmioSize = (~(MmioSize)) + 1;
//
@@ -160,7 +160,8 @@ InitializeUfsHcPeim ( //
ASSERT (FALSE);
continue;
- };
+ }
+
//
// Assign resource to the Ufs Pci host controller's MMIO BAR.
// Enable the Ufs Pci host controller by setting BME and MSE bits of PCI_CMD register.
|