Fixed unexpected timeout in Usb MassStorage Driver.

Fixed unexpected timeout in Uhci/Ehci driver.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@4038 6f19259b-4bc3-4df7-8a09-765794883524

3 files changed, 45 insertions, 38 deletions

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
index 1dee976504..00108b87e2 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
@@ -56,44 +56,33 @@ UhciReset (
     //

     // Stop schedule and set the Global Reset bit in the command register

     //

-    UhciStopHc (Uhc, STALL_1_SECOND);

+    UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);

     UhciSetRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_GRESET);

 

-    //

-    // Wait 50ms for root port to let reset complete

-    // See UHCI spec page122 Reset signaling

-    //

-    gBS->Stall (ROOT_PORT_REST_TIME);

+    gBS->Stall (UHC_ROOT_PORT_RESET_STALL);

 

     //

     // Clear the Global Reset bit to zero.

     //

     UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_GRESET);

 

-    //

-    // UHCI spec page120 reset recovery time

-    //

-    gBS->Stall (PORT_RESET_RECOVERY_TIME);

+    gBS->Stall (UHC_ROOT_PORT_RECOVERY_STALL);

     break;

 

   case EFI_USB_HC_RESET_HOST_CONTROLLER:

     //

     // Stop schedule and set Host Controller Reset bit to 1

     //

-    UhciStopHc (Uhc, STALL_1_SECOND);

+    UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);

     UhciSetRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_HCRESET);

 

-    //

-    // this bit will be reset by Host Controller when reset is completed.

-    // wait 10ms to let reset complete

-    //

-    gBS->Stall (PORT_RESET_RECOVERY_TIME);

+    gBS->Stall (UHC_ROOT_PORT_RECOVERY_STALL);

     break;

 

   default:

     goto ON_INVAILD_PARAMETER;

   }

-

+  

   //

   // Delete all old transactions on the USB bus, then

   // reinitialize the frame list

@@ -103,13 +92,13 @@ UhciReset (
   UhciInitFrameList (Uhc);

 

   gBS->RestoreTPL (OldTpl);

-

+  

   return EFI_SUCCESS;

 

 ON_INVAILD_PARAMETER:

-

+  

   gBS->RestoreTPL (OldTpl);

-

+  

   return EFI_INVALID_PARAMETER;

 }

 

@@ -202,7 +191,7 @@ UhciSetState (
 

   switch (State) {

   case EfiUsbHcStateHalt:

-    Status = UhciStopHc (Uhc, STALL_1_SECOND);

+    Status = UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);

     break;

 

   case EfiUsbHcStateOperational:

@@ -224,11 +213,11 @@ UhciSetState (
         UsbCmd |= USBCMD_FGR;

         UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);

       }

-

+      

       //

       // wait 20ms to let resume complete (20ms is specified by UHCI spec)

       //

-      gBS->Stall (FORCE_GLOBAL_RESUME_TIME);

+      gBS->Stall (UHC_FORCE_GLOBAL_RESUME_STALL);

 

       //

       // Write FGR bit to 0 and EGSM(Enter Global Suspend Mode) bit to 0

@@ -248,7 +237,7 @@ UhciSetState (
       Status = EFI_DEVICE_ERROR;

       goto ON_EXIT;

     }

-

+    

     //

     // Set Enter Global Suspend Mode bit to 1.

     //

@@ -2084,7 +2073,7 @@ UhciCleanDevUp (
   // Uninstall the USB_HC and USB_HC2 protocol, then disable the controller

   //

   Uhc = UHC_FROM_USB_HC_PROTO (This);

-  UhciStopHc (Uhc, STALL_1_SECOND);

+  UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);

 

   gBS->UninstallProtocolInterface (

         Controller,

@@ -2188,7 +2177,7 @@ UhciDriverBindingStart (
   Status = gBS->SetTimer (

                   Uhc->AsyncIntMonitor,

                   TimerPeriodic,

-                  INTERRUPT_POLLING_TIME

+                  UHC_ASYNC_POLL_INTERVAL

                   );

 

   if (EFI_ERROR (Status)) {

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
index 3f2540faf7..e7b4447def 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
@@ -51,25 +51,43 @@ typedef struct _USB_HC_DEV  USB_HC_DEV;
 #include "UhciDebug.h"

 

 enum {

+  UHC_1_MICROSECOND             = 1,

+  UHC_1_MILLISECOND             = 1000 * UHC_1_MICROSECOND,

+  UHC_1_SECOND                  = 1000 * UHC_1_MILLISECOND,

+

+  //

+  // UHCI register operation timeout, set by experience

   //

-  // Stall times

+  UHC_GENERIC_TIMEOUT           = UHC_1_SECOND,

+  

   //

-  STALL_1_MS               = 1000,

-  STALL_1_SECOND           = 1000 *STALL_1_MS,

+  // Wait for force global resume(FGR) complete, refers to

+  // specification[UHCI11-2.1.1]

+  // 

+  UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,

 

-  UHC_SYN_POLL             = 50,

-  FORCE_GLOBAL_RESUME_TIME = 20 *STALL_1_MS,

-  ROOT_PORT_REST_TIME      = 50 *STALL_1_MS,

-  PORT_RESET_RECOVERY_TIME = 10 *STALL_1_MS,

-  INTERRUPT_POLLING_TIME   = 50 * 10000UL,

+  //

+  // Wait for roothub port reset and recovery, reset stall

+  // is set by experience, and recovery stall refers to 

+  // specification[UHCI11-2.1.1]

+  //

+  UHC_ROOT_PORT_RESET_STALL     = 50 * UHC_1_MILLISECOND,

+  UHC_ROOT_PORT_RECOVERY_STALL  = 10 * UHC_1_MILLISECOND,

 

   //

+  // Sync and Async transfer polling interval, set by experience, 

+  // and the unit of Async is 100us.

+  //

+  UHC_SYNC_POLL_INTERVAL        = 50 * UHC_1_MICROSECOND,

+  UHC_ASYNC_POLL_INTERVAL       = 50 * 10000UL,

+  

+  //

   // UHC raises TPL to TPL_NOTIFY to serialize all its operations

   // to protect shared data structures.

   //

   UHCI_TPL                 = TPL_NOTIFY,

 

-  USB_HC_DEV_SIGNATURE     = EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')

+  USB_HC_DEV_SIGNATURE          = EFI_SIGNATURE_32 ('u', 'h', 'c', 'i'),

 };

 

 #pragma pack(1)

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
index e1b602e7e2..401d32eb34 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
@@ -575,8 +575,8 @@ UhciExecuteTransfer (
 

   Finished = FALSE;

   Status   = EFI_SUCCESS;

-  Delay    = (TimeOut * STALL_1_MS / UHC_SYN_POLL) + 1;

-

+  Delay    = (TimeOut * UHC_1_MILLISECOND / UHC_SYNC_POLL_INTERVAL) + 1;

+  

   for (Index = 0; Index < Delay; Index++) {

     Finished = UhciCheckTdStatus (Uhc, Td, IsLow, QhResult);

 

@@ -587,7 +587,7 @@ UhciExecuteTransfer (
       break;

     }

 

-    gBS->Stall (UHC_SYN_POLL);

+    gBS->Stall (UHC_SYNC_POLL_INTERVAL);

   }

 

   if (!Finished) {