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author | Star Zeng <star.zeng@intel.com> | 2018-10-21 12:12:39 +0800 |
---|---|---|
committer | Star Zeng <star.zeng@intel.com> | 2018-10-23 11:17:31 +0800 |
commit | fed6cf25b8eefccf302f90f1fa7e54bf4a91b124 (patch) | |
tree | 8d0c235815e776a860a4b3f41df9e60796d6ed7a /MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | |
parent | a6a326770b0e9e209c604d26fd861a9714c36bef (diff) | |
download | edk2-fed6cf25b8eefccf302f90f1fa7e54bf4a91b124.tar.gz edk2-fed6cf25b8eefccf302f90f1fa7e54bf4a91b124.tar.bz2 edk2-fed6cf25b8eefccf302f90f1fa7e54bf4a91b124.zip |
MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN
Current hard code Usb2Hc.XXXRevision may be not accurate.
This patch updates code to assign Usb2Hc.XXXRevision based on
SBRN (Serial Bus Release Number, PCI configuration space offset
0x60) although there is no code consuming them.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c')
-rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c index 48eccf770a..4796d4611b 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -1770,6 +1770,7 @@ XhcCreateUsbHc ( EFI_STATUS Status;
UINT32 PageSize;
UINT16 ExtCapReg;
+ UINT8 ReleaseNumber;
Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE));
@@ -1786,6 +1787,19 @@ XhcCreateUsbHc ( Xhc->OriginalPciAttributes = OriginalPciAttributes;
CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof (EFI_USB2_HC_PROTOCOL));
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ XHC_PCI_SBRN_OFFSET,
+ 1,
+ &ReleaseNumber
+ );
+
+ if (!EFI_ERROR (Status)) {
+ Xhc->Usb2Hc.MajorRevision = (ReleaseNumber & 0xF0) >> 4;
+ Xhc->Usb2Hc.MinorRevision = (ReleaseNumber & 0x0F);
+ }
+
InitializeListHead (&Xhc->AsyncIntTransfers);
//
|