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| author | Vidya Sagar <vidyas@nvidia.com> | 2023-09-21 20:10:05 +0000 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-09-22 14:46:02 +0000 |
| commit | 8b2e6b90b85fd4b1f7f921da09b16f5175acea8a (patch) | |
| tree | 449541310ea37268b3ce12414b46ff785050d7aa /MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | |
| parent | 909e870e3405a983bc4c61622467e235053a4041 (diff) | |
| download | edk2-8b2e6b90b85fd4b1f7f921da09b16f5175acea8a.tar.gz edk2-8b2e6b90b85fd4b1f7f921da09b16f5175acea8a.tar.bz2 edk2-8b2e6b90b85fd4b1f7f921da09b16f5175acea8a.zip | |
DynamicTablesPkg: AcpiSsdtPcieLibArm: Use QWord to describe I/O range
Use AmlCodeGenRdQWordIo() to generate the I/O range in _CRS instead of
AmlCodeGenRdDWordIo() to cater to the scenarios where 64-bit addresses
can be used to generate I/O packets over the PCIe bus.
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c')
0 files changed, 0 insertions, 0 deletions