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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-05-31 10:56:35 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-06-02 14:23:29 +0800 |
| commit | b33b1055b0026f36be97fb5ec6826436088e9a23 (patch) | |
| tree | 4407203c9b6e3a2248b381183024b72c2b28e5c4 /MdeModulePkg/Bus/Pci/XhciDxe | |
| parent | 54d7177c78dc35919a631c8baa533d287bf0ae57 (diff) | |
| download | edk2-b33b1055b0026f36be97fb5ec6826436088e9a23.tar.gz edk2-b33b1055b0026f36be97fb5ec6826436088e9a23.tar.bz2 edk2-b33b1055b0026f36be97fb5ec6826436088e9a23.zip | |
MdeModulePkg/Xhci: Remove TRB when canceling Async Int Transfer
Some USB devices don't report data periodically through Int
Transfer. They report data only when be asked. If the TRB
is not removed from the XHCI HW, when next time HOST asks
data again, the data is reported but consumed by the previous
TRB, which results the HOST thinks data never comes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 58a2f984a9..9e34faf263 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -1319,6 +1319,7 @@ XhciDelAsyncIntTransfer ( LIST_ENTRY *Next;
URB *Urb;
EFI_USB_DATA_DIRECTION Direction;
+ EFI_STATUS Status;
Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
EpNum &= 0x0F;
@@ -1330,6 +1331,15 @@ XhciDelAsyncIntTransfer ( if ((Urb->Ep.BusAddr == BusAddr) &&
(Urb->Ep.EpAddr == EpNum) &&
(Urb->Ep.Direction == Direction)) {
+ //
+ // Device doesn't finish the IntTransfer until real data comes
+ // So the TRB should be removed as well.
+ //
+ Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
+ }
+
RemoveEntryList (&Urb->UrbList);
FreePool (Urb->Data);
XhcFreeUrb (Xhc, Urb);
@@ -1354,9 +1364,20 @@ XhciDelAllAsyncIntTransfers ( LIST_ENTRY *Entry;
LIST_ENTRY *Next;
URB *Urb;
+ EFI_STATUS Status;
EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
+
+ //
+ // Device doesn't finish the IntTransfer until real data comes
+ // So the TRB should be removed as well.
+ //
+ Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
+ }
+
RemoveEntryList (&Urb->UrbList);
FreePool (Urb->Data);
XhcFreeUrb (Xhc, Urb);
|