diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:02 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 1436aea4d5707e672672a11bda72be2c63c936c3 (patch) | |
| tree | 370c9d5bd8823aa8ea7bce71a0f29bff71feff67 /MdeModulePkg/Bus/Pci | |
| parent | 7c7184e201a90a1d2376e615e55e3f4074731468 (diff) | |
| download | edk2-1436aea4d5707e672672a11bda72be2c63c936c3.tar.gz edk2-1436aea4d5707e672672a11bda72be2c63c936c3.tar.bz2 edk2-1436aea4d5707e672672a11bda72be2c63c936c3.zip | |
MdeModulePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the MdeModulePkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'MdeModulePkg/Bus/Pci')
143 files changed, 18506 insertions, 17898 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.c index a2132d072b..ee83af2789 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.c @@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Ehci.h"
-
//
// EFI Component Name Protocol
//
@@ -22,19 +21,17 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName = //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) EhciComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) EhciComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)EhciComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)EhciComponentNameGetControllerName,
"en"
};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mEhciDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mEhciDriverNameTable[] = {
{ "eng;en", L"Usb Ehci Driver" },
- { NULL , NULL }
+ { NULL, NULL }
};
-
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -162,16 +159,16 @@ EhciComponentNameGetDriverName ( EFI_STATUS
EFIAPI
EhciComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
- USB2_HC_DEV *EhciDev;
- EFI_USB2_HC_PROTOCOL *Usb2Hc;
+ EFI_STATUS Status;
+ USB2_HC_DEV *EhciDev;
+ EFI_USB2_HC_PROTOCOL *Usb2Hc;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -179,6 +176,7 @@ EhciComponentNameGetControllerName ( if (ChildHandle != NULL) {
return EFI_UNSUPPORTED;
}
+
//
// Make sure this driver is currently managing ControllerHandle
//
@@ -190,13 +188,14 @@ EhciComponentNameGetControllerName ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Get the device context
//
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
gEhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -214,5 +213,4 @@ EhciComponentNameGetControllerName ( ControllerName,
(BOOLEAN)(This == &gEhciComponentName)
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.h b/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.h index 739592a6f6..d67cbf0709 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/ComponentName.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _COMPONENT_NAME_H_
#define _COMPONENT_NAME_H_
-
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -58,7 +57,6 @@ EhciComponentNameGetDriverName ( OUT CHAR16 **DriverName
);
-
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -130,12 +128,11 @@ EhciComponentNameGetDriverName ( EFI_STATUS
EFIAPI
EhciComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
#endif
-
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c index 0e41ee17ec..0b7270f4e9 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c @@ -16,7 +16,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#include "Ehci.h"
//
@@ -24,23 +23,23 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
- {PORTSC_CONN, USB_PORT_STAT_CONNECTION},
- {PORTSC_ENABLED, USB_PORT_STAT_ENABLE},
- {PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND},
- {PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT},
- {PORTSC_RESET, USB_PORT_STAT_RESET},
- {PORTSC_POWER, USB_PORT_STAT_POWER},
- {PORTSC_OWNER, USB_PORT_STAT_OWNER}
+ { PORTSC_CONN, USB_PORT_STAT_CONNECTION },
+ { PORTSC_ENABLED, USB_PORT_STAT_ENABLE },
+ { PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND },
+ { PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT },
+ { PORTSC_RESET, USB_PORT_STAT_RESET },
+ { PORTSC_POWER, USB_PORT_STAT_POWER },
+ { PORTSC_OWNER, USB_PORT_STAT_OWNER }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
- {PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION},
- {PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE},
- {PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT}
+ { PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION },
+ { PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE },
+ { PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT }
};
EFI_DRIVER_BINDING_PROTOCOL
-gEhciDriverBinding = {
+ gEhciDriverBinding = {
EhcDriverBindingSupported,
EhcDriverBindingStart,
EhcDriverBindingStop,
@@ -71,19 +70,19 @@ EhcGetCapability ( OUT UINT8 *Is64BitCapable
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
if ((MaxSpeed == NULL) || (PortNumber == NULL) || (Is64BitCapable == NULL)) {
return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
*MaxSpeed = EFI_USB_SPEED_HIGH;
- *PortNumber = (UINT8) (Ehc->HcStructParams & HCSP_NPORTS);
- *Is64BitCapable = (UINT8) Ehc->Support64BitDma;
+ *PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);
+ *Is64BitCapable = (UINT8)Ehc->Support64BitDma;
DEBUG ((DEBUG_INFO, "EhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
@@ -91,7 +90,6 @@ EhcGetCapability ( return EFI_SUCCESS;
}
-
/**
Provides software reset for the USB host controller.
@@ -108,13 +106,13 @@ EhcGetCapability ( EFI_STATUS
EFIAPI
EhcReset (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT16 Attributes
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT16 Attributes
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
Ehc = EHC_FROM_THIS (This);
@@ -129,55 +127,55 @@ EhcReset ( );
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
switch (Attributes) {
- case EFI_USB_HC_RESET_GLOBAL:
- //
- // Flow through, same behavior as Host Controller Reset
- //
- case EFI_USB_HC_RESET_HOST_CONTROLLER:
+ case EFI_USB_HC_RESET_GLOBAL:
//
- // Host Controller must be Halt when Reset it
+ // Flow through, same behavior as Host Controller Reset
//
- if (EhcIsDebugPortInUse (Ehc, NULL)) {
- Status = EFI_SUCCESS;
- goto ON_EXIT;
- }
+ case EFI_USB_HC_RESET_HOST_CONTROLLER:
+ //
+ // Host Controller must be Halt when Reset it
+ //
+ if (EhcIsDebugPortInUse (Ehc, NULL)) {
+ Status = EFI_SUCCESS;
+ goto ON_EXIT;
+ }
- if (!EhcIsHalt (Ehc)) {
- Status = EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
+ if (!EhcIsHalt (Ehc)) {
+ Status = EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
- if (EFI_ERROR (Status)) {
- Status = EFI_DEVICE_ERROR;
- goto ON_EXIT;
+ if (EFI_ERROR (Status)) {
+ Status = EFI_DEVICE_ERROR;
+ goto ON_EXIT;
+ }
}
- }
- //
- // Clean up the asynchronous transfers, currently only
- // interrupt supports asynchronous operation.
- //
- EhciDelAllAsyncIntTransfers (Ehc);
- EhcAckAllInterrupt (Ehc);
- EhcFreeSched (Ehc);
+ //
+ // Clean up the asynchronous transfers, currently only
+ // interrupt supports asynchronous operation.
+ //
+ EhciDelAllAsyncIntTransfers (Ehc);
+ EhcAckAllInterrupt (Ehc);
+ EhcFreeSched (Ehc);
- Status = EhcResetHC (Ehc, EHC_RESET_TIMEOUT);
+ Status = EhcResetHC (Ehc, EHC_RESET_TIMEOUT);
- if (EFI_ERROR (Status)) {
- goto ON_EXIT;
- }
+ if (EFI_ERROR (Status)) {
+ goto ON_EXIT;
+ }
- Status = EhcInitHC (Ehc);
- break;
+ Status = EhcInitHC (Ehc);
+ break;
- case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
- case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
- Status = EFI_UNSUPPORTED;
- break;
+ case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
+ case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
+ Status = EFI_UNSUPPORTED;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -186,7 +184,6 @@ ON_EXIT: return Status;
}
-
/**
Retrieve the current state of the USB host controller.
@@ -207,15 +204,15 @@ EhcGetState ( OUT EFI_USB_HC_STATE *State
)
{
- EFI_TPL OldTpl;
- USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ USB2_HC_DEV *Ehc;
if (State == NULL) {
return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
if (EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT)) {
*State = EfiUsbHcStateHalt;
@@ -229,7 +226,6 @@ EhcGetState ( return EFI_SUCCESS;
}
-
/**
Sets the USB host controller to a specific state.
@@ -245,14 +241,14 @@ EhcGetState ( EFI_STATUS
EFIAPI
EhcSetState (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN EFI_USB_HC_STATE State
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN EFI_USB_HC_STATE State
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
- EFI_USB_HC_STATE CurState;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ EFI_USB_HC_STATE CurState;
Status = EhcGetState (This, &CurState);
@@ -264,39 +260,39 @@ EhcSetState ( return EFI_SUCCESS;
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
switch (State) {
- case EfiUsbHcStateHalt:
- Status = EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
- break;
-
- case EfiUsbHcStateOperational:
- if (EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR)) {
- Status = EFI_DEVICE_ERROR;
+ case EfiUsbHcStateHalt:
+ Status = EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
break;
- }
- //
- // Software must not write a one to this field unless the host controller
- // is in the Halted state. Doing so will yield undefined results.
- // refers to Spec[EHCI1.0-2.3.1]
- //
- if (!EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT)) {
- Status = EFI_DEVICE_ERROR;
- break;
- }
+ case EfiUsbHcStateOperational:
+ if (EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
- Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
- break;
+ //
+ // Software must not write a one to this field unless the host controller
+ // is in the Halted state. Doing so will yield undefined results.
+ // refers to Spec[EHCI1.0-2.3.1]
+ //
+ if (!EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
- case EfiUsbHcStateSuspend:
- Status = EFI_UNSUPPORTED;
- break;
+ Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ case EfiUsbHcStateSuspend:
+ Status = EFI_UNSUPPORTED;
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
DEBUG ((DEBUG_INFO, "EhcSetState: exit status %r\n", Status));
@@ -304,7 +300,6 @@ EhcSetState ( return Status;
}
-
/**
Retrieves the current status of a USB root hub port.
@@ -327,23 +322,23 @@ EhcGetRootHubPortStatus ( OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- UINTN Index;
- UINTN MapSize;
- EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ UINTN Index;
+ UINTN MapSize;
+ EFI_STATUS Status;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ Ehc = EHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -352,15 +347,15 @@ EhcGetRootHubPortStatus ( goto ON_EXIT;
}
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
- PortStatus->PortStatus = 0;
- PortStatus->PortChangeStatus = 0;
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
+ PortStatus->PortStatus = 0;
+ PortStatus->PortChangeStatus = 0;
if (EhcIsDebugPortInUse (Ehc, &PortNumber)) {
goto ON_EXIT;
}
- State = EhcReadOpReg (Ehc, Offset);
+ State = EhcReadOpReg (Ehc, Offset);
//
// Identify device speed. If in K state, it is low speed.
@@ -370,7 +365,6 @@ EhcGetRootHubPortStatus ( //
if (EHC_BIT_IS_SET (State, PORTSC_LINESTATE_K)) {
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
-
} else if (EHC_BIT_IS_SET (State, PORTSC_ENABLED)) {
PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
}
@@ -382,7 +376,7 @@ EhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
@@ -390,7 +384,7 @@ EhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -399,7 +393,6 @@ ON_EXIT: return Status;
}
-
/**
Sets a feature for the specified root hub port.
@@ -420,16 +413,16 @@ EhcSetRootHubPortFeature ( IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
-
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -438,8 +431,8 @@ EhcSetRootHubPortFeature ( goto ON_EXIT;
}
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
- State = EhcReadOpReg (Ehc, Offset);
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
+ State = EhcReadOpReg (Ehc, Offset);
//
// Mask off the port status change bits, these bits are
@@ -448,58 +441,59 @@ EhcSetRootHubPortFeature ( State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Sofeware can't set this bit, Port can only be enable by
- // EHCI as a part of the reset and enable
- //
- State |= PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnable:
+ //
+ // Sofeware can't set this bit, Port can only be enable by
+ // EHCI as a part of the reset and enable
+ //
+ State |= PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortSuspend:
- State |= PORTSC_SUSPEND;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ State |= PORTSC_SUSPEND;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortReset:
- //
- // Make sure Host Controller not halt before reset it
- //
- if (EhcIsHalt (Ehc)) {
- Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
+ case EfiUsbPortReset:
+ //
+ // Make sure Host Controller not halt before reset it
+ //
+ if (EhcIsHalt (Ehc)) {
+ Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "EhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
- break;
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "EhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
+ break;
+ }
}
- }
-
- //
- // Set one to PortReset bit must also set zero to PortEnable bit
- //
- State |= PORTSC_RESET;
- State &= ~PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
- case EfiUsbPortPower:
- //
- // Set port power bit when PPC is 1
- //
- if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {
- State |= PORTSC_POWER;
+ //
+ // Set one to PortReset bit must also set zero to PortEnable bit
+ //
+ State |= PORTSC_RESET;
+ State &= ~PORTSC_ENABLED;
EhcWriteOpReg (Ehc, Offset, State);
- }
- break;
+ break;
- case EfiUsbPortOwner:
- State |= PORTSC_OWNER;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortPower:
+ //
+ // Set port power bit when PPC is 1
+ //
+ if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {
+ State |= PORTSC_POWER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ }
- default:
- Status = EFI_INVALID_PARAMETER;
+ break;
+
+ case EfiUsbPortOwner:
+ State |= PORTSC_OWNER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -509,7 +503,6 @@ ON_EXIT: return Status;
}
-
/**
Clears a feature for the specified root hub port.
@@ -533,16 +526,16 @@ EhcClearRootHubPortFeature ( IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
-
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -551,90 +544,91 @@ EhcClearRootHubPortFeature ( goto ON_EXIT;
}
- Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
- State = EhcReadOpReg (Ehc, Offset);
+ Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
+ State = EhcReadOpReg (Ehc, Offset);
State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Clear PORT_ENABLE feature means disable port.
- //
- State &= ~PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
-
- case EfiUsbPortSuspend:
- //
- // A write of zero to this bit is ignored by the host
- // controller. The host controller will unconditionally
- // set this bit to a zero when:
- // 1. software sets the Forct Port Resume bit to a zero from a one.
- // 2. software sets the Port Reset bit to a one frome a zero.
- //
- State &= ~PORSTSC_RESUME;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnable:
+ //
+ // Clear PORT_ENABLE feature means disable port.
+ //
+ State &= ~PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortReset:
- //
- // Clear PORT_RESET means clear the reset signal.
- //
- State &= ~PORTSC_RESET;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ //
+ // A write of zero to this bit is ignored by the host
+ // controller. The host controller will unconditionally
+ // set this bit to a zero when:
+ // 1. software sets the Forct Port Resume bit to a zero from a one.
+ // 2. software sets the Port Reset bit to a one frome a zero.
+ //
+ State &= ~PORSTSC_RESUME;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortOwner:
- //
- // Clear port owner means this port owned by EHC
- //
- State &= ~PORTSC_OWNER;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortReset:
+ //
+ // Clear PORT_RESET means clear the reset signal.
+ //
+ State &= ~PORTSC_RESET;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortConnectChange:
- //
- // Clear connect status change
- //
- State |= PORTSC_CONN_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortOwner:
+ //
+ // Clear port owner means this port owned by EHC
+ //
+ State &= ~PORTSC_OWNER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortEnableChange:
- //
- // Clear enable status change
- //
- State |= PORTSC_ENABLE_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortConnectChange:
+ //
+ // Clear connect status change
+ //
+ State |= PORTSC_CONN_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortOverCurrentChange:
- //
- // Clear PortOverCurrent change
- //
- State |= PORTSC_OVERCUR_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnableChange:
+ //
+ // Clear enable status change
+ //
+ State |= PORTSC_ENABLE_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortPower:
- //
- // Clear port power bit when PPC is 1
- //
- if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {
- State &= ~PORTSC_POWER;
+ case EfiUsbPortOverCurrentChange:
+ //
+ // Clear PortOverCurrent change
+ //
+ State |= PORTSC_OVERCUR_CHANGE;
EhcWriteOpReg (Ehc, Offset, State);
- }
- break;
- case EfiUsbPortSuspendChange:
- case EfiUsbPortResetChange:
- //
- // Not supported or not related operation
- //
- break;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
+ case EfiUsbPortPower:
+ //
+ // Clear port power bit when PPC is 1
+ //
+ if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {
+ State &= ~PORTSC_POWER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ }
+
+ break;
+ case EfiUsbPortSuspendChange:
+ case EfiUsbPortResetChange:
+ //
+ // Not supported or not related operation
+ //
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
+ break;
}
ON_EXIT:
@@ -643,7 +637,6 @@ ON_EXIT: return Status;
}
-
/**
Submits control transfer to a target USB device.
@@ -684,11 +677,11 @@ EhcControlTransfer ( OUT UINT32 *TransferResult
)
{
- USB2_HC_DEV *Ehc;
- URB *Urb;
- EFI_TPL OldTpl;
- UINT8 Endpoint;
- EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ URB *Urb;
+ EFI_TPL OldTpl;
+ UINT8 Endpoint;
+ EFI_STATUS Status;
//
// Validate parameters
@@ -699,22 +692,26 @@ EhcControlTransfer ( if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
- (TransferDirection != EfiUsbNoData)) {
+ (TransferDirection != EfiUsbNoData))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
- ((Data != NULL) || (*DataLength != 0))) {
+ ((Data != NULL) || (*DataLength != 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
- ((Data == NULL) || (*DataLength == 0))) {
+ ((Data == NULL) || (*DataLength == 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
- (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {
+ (MaximumPacketLength != 32) && (MaximumPacketLength != 64))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -722,8 +719,8 @@ EhcControlTransfer ( return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
@@ -746,23 +743,23 @@ EhcControlTransfer ( // endpoint is bidirectional. EhcCreateUrb expects this
// combination of Ep addr and its direction.
//
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
- Urb = EhcCreateUrb (
- Ehc,
- DeviceAddress,
- Endpoint,
- DeviceSpeed,
- 0,
- MaximumPacketLength,
- Translator,
- EHC_CTRL_TRANSFER,
- Request,
- Data,
- *DataLength,
- NULL,
- NULL,
- 1
- );
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
+ Urb = EhcCreateUrb (
+ Ehc,
+ DeviceAddress,
+ Endpoint,
+ DeviceSpeed,
+ 0,
+ MaximumPacketLength,
+ Translator,
+ EHC_CTRL_TRANSFER,
+ Request,
+ Data,
+ *DataLength,
+ NULL,
+ NULL,
+ 1
+ );
if (Urb == NULL) {
DEBUG ((DEBUG_ERROR, "EhcControlTransfer: failed to create URB"));
@@ -800,7 +797,6 @@ ON_EXIT: return Status;
}
-
/**
Submits bulk transfer to a bulk endpoint of a USB device.
@@ -848,16 +844,17 @@ EhcBulkTransfer ( OUT UINT32 *TransferResult
)
{
- USB2_HC_DEV *Ehc;
- URB *Urb;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ URB *Urb;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -867,12 +864,13 @@ EhcBulkTransfer ( if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {
+ ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))
+ {
return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -940,7 +938,6 @@ ON_EXIT: return Status;
}
-
/**
Submits an asynchronous interrupt transfer to an
interrupt endpoint of a USB device.
@@ -973,24 +970,24 @@ ON_EXIT: EFI_STATUS
EFIAPI
EhcAsyncInterruptTransfer (
- IN EFI_USB2_HC_PROTOCOL * This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN BOOLEAN IsNewTransfer,
- IN OUT UINT8 *DataToggle,
- IN UINTN PollingInterval,
- IN UINTN DataLength,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR * Translator,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,
- IN VOID *Context OPTIONAL
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN BOOLEAN IsNewTransfer,
+ IN OUT UINT8 *DataToggle,
+ IN UINTN PollingInterval,
+ IN UINTN DataLength,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,
+ IN VOID *Context OPTIONAL
)
{
- USB2_HC_DEV *Ehc;
- URB *Urb;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ URB *Urb;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
//
// Validate parameters
@@ -1013,8 +1010,8 @@ EhcAsyncInterruptTransfer ( }
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
//
// Delete Async interrupt transfer request. DataToggle will return
@@ -1065,7 +1062,6 @@ ON_EXIT: return Status;
}
-
/**
Submits synchronous interrupt transfer to an interrupt endpoint
of a USB device.
@@ -1109,16 +1105,17 @@ EhcSyncInterruptTransfer ( OUT UINT32 *TransferResult
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
- URB *Urb;
- EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ URB *Urb;
+ EFI_STATUS Status;
//
// Validates parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1128,12 +1125,13 @@ EhcSyncInterruptTransfer ( if (((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072))) {
+ ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072)))
+ {
return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = EHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -1195,7 +1193,6 @@ ON_EXIT: return Status;
}
-
/**
Submits isochronous transfer to a target USB device.
@@ -1235,7 +1232,6 @@ EhcIsochronousTransfer ( return EFI_UNSUPPORTED;
}
-
/**
Submits Async isochronous transfer to a target USB device.
@@ -1291,8 +1287,8 @@ EhcAsyncIsochronousTransfer ( EFI_STATUS
EFIAPI
EhcDriverEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
return EfiLibInstallDriverBindingComponentName2 (
@@ -1305,7 +1301,6 @@ EhcDriverEntryPoint ( );
}
-
/**
Test to see if this driver supports ControllerHandle. Any
ControllerHandle that has Usb2HcProtocol installed will
@@ -1322,14 +1317,14 @@ EhcDriverEntryPoint ( EFI_STATUS
EFIAPI
EhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- USB_CLASSC UsbClassCReg;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ USB_CLASSC UsbClassCReg;
//
// Test whether there is PCI IO Protocol attached on the controller handle.
@@ -1337,7 +1332,7 @@ EhcDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1363,9 +1358,9 @@ EhcDriverBindingSupported ( //
// Test whether the controller belongs to Ehci type
//
- if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB)
- || ((UsbClassCReg.ProgInterface != PCI_IF_EHCI) && (UsbClassCReg.ProgInterface != PCI_IF_UHCI) && (UsbClassCReg.ProgInterface != PCI_IF_OHCI))) {
-
+ if ( (UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB)
+ || ((UsbClassCReg.ProgInterface != PCI_IF_EHCI) && (UsbClassCReg.ProgInterface != PCI_IF_UHCI) && (UsbClassCReg.ProgInterface != PCI_IF_OHCI)))
+ {
Status = EFI_UNSUPPORTED;
}
@@ -1391,15 +1386,15 @@ ON_EXIT: **/
EFI_STATUS
EhcGetUsbDebugPortInfo (
- IN USB2_HC_DEV *Ehc
- )
+ IN USB2_HC_DEV *Ehc
+ )
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 PciStatus;
- UINT8 CapabilityPtr;
- UINT8 CapabilityId;
- UINT16 DebugPort;
- EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 PciStatus;
+ UINT8 CapabilityPtr;
+ UINT8 CapabilityId;
+ UINT16 DebugPort;
+ EFI_STATUS Status;
ASSERT (Ehc->PciIo != NULL);
PciIo = Ehc->PciIo;
@@ -1503,7 +1498,6 @@ EhcGetUsbDebugPortInfo ( return EFI_SUCCESS;
}
-
/**
Create and initialize a USB2_HC_DEV.
@@ -1522,8 +1516,8 @@ EhcCreateUsb2Hc ( IN UINT64 OriginalPciAttributes
)
{
- USB2_HC_DEV *Ehc;
- EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ EFI_STATUS Status;
Ehc = AllocateZeroPool (sizeof (USB2_HC_DEV));
@@ -1534,23 +1528,23 @@ EhcCreateUsb2Hc ( //
// Init EFI_USB2_HC_PROTOCOL interface and private data structure
//
- Ehc->Signature = USB2_HC_DEV_SIGNATURE;
-
- Ehc->Usb2Hc.GetCapability = EhcGetCapability;
- Ehc->Usb2Hc.Reset = EhcReset;
- Ehc->Usb2Hc.GetState = EhcGetState;
- Ehc->Usb2Hc.SetState = EhcSetState;
- Ehc->Usb2Hc.ControlTransfer = EhcControlTransfer;
- Ehc->Usb2Hc.BulkTransfer = EhcBulkTransfer;
- Ehc->Usb2Hc.AsyncInterruptTransfer = EhcAsyncInterruptTransfer;
- Ehc->Usb2Hc.SyncInterruptTransfer = EhcSyncInterruptTransfer;
- Ehc->Usb2Hc.IsochronousTransfer = EhcIsochronousTransfer;
- Ehc->Usb2Hc.AsyncIsochronousTransfer = EhcAsyncIsochronousTransfer;
- Ehc->Usb2Hc.GetRootHubPortStatus = EhcGetRootHubPortStatus;
- Ehc->Usb2Hc.SetRootHubPortFeature = EhcSetRootHubPortFeature;
- Ehc->Usb2Hc.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
- Ehc->Usb2Hc.MajorRevision = 0x2;
- Ehc->Usb2Hc.MinorRevision = 0x0;
+ Ehc->Signature = USB2_HC_DEV_SIGNATURE;
+
+ Ehc->Usb2Hc.GetCapability = EhcGetCapability;
+ Ehc->Usb2Hc.Reset = EhcReset;
+ Ehc->Usb2Hc.GetState = EhcGetState;
+ Ehc->Usb2Hc.SetState = EhcSetState;
+ Ehc->Usb2Hc.ControlTransfer = EhcControlTransfer;
+ Ehc->Usb2Hc.BulkTransfer = EhcBulkTransfer;
+ Ehc->Usb2Hc.AsyncInterruptTransfer = EhcAsyncInterruptTransfer;
+ Ehc->Usb2Hc.SyncInterruptTransfer = EhcSyncInterruptTransfer;
+ Ehc->Usb2Hc.IsochronousTransfer = EhcIsochronousTransfer;
+ Ehc->Usb2Hc.AsyncIsochronousTransfer = EhcAsyncIsochronousTransfer;
+ Ehc->Usb2Hc.GetRootHubPortStatus = EhcGetRootHubPortStatus;
+ Ehc->Usb2Hc.SetRootHubPortFeature = EhcSetRootHubPortFeature;
+ Ehc->Usb2Hc.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
+ Ehc->Usb2Hc.MajorRevision = 0x2;
+ Ehc->Usb2Hc.MinorRevision = 0x0;
Ehc->PciIo = PciIo;
Ehc->DevicePath = DevicePath;
@@ -1603,14 +1597,14 @@ EhcCreateUsb2Hc ( VOID
EFIAPI
EhcExitBootService (
- EFI_EVENT Event,
- VOID *Context
+ EFI_EVENT Event,
+ VOID *Context
)
{
- USB2_HC_DEV *Ehc;
+ USB2_HC_DEV *Ehc;
- Ehc = (USB2_HC_DEV *) Context;
+ Ehc = (USB2_HC_DEV *)Context;
//
// Reset the Host Controller
@@ -1618,7 +1612,6 @@ EhcExitBootService ( EhcResetHC (Ehc, EHC_RESET_TIMEOUT);
}
-
/**
Starting the Usb EHCI Driver.
@@ -1635,30 +1628,30 @@ EhcExitBootService ( EFI_STATUS
EFIAPI
EhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- USB2_HC_DEV *Ehc;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_PCI_IO_PROTOCOL *Instance;
- UINT64 Supports;
- UINT64 OriginalPciAttributes;
- BOOLEAN PciAttributesSaved;
- USB_CLASSC UsbClassCReg;
- EFI_HANDLE *HandleBuffer;
- UINTN NumberOfHandles;
- UINTN Index;
- UINTN CompanionSegmentNumber;
- UINTN CompanionBusNumber;
- UINTN CompanionDeviceNumber;
- UINTN CompanionFunctionNumber;
- UINTN EhciSegmentNumber;
- UINTN EhciBusNumber;
- UINTN EhciDeviceNumber;
- UINTN EhciFunctionNumber;
+ EFI_STATUS Status;
+ USB2_HC_DEV *Ehc;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *Instance;
+ UINT64 Supports;
+ UINT64 OriginalPciAttributes;
+ BOOLEAN PciAttributesSaved;
+ USB_CLASSC UsbClassCReg;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ UINTN Index;
+ UINTN CompanionSegmentNumber;
+ UINTN CompanionBusNumber;
+ UINTN CompanionDeviceNumber;
+ UINTN CompanionFunctionNumber;
+ UINTN EhciSegmentNumber;
+ UINTN EhciBusNumber;
+ UINTN EhciDeviceNumber;
+ UINTN EhciFunctionNumber;
EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;
//
@@ -1667,7 +1660,7 @@ EhcDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1681,14 +1674,14 @@ EhcDriverBindingStart ( // Open Device Path Protocol for on USB host controller
//
HcDevicePath = NULL;
- Status = gBS->OpenProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- (VOID **) &HcDevicePath,
- This->DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL
- );
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&HcDevicePath,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
PciAttributesSaved = FALSE;
//
@@ -1704,6 +1697,7 @@ EhcDriverBindingStart ( if (EFI_ERROR (Status)) {
goto CLOSE_PCIIO;
}
+
PciAttributesSaved = TRUE;
Status = PciIo->Attributes (
@@ -1714,12 +1708,12 @@ EhcDriverBindingStart ( );
if (!EFI_ERROR (Status)) {
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
- Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
}
if (EFI_ERROR (Status)) {
@@ -1742,21 +1736,23 @@ EhcDriverBindingStart ( Status = EFI_UNSUPPORTED;
goto CLOSE_PCIIO;
}
+
//
// Determine if the device is UHCI or OHCI host controller or not. If yes, then find out the
// companion usb ehci host controller and force EHCI driver get attached to it before
// UHCI or OHCI driver attaches to UHCI or OHCI host controller.
//
- if ((UsbClassCReg.ProgInterface == PCI_IF_UHCI || UsbClassCReg.ProgInterface == PCI_IF_OHCI) &&
- (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
- (UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
+ if (((UsbClassCReg.ProgInterface == PCI_IF_UHCI) || (UsbClassCReg.ProgInterface == PCI_IF_OHCI)) &&
+ (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
+ (UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB))
+ {
Status = PciIo->GetLocation (
- PciIo,
- &CompanionSegmentNumber,
- &CompanionBusNumber,
- &CompanionDeviceNumber,
- &CompanionFunctionNumber
- );
+ PciIo,
+ &CompanionSegmentNumber,
+ &CompanionBusNumber,
+ &CompanionDeviceNumber,
+ &CompanionFunctionNumber
+ );
if (EFI_ERROR (Status)) {
goto CLOSE_PCIIO;
}
@@ -1777,19 +1773,19 @@ EhcDriverBindingStart ( // Get the device path on this handle
//
Status = gBS->HandleProtocol (
- HandleBuffer[Index],
- &gEfiPciIoProtocolGuid,
- (VOID **)&Instance
- );
+ HandleBuffer[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID **)&Instance
+ );
ASSERT_EFI_ERROR (Status);
Status = Instance->Pci.Read (
- Instance,
- EfiPciIoWidthUint8,
- PCI_CLASSCODE_OFFSET,
- sizeof (USB_CLASSC) / sizeof (UINT8),
- &UsbClassCReg
- );
+ Instance,
+ EfiPciIoWidthUint8,
+ PCI_CLASSCODE_OFFSET,
+ sizeof (USB_CLASSC) / sizeof (UINT8),
+ &UsbClassCReg
+ );
if (EFI_ERROR (Status)) {
Status = EFI_UNSUPPORTED;
@@ -1797,33 +1793,36 @@ EhcDriverBindingStart ( }
if ((UsbClassCReg.ProgInterface == PCI_IF_EHCI) &&
- (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
- (UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
+ (UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
+ (UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB))
+ {
Status = Instance->GetLocation (
- Instance,
- &EhciSegmentNumber,
- &EhciBusNumber,
- &EhciDeviceNumber,
- &EhciFunctionNumber
- );
+ Instance,
+ &EhciSegmentNumber,
+ &EhciBusNumber,
+ &EhciDeviceNumber,
+ &EhciFunctionNumber
+ );
if (EFI_ERROR (Status)) {
goto CLOSE_PCIIO;
}
+
//
// Currently, the judgment on the companion usb host controller is through the
// same bus number, which may vary on different platform.
//
if (EhciBusNumber == CompanionBusNumber) {
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
- EhcDriverBindingStart(This, HandleBuffer[Index], NULL);
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+ EhcDriverBindingStart (This, HandleBuffer[Index], NULL);
}
}
}
+
Status = EFI_NOT_FOUND;
goto CLOSE_PCIIO;
}
@@ -1854,9 +1853,13 @@ EhcDriverBindingStart ( if (!EFI_ERROR (Status)) {
Ehc->Support64BitDma = TRUE;
} else {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
- __FUNCTION__, Controller, Status));
+ __FUNCTION__,
+ Controller,
+ Status
+ ));
}
}
@@ -1937,7 +1940,6 @@ EhcDriverBindingStart ( FALSE
);
-
DEBUG ((DEBUG_INFO, "EhcDriverBindingStart: EHCI started for controller @ %p\n", Controller));
return EFI_SUCCESS;
@@ -1959,11 +1961,11 @@ CLOSE_PCIIO: // Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ OriginalPciAttributes,
+ NULL
+ );
}
gBS->CloseProtocol (
@@ -1976,7 +1978,6 @@ CLOSE_PCIIO: return Status;
}
-
/**
Stop this driver on ControllerHandle. Support stopping any child handles
created by this driver.
@@ -1993,10 +1994,10 @@ CLOSE_PCIIO: EFI_STATUS
EFIAPI
EhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -2012,7 +2013,7 @@ EhcDriverBindingStop ( Status = gBS->OpenProtocol (
Controller,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -2066,11 +2067,11 @@ EhcDriverBindingStop ( // Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- Ehc->OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ Ehc->OriginalPciAttributes,
+ NULL
+ );
gBS->CloseProtocol (
Controller,
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h index 65933d9439..393cc209dc 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h @@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_H_
#define _EFI_EHCI_H_
-
#include <Uefi.h>
#include <Protocol/Usb2HostController.h>
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <IndustryStandard/Pci.h>
-typedef struct _USB2_HC_DEV USB2_HC_DEV;
+typedef struct _USB2_HC_DEV USB2_HC_DEV;
#include "UsbHcMem.h"
#include "EhciReg.h"
@@ -44,64 +43,63 @@ typedef struct _USB2_HC_DEV USB2_HC_DEV; // EHC timeout experience values
//
-#define EHC_1_MICROSECOND 1
-#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
-#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
+#define EHC_1_MICROSECOND 1
+#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
+#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
//
// EHCI register operation timeout, set by experience
//
-#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
-#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
+#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
+#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
-#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
+#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
//
// Sync and Async transfer polling interval, set by experience,
// and the unit of Async is 100us, means 1ms as interval.
//
-#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
-#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
+#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
+#define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// EHCI debug port control status register bit definition
//
-#define USB_DEBUG_PORT_IN_USE BIT10
-#define USB_DEBUG_PORT_ENABLE BIT28
-#define USB_DEBUG_PORT_OWNER BIT30
-#define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \
+#define USB_DEBUG_PORT_IN_USE BIT10
+#define USB_DEBUG_PORT_ENABLE BIT28
+#define USB_DEBUG_PORT_OWNER BIT30
+#define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \
USB_DEBUG_PORT_OWNER)
//
// EHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
-#define EHC_TPL TPL_NOTIFY
-
-#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
+#define EHC_TPL TPL_NOTIFY
+#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
-#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
-#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
+#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
+#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
(EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
#define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
-#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
+#define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
struct _USB2_HC_DEV {
- UINTN Signature;
- EFI_USB2_HC_PROTOCOL Usb2Hc;
+ UINTN Signature;
+ EFI_USB2_HC_PROTOCOL Usb2Hc;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- UINT64 OriginalPciAttributes;
- USBHC_MEM_POOL *MemPool;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINT64 OriginalPciAttributes;
+ USBHC_MEM_POOL *MemPool;
//
// Schedule data shared between asynchronous and periodic
@@ -112,58 +110,57 @@ struct _USB2_HC_DEV { // For control transfer, even the short read happens, try the
// status stage.
//
- EHC_QTD *ShortReadStop;
- EFI_EVENT PollTimer;
+ EHC_QTD *ShortReadStop;
+ EFI_EVENT PollTimer;
//
// ExitBootServicesEvent is used to stop the EHC DMA operation
// after exit boot service.
//
- EFI_EVENT ExitBootServiceEvent;
+ EFI_EVENT ExitBootServiceEvent;
//
// Asynchronous(bulk and control) transfer schedule data:
// ReclaimHead is used as the head of the asynchronous transfer
// list. It acts as the reclamation header.
//
- EHC_QH *ReclaimHead;
+ EHC_QH *ReclaimHead;
//
// Periodic (interrupt) transfer schedule data:
//
- VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
- VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
- VOID *PeriodFrameMap;
+ VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
+ VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
+ VOID *PeriodFrameMap;
- EHC_QH *PeriodOne;
- LIST_ENTRY AsyncIntTransfers;
+ EHC_QH *PeriodOne;
+ LIST_ENTRY AsyncIntTransfers;
//
// EHCI configuration data
//
- UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
- UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
- UINT32 CapLen; // Capability length
+ UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
+ UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
+ UINT32 CapLen; // Capability length
//
// Misc
//
- EFI_UNICODE_STRING_TABLE *ControllerNameTable;
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// EHCI debug port info
//
- UINT16 DebugPortOffset; // The offset of debug port mmio register
- UINT8 DebugPortBarNum; // The bar number of debug port mmio register
- UINT8 DebugPortNum; // The port number of usb debug port
+ UINT16 DebugPortOffset; // The offset of debug port mmio register
+ UINT8 DebugPortBarNum; // The bar number of debug port mmio register
+ UINT8 DebugPortNum; // The port number of usb debug port
- BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
+ BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};
-
-extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
-extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;
/**
Test to see if this driver supports ControllerHandle. Any
@@ -181,9 +178,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2; EFI_STATUS
EFIAPI
EhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -202,9 +199,9 @@ EhcDriverBindingSupported ( EFI_STATUS
EFIAPI
EhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -223,11 +220,10 @@ EhcDriverBindingStart ( EFI_STATUS
EFIAPI
EhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
#endif
-
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c index 55cbb68570..79888bf3a5 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c @@ -8,7 +8,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#include "Ehci.h"
/**
@@ -19,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
EhcDumpStatus (
- IN UINT32 State
+ IN UINT32 State
)
{
if (EHC_BIT_IS_SET (State, QTD_STAT_DO_PING)) {
@@ -57,7 +56,6 @@ EhcDumpStatus ( DEBUG ((DEBUG_VERBOSE, "\n"));
}
-
/**
Dump the fields of a QTD.
@@ -67,12 +65,12 @@ EhcDumpStatus ( **/
VOID
EhcDumpQtd (
- IN EHC_QTD *Qtd,
- IN CHAR8 *Msg
+ IN EHC_QTD *Qtd,
+ IN CHAR8 *Msg
)
{
- QTD_HW *QtdHw;
- UINTN Index;
+ QTD_HW *QtdHw;
+ UINTN Index;
if (Msg != NULL) {
DEBUG ((DEBUG_VERBOSE, Msg));
@@ -89,13 +87,10 @@ EhcDumpQtd ( if (QtdHw->Pid == QTD_PID_SETUP) {
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
-
} else if (QtdHw->Pid == QTD_PID_INPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
-
} else if (QtdHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
-
}
DEBUG ((DEBUG_VERBOSE, "Error Count : %d\n", QtdHw->ErrCnt));
@@ -109,7 +104,6 @@ EhcDumpQtd ( }
}
-
/**
Dump the queue head.
@@ -120,22 +114,27 @@ EhcDumpQtd ( **/
VOID
EhcDumpQh (
- IN EHC_QH *Qh,
- IN CHAR8 *Msg,
- IN BOOLEAN DumpBuf
+ IN EHC_QH *Qh,
+ IN CHAR8 *Msg,
+ IN BOOLEAN DumpBuf
)
{
- EHC_QTD *Qtd;
- QH_HW *QhHw;
- LIST_ENTRY *Entry;
- UINTN Index;
+ EHC_QTD *Qtd;
+ QH_HW *QhHw;
+ LIST_ENTRY *Entry;
+ UINTN Index;
if (Msg != NULL) {
DEBUG ((DEBUG_VERBOSE, Msg));
}
- DEBUG ((DEBUG_VERBOSE, "Queue head @ 0x%p, interval %ld, next qh %p\n",
- Qh, (UINT64)Qh->Interval, Qh->NextQh));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "Queue head @ 0x%p, interval %ld, next qh %p\n",
+ Qh,
+ (UINT64)Qh->Interval,
+ Qh->NextQh
+ ));
QhHw = &Qh->QhHw;
@@ -166,10 +165,8 @@ EhcDumpQh ( if (QhHw->Pid == QTD_PID_SETUP) {
DEBUG ((DEBUG_VERBOSE, "PID : Setup\n"));
-
} else if (QhHw->Pid == QTD_PID_INPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : IN\n"));
-
} else if (QhHw->Pid == QTD_PID_OUTPUT) {
DEBUG ((DEBUG_VERBOSE, "PID : OUT\n"));
}
@@ -196,7 +193,6 @@ EhcDumpQh ( }
}
-
/**
Dump the buffer in the form of hex.
@@ -206,15 +202,15 @@ EhcDumpQh ( **/
VOID
EhcDumpBuf (
- IN UINT8 *Buf,
- IN UINTN Len
+ IN UINT8 *Buf,
+ IN UINTN Len
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Len; Index++) {
if (Index % 16 == 0) {
- DEBUG ((DEBUG_VERBOSE,"\n"));
+ DEBUG ((DEBUG_VERBOSE, "\n"));
}
DEBUG ((DEBUG_VERBOSE, "%02x ", Buf[Index]));
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h index eff85dcec8..2ed2d46f96 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_DEBUG_H_
#define _EFI_EHCI_DEBUG_H_
-
/**
Dump the fields of a QTD.
@@ -20,11 +19,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
EhcDumpQtd (
- IN EHC_QTD *Qtd,
- IN CHAR8 *Msg
+ IN EHC_QTD *Qtd,
+ IN CHAR8 *Msg
);
-
/**
Dump the queue head.
@@ -35,12 +33,11 @@ EhcDumpQtd ( **/
VOID
EhcDumpQh (
- IN EHC_QH *Qh,
- IN CHAR8 *Msg,
- IN BOOLEAN DumpBuf
+ IN EHC_QH *Qh,
+ IN CHAR8 *Msg,
+ IN BOOLEAN DumpBuf
);
-
/**
Dump the buffer in the form of hex.
@@ -50,9 +47,8 @@ EhcDumpQh ( **/
VOID
EhcDumpBuf (
- IN UINT8 *Buf,
- IN UINTN Len
+ IN UINT8 *Buf,
+ IN UINTN Len
);
-
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c index 7bd01c1aee..912048eee9 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c @@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#include "Ehci.h"
-
/**
Read EHCI capability register.
@@ -23,18 +21,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
UINT32
EhcReadCapRegister (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
Status = Ehc->PciIo->Mem.Read (
Ehc->PciIo,
EfiPciIoWidthUint32,
EHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -59,12 +57,12 @@ EhcReadCapRegister ( **/
UINT32
EhcReadDbgRegister (
- IN CONST USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN CONST USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
Status = Ehc->PciIo->Mem.Read (
Ehc->PciIo,
@@ -83,7 +81,6 @@ EhcReadDbgRegister ( return Data;
}
-
/**
Check whether the host controller has an in-use debug port.
@@ -105,11 +102,11 @@ EhcReadDbgRegister ( **/
BOOLEAN
EhcIsDebugPortInUse (
- IN CONST USB2_HC_DEV *Ehc,
- IN CONST UINT8 *PortNumber OPTIONAL
+ IN CONST USB2_HC_DEV *Ehc,
+ IN CONST UINT8 *PortNumber OPTIONAL
)
{
- UINT32 State;
+ UINT32 State;
if (Ehc->DebugPortNum == 0) {
//
@@ -121,7 +118,7 @@ EhcIsDebugPortInUse ( //
// The Debug Port Number field in HCSPARAMS is one-based.
//
- if (PortNumber != NULL && *PortNumber != Ehc->DebugPortNum - 1) {
+ if ((PortNumber != NULL) && (*PortNumber != Ehc->DebugPortNum - 1)) {
//
// The caller specified a port, but it's not the debug port of the host
// controller.
@@ -132,11 +129,10 @@ EhcIsDebugPortInUse ( //
// Deduce usage from the Control Register.
//
- State = EhcReadDbgRegister(Ehc, 0);
+ State = EhcReadDbgRegister (Ehc, 0);
return (State & USB_DEBUG_PORT_IN_USE_MASK) == USB_DEBUG_PORT_IN_USE_MASK;
}
-
/**
Read EHCI Operation register.
@@ -149,12 +145,12 @@ EhcIsDebugPortInUse ( **/
UINT32
EhcReadOpReg (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Ehc->CapLen != 0);
@@ -175,7 +171,6 @@ EhcReadOpReg ( return Data;
}
-
/**
Write the data to the EHCI operation register.
@@ -186,12 +181,12 @@ EhcReadOpReg ( **/
VOID
EhcWriteOpReg (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Ehc->CapLen != 0);
@@ -209,7 +204,6 @@ EhcWriteOpReg ( }
}
-
/**
Set one bit of the operational register while keeping other bits.
@@ -220,19 +214,18 @@ EhcWriteOpReg ( **/
VOID
EhcSetOpRegBit (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data |= Bit;
EhcWriteOpReg (Ehc, Offset, Data);
}
-
/**
Clear one bit of the operational register while keeping other bits.
@@ -243,19 +236,18 @@ EhcSetOpRegBit ( **/
VOID
EhcClearOpRegBit (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data &= ~Bit;
EhcWriteOpReg (Ehc, Offset, Data);
}
-
/**
Wait the operation register's bit as specified by Bit
to become set (or clear).
@@ -272,14 +264,14 @@ EhcClearOpRegBit ( **/
EFI_STATUS
EhcWaitOpRegBit (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- UINT32 Index;
+ UINT32 Index;
for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {
if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {
@@ -292,7 +284,6 @@ EhcWaitOpRegBit ( return EFI_TIMEOUT;
}
-
/**
Add support for UEFI Over Legacy (UoL) feature, stop
the legacy USB SMI support.
@@ -302,13 +293,13 @@ EhcWaitOpRegBit ( **/
VOID
EhcClearLegacySupport (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
- UINT32 ExtendCap;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT32 Value;
- UINT32 TimeOut;
+ UINT32 ExtendCap;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 Value;
+ UINT32 TimeOut;
DEBUG ((DEBUG_INFO, "EhcClearLegacySupport: called to clear legacy support\n"));
@@ -337,8 +328,6 @@ EhcClearLegacySupport ( PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value);
}
-
-
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@@ -352,12 +341,12 @@ EhcClearLegacySupport ( **/
EFI_STATUS
EhcSetAndWaitDoorBell (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_STATUS Status;
+ UINT32 Data;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);
@@ -376,7 +365,6 @@ EhcSetAndWaitDoorBell ( return Status;
}
-
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@@ -386,13 +374,12 @@ EhcSetAndWaitDoorBell ( **/
VOID
EhcAckAllInterrupt (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
}
-
/**
Enable the periodic schedule then wait EHC to
actually enable it.
@@ -406,11 +393,11 @@ EhcAckAllInterrupt ( **/
EFI_STATUS
EhcEnablePeriodSchd (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
@@ -418,11 +405,6 @@ EhcEnablePeriodSchd ( return Status;
}
-
-
-
-
-
/**
Enable asynchrounous schedule.
@@ -435,11 +417,11 @@ EhcEnablePeriodSchd ( **/
EFI_STATUS
EhcEnableAsyncSchd (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
@@ -447,12 +429,6 @@ EhcEnableAsyncSchd ( return Status;
}
-
-
-
-
-
-
/**
Whether Ehc is halted.
@@ -464,13 +440,12 @@ EhcEnableAsyncSchd ( **/
BOOLEAN
EhcIsHalt (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);
}
-
/**
Whether system error occurred.
@@ -482,13 +457,12 @@ EhcIsHalt ( **/
BOOLEAN
EhcIsSysError (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);
}
-
/**
Reset the host controller.
@@ -501,11 +475,11 @@ EhcIsSysError ( **/
EFI_STATUS
EhcResetHC (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Host can only be reset when it is halt. If not so, halt it
@@ -523,7 +497,6 @@ EhcResetHC ( return Status;
}
-
/**
Halt the host controller.
@@ -536,18 +509,17 @@ EhcResetHC ( **/
EFI_STATUS
EhcHaltHC (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);
return Status;
}
-
/**
Set the EHCI to run.
@@ -560,18 +532,17 @@ EhcHaltHC ( **/
EFI_STATUS
EhcRunHC (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);
return Status;
}
-
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware:
@@ -589,12 +560,12 @@ EhcRunHC ( **/
EFI_STATUS
EhcInitHC (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
- EFI_STATUS Status;
- UINT32 Index;
- UINT32 RegVal;
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINT32 RegVal;
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix
@@ -629,15 +600,15 @@ EhcInitHC ( // 3. Power up all ports if EHCI has Port Power Control (PPC) support
//
if (Ehc->HcStructParams & HCSP_PPC) {
- for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {
+ for (Index = 0; Index < (UINT8)(Ehc->HcStructParams & HCSP_NPORTS); Index++) {
//
// Do not clear port status bits on initialization. Otherwise devices will
// not enumerate properly at startup.
//
- RegVal = EhcReadOpReg(Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));
+ RegVal = EhcReadOpReg (Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));
RegVal &= ~PORTSC_CHANGE_MASK;
RegVal |= PORTSC_POWER;
- EhcWriteOpReg (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);
+ EhcWriteOpReg (Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);
}
}
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h index 911cd2135f..064de362cb 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h @@ -14,20 +14,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // EHCI register offset
//
-
//
// Capability register offset
//
-#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
-#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
-#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
-#define HCSP_NPORTS 0x0F // Number of root hub port
-#define HCSP_PPC 0x10 // Port Power Control
-#define HCCP_64BIT 0x01 // 64-bit addressing capability
+#define HCSP_NPORTS 0x0F // Number of root hub port
+#define HCSP_PPC 0x10 // Port Power Control
+#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -42,66 +41,66 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
-#define EHC_FRAME_LEN 1024
+#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
-#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
-
-#define USBCMD_RUN 0x01 // Run/stop
-#define USBCMD_RESET 0x02 // Start the host controller reset
-#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
-#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
-#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
-
-#define USBSTS_IAA 0x20 // Interrupt on async advance
-#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
-#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
-#define USBSTS_HALT 0x1000 // Host controller halted
-#define USBSTS_SYS_ERROR 0x10 // Host system error
-#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
+
+#define USBCMD_RUN 0x01 // Run/stop
+#define USBCMD_RESET 0x02 // Start the host controller reset
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
+
+#define USBSTS_IAA 0x20 // Interrupt on async advance
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
+#define USBSTS_HALT 0x1000 // Host controller halted
+#define USBSTS_SYS_ERROR 0x10 // Host system error
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
-#define PORTSC_CONN 0x01 // Current Connect Status
-#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
-#define PORTSC_ENABLED 0x04 // Port Enable / Disable
-#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
-#define PORTSC_OVERCUR 0x10 // Over current Active
-#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
-#define PORSTSC_RESUME 0x40 // Force Port Resume
-#define PORTSC_SUSPEND 0x80 // Port Suspend State
-#define PORTSC_RESET 0x100 // Port Reset
-#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
-#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
-#define PORTSC_POWER 0x1000 // Port Power
-#define PORTSC_OWNER 0x2000 // Port Owner
-#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
+#define PORTSC_CONN 0x01 // Current Connect Status
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
+#define PORTSC_OVERCUR 0x10 // Over current Active
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
+#define PORSTSC_RESUME 0x40 // Force Port Resume
+#define PORTSC_SUSPEND 0x80 // Port Suspend State
+#define PORTSC_RESET 0x100 // Port Reset
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
+#define PORTSC_POWER 0x1000 // Port Power
+#define PORTSC_OWNER 0x2000 // Port Owner
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
-#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
//
// Debug port capability id
//
-#define EHC_DEBUG_PORT_CAP_ID 0x0A
+#define EHC_DEBUG_PORT_CAP_ID 0x0A
-#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
+#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
-#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
+#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
- UINT16 HwState;
- UINT16 UefiState;
+ UINT16 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -109,9 +108,9 @@ typedef struct { //
#pragma pack(1)
typedef struct {
- UINT8 ProgInterface;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 ProgInterface;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
@@ -126,8 +125,8 @@ typedef struct { **/
UINT32
EhcReadCapRegister (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
);
/**
@@ -151,8 +150,8 @@ EhcReadCapRegister ( **/
BOOLEAN
EhcIsDebugPortInUse (
- IN CONST USB2_HC_DEV *Ehc,
- IN CONST UINT8 *PortNumber OPTIONAL
+ IN CONST USB2_HC_DEV *Ehc,
+ IN CONST UINT8 *PortNumber OPTIONAL
);
/**
@@ -166,11 +165,10 @@ EhcIsDebugPortInUse ( **/
UINT32
EhcReadOpReg (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
);
-
/**
Write the data to the EHCI operation register.
@@ -181,9 +179,9 @@ EhcReadOpReg ( **/
VOID
EhcWriteOpReg (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -196,9 +194,9 @@ EhcWriteOpReg ( **/
VOID
EhcSetOpRegBit (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -211,9 +209,9 @@ EhcSetOpRegBit ( **/
VOID
EhcClearOpRegBit (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -225,11 +223,9 @@ EhcClearOpRegBit ( **/
VOID
EhcClearLegacySupport (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
-
-
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@@ -243,11 +239,10 @@ EhcClearLegacySupport ( **/
EFI_STATUS
EhcSetAndWaitDoorBell (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
);
-
/**
Clear all the interrutp status bits, these bits are Write-Clean.
@@ -256,11 +251,9 @@ EhcSetAndWaitDoorBell ( **/
VOID
EhcAckAllInterrupt (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
-
-
/**
Whether Ehc is halted.
@@ -272,10 +265,9 @@ EhcAckAllInterrupt ( **/
BOOLEAN
EhcIsHalt (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
-
/**
Whether system error occurred.
@@ -287,10 +279,9 @@ EhcIsHalt ( **/
BOOLEAN
EhcIsSysError (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
-
/**
Reset the host controller.
@@ -303,11 +294,10 @@ EhcIsSysError ( **/
EFI_STATUS
EhcResetHC (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
);
-
/**
Halt the host controller.
@@ -320,11 +310,10 @@ EhcResetHC ( **/
EFI_STATUS
EhcHaltHC (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
);
-
/**
Set the EHCI to run.
@@ -337,12 +326,10 @@ EhcHaltHC ( **/
EFI_STATUS
EhcRunHC (
- IN USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
);
-
-
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware:
@@ -360,7 +347,7 @@ EhcRunHC ( **/
EFI_STATUS
EhcInitHC (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c index 34ee40c4bb..5da26afbe1 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Ehci.h"
-
/**
Create helper QTD/QH for the EHCI device.
@@ -22,14 +21,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
EhcCreateHelpQ (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
- USB_ENDPOINT Ep;
- EHC_QH *Qh;
- QH_HW *QhHw;
- EHC_QTD *Qtd;
- EFI_PHYSICAL_ADDRESS PciAddr;
+ USB_ENDPOINT Ep;
+ EHC_QH *Qh;
+ QH_HW *QhHw;
+ EHC_QTD *Qtd;
+ EFI_PHYSICAL_ADDRESS PciAddr;
//
// Create an inactive Qtd to terminate the short packet read.
@@ -40,25 +39,25 @@ EhcCreateHelpQ ( return EFI_OUT_OF_RESOURCES;
}
- Qtd->QtdHw.Status = QTD_STAT_HALTED;
- Ehc->ShortReadStop = Qtd;
+ Qtd->QtdHw.Status = QTD_STAT_HALTED;
+ Ehc->ShortReadStop = Qtd;
//
// Create a QH to act as the EHC reclamation header.
// Set the header to loopback to itself.
//
- Ep.DevAddr = 0;
- Ep.EpAddr = 1;
- Ep.Direction = EfiUsbDataIn;
- Ep.DevSpeed = EFI_USB_SPEED_HIGH;
- Ep.MaxPacket = 64;
- Ep.HubAddr = 0;
- Ep.HubPort = 0;
- Ep.Toggle = 0;
- Ep.Type = EHC_BULK_TRANSFER;
- Ep.PollRate = 1;
-
- Qh = EhcCreateQh (Ehc, &Ep);
+ Ep.DevAddr = 0;
+ Ep.EpAddr = 1;
+ Ep.Direction = EfiUsbDataIn;
+ Ep.DevSpeed = EFI_USB_SPEED_HIGH;
+ Ep.MaxPacket = 64;
+ Ep.HubAddr = 0;
+ Ep.HubPort = 0;
+ Ep.Toggle = 0;
+ Ep.Type = EHC_BULK_TRANSFER;
+ Ep.PollRate = 1;
+
+ Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -66,7 +65,7 @@ EhcCreateHelpQ ( PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
QhHw = &Qh->QhHw;
- QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF(EHC_QH, QhHw), EHC_TYPE_QH, FALSE);
+ QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF (EHC_QH, QhHw), EHC_TYPE_QH, FALSE);
QhHw->Status = QTD_STAT_HALTED;
QhHw->ReclaimHead = 1;
Qh->NextQh = Qh;
@@ -75,10 +74,10 @@ EhcCreateHelpQ ( //
// Create a dummy QH to act as the terminator for periodical schedule
//
- Ep.EpAddr = 2;
- Ep.Type = EHC_INT_TRANSFER_SYNC;
+ Ep.EpAddr = 2;
+ Ep.Type = EHC_INT_TRANSFER_SYNC;
- Qh = EhcCreateQh (Ehc, &Ep);
+ Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -90,7 +89,6 @@ EhcCreateHelpQ ( return EFI_SUCCESS;
}
-
/**
Initialize the schedule data structure such as frame list.
@@ -102,7 +100,7 @@ EhcCreateHelpQ ( **/
EFI_STATUS
EhcInitSched (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
EFI_PCI_IO_PROTOCOL *PciIo;
@@ -154,8 +152,8 @@ EhcInitSched ( return EFI_OUT_OF_RESOURCES;
}
- Ehc->PeriodFrame = Buf;
- Ehc->PeriodFrameMap = Map;
+ Ehc->PeriodFrame = Buf;
+ Ehc->PeriodFrameMap = Map;
//
// Program the FRAMELISTBASE register with the low 32 bit addr
@@ -191,13 +189,13 @@ EhcInitSched ( //
// Initialize the frame list entries then set the registers
//
- Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));
+ Ehc->PeriodFrameHost = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));
if (Ehc->PeriodFrameHost == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto ErrorExit;
}
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));
for (Index = 0; Index < EHC_FRAME_LEN; Index++) {
//
@@ -242,7 +240,6 @@ ErrorExit1: return Status;
}
-
/**
Free the schedule data. It may be partially initialized.
@@ -251,10 +248,10 @@ ErrorExit1: **/
VOID
EhcFreeSched (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);
@@ -300,7 +297,6 @@ EhcFreeSched ( }
}
-
/**
Link the queue head to the asynchronous schedule list.
UEFI only supports one CTRL/BULK transfer at a time
@@ -314,30 +310,29 @@ EhcFreeSched ( **/
VOID
EhcLinkQhToAsync (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
)
{
- EHC_QH *Head;
- EFI_PHYSICAL_ADDRESS PciAddr;
+ EHC_QH *Head;
+ EFI_PHYSICAL_ADDRESS PciAddr;
//
// Append the queue head after the reclaim header, then
// fix the hardware visiable parts (EHCI R1.0 page 72).
// ReclaimHead is always linked to the EHCI's AsynListAddr.
//
- Head = Ehc->ReclaimHead;
+ Head = Ehc->ReclaimHead;
- Qh->NextQh = Head->NextQh;
- Head->NextQh = Qh;
+ Qh->NextQh = Head->NextQh;
+ Head->NextQh = Qh;
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));
- Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
- Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh->NextQh, sizeof (EHC_QH));
+ Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
+ Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
-
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@@ -348,13 +343,13 @@ EhcLinkQhToAsync ( **/
VOID
EhcUnlinkQhFromAsync (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
)
{
- EHC_QH *Head;
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PciAddr;
+ EHC_QH *Head;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PciAddr;
ASSERT (Ehc->ReclaimHead->NextQh == Qh);
@@ -363,13 +358,13 @@ EhcUnlinkQhFromAsync ( // visiable part: Only need to loopback the ReclaimHead. The Qh
// is pointing to ReclaimHead (which is staill in the list).
//
- Head = Ehc->ReclaimHead;
+ Head = Ehc->ReclaimHead;
- Head->NextQh = Qh->NextQh;
- Qh->NextQh = NULL;
+ Head->NextQh = Qh->NextQh;
+ Qh->NextQh = NULL;
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
- Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head->NextQh, sizeof (EHC_QH));
+ Head->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
//
// Set and wait the door bell to synchronize with the hardware
@@ -381,7 +376,6 @@ EhcUnlinkQhFromAsync ( }
}
-
/**
Link a queue head for interrupt transfer to the periodic
schedule frame list. This code is very much the same as
@@ -393,23 +387,23 @@ EhcUnlinkQhFromAsync ( **/
VOID
EhcLinkQhToPeriod (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
)
{
- UINTN Index;
- EHC_QH *Prev;
- EHC_QH *Next;
- EFI_PHYSICAL_ADDRESS PciAddr;
+ UINTN Index;
+ EHC_QH *Prev;
+ EHC_QH *Next;
+ EFI_PHYSICAL_ADDRESS PciAddr;
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {
//
// First QH can't be NULL because we always keep PeriodOne
// heads on the frame list
//
- ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));
- Next = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];
- Prev = NULL;
+ ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));
+ Next = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];
+ Prev = NULL;
//
// Now, insert the queue head (Qh) into this frame:
@@ -422,8 +416,8 @@ EhcLinkQhToPeriod ( // Then, insert the Qh between then
//
while (Next->Interval > Qh->Interval) {
- Prev = Next;
- Next = Next->NextQh;
+ Prev = Next;
+ Next = Next->NextQh;
}
ASSERT (Next != NULL);
@@ -449,15 +443,15 @@ EhcLinkQhToPeriod ( //
ASSERT ((Index == 0) && (Qh->NextQh == NULL));
- Prev = Next;
- Next = Next->NextQh;
+ Prev = Next;
+ Next = Next->NextQh;
- Qh->NextQh = Next;
- Prev->NextQh = Qh;
+ Qh->NextQh = Next;
+ Prev->NextQh = Qh;
- Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
- Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
+ Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
+ Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
break;
}
@@ -467,24 +461,23 @@ EhcLinkQhToPeriod ( // guarranted by 2^n polling interval.
//
if (Qh->NextQh == NULL) {
- Qh->NextQh = Next;
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));
- Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
+ Qh->NextQh = Next;
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));
+ Qh->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));
if (Prev == NULL) {
- ((UINT32*)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
- ((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;
+ ((UINT32 *)Ehc->PeriodFrame)[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
+ ((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh;
} else {
- Prev->NextQh = Qh;
- Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
+ Prev->NextQh = Qh;
+ Prev->QhHw.HorizonLink = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
}
}
-
/**
Unlink an interrupt queue head from the periodic
schedule frame list.
@@ -495,30 +488,30 @@ EhcLinkQhToPeriod ( **/
VOID
EhcUnlinkQhFromPeriod (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
)
{
- UINTN Index;
- EHC_QH *Prev;
- EHC_QH *This;
+ UINTN Index;
+ EHC_QH *Prev;
+ EHC_QH *This;
for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {
//
// Frame link can't be NULL because we always keep PeroidOne
// on the frame list
//
- ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));
- This = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];
- Prev = NULL;
+ ASSERT (!EHC_LINK_TERMINATED (((UINT32 *)Ehc->PeriodFrame)[Index]));
+ This = (EHC_QH *)((UINTN *)Ehc->PeriodFrameHost)[Index];
+ Prev = NULL;
//
// Walk through the frame's QH list to find the
// queue head to remove
//
while ((This != NULL) && (This != Qh)) {
- Prev = This;
- This = This->NextQh;
+ Prev = This;
+ This = This->NextQh;
}
//
@@ -533,16 +526,15 @@ EhcUnlinkQhFromPeriod ( //
// Qh is the first entry in the frame
//
- ((UINT32*)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;
- ((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;
+ ((UINT32 *)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;
+ ((UINTN *)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;
} else {
- Prev->NextQh = Qh->NextQh;
- Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
+ Prev->NextQh = Qh->NextQh;
+ Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
}
}
}
-
/**
Check the URB's execution result and update the URB's
result accordingly.
@@ -555,23 +547,23 @@ EhcUnlinkQhFromPeriod ( **/
BOOLEAN
EhcCheckUrbResult (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb
)
{
- LIST_ENTRY *Entry;
- EHC_QTD *Qtd;
- QTD_HW *QtdHw;
- UINT8 State;
- BOOLEAN Finished;
- EFI_PHYSICAL_ADDRESS PciAddr;
+ LIST_ENTRY *Entry;
+ EHC_QTD *Qtd;
+ QTD_HW *QtdHw;
+ UINT8 State;
+ BOOLEAN Finished;
+ EFI_PHYSICAL_ADDRESS PciAddr;
ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));
- Finished = TRUE;
- Urb->Completed = 0;
+ Finished = TRUE;
+ Urb->Completed = 0;
- Urb->Result = EFI_USB_NOERROR;
+ Urb->Result = EFI_USB_NOERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
Urb->Result |= EFI_USB_ERR_SYSTEM;
@@ -581,7 +573,7 @@ EhcCheckUrbResult ( BASE_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);
QtdHw = &Qtd->QtdHw;
- State = (UINT8) QtdHw->Status;
+ State = (UINT8)QtdHw->Status;
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
//
@@ -606,7 +598,6 @@ EhcCheckUrbResult ( Finished = TRUE;
goto ON_EXIT;
-
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
//
// The QTD is still active, no need to check furthur.
@@ -615,7 +606,6 @@ EhcCheckUrbResult ( Finished = FALSE;
goto ON_EXIT;
-
} else {
//
// This QTD is finished OK or met short packet read. Update the
@@ -657,12 +647,11 @@ ON_EXIT: // NOTICE: don't move DT update before the loop, otherwise there is
// a race condition that DT is wrong.
//
- Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;
+ Urb->DataToggle = (UINT8)Urb->Qh->QhHw.DataToggle;
return Finished;
}
-
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -677,16 +666,16 @@ ON_EXIT: **/
EFI_STATUS
EhcExecTransfer (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb,
- IN UINTN TimeOut
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb,
+ IN UINTN TimeOut
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINTN Loop;
- BOOLEAN Finished;
- BOOLEAN InfiniteLoop;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN Loop;
+ BOOLEAN Finished;
+ BOOLEAN InfiniteLoop;
Status = EFI_SUCCESS;
Loop = TimeOut * EHC_1_MILLISECOND;
@@ -717,7 +706,6 @@ EhcExecTransfer ( EhcDumpQh (Urb->Qh, NULL, FALSE);
Status = EFI_TIMEOUT;
-
} else if (Urb->Result != EFI_USB_NOERROR) {
DEBUG ((DEBUG_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));
EhcDumpQh (Urb->Qh, NULL, FALSE);
@@ -728,7 +716,6 @@ EhcExecTransfer ( return Status;
}
-
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@@ -744,10 +731,10 @@ EhcExecTransfer ( **/
EFI_STATUS
EhciDelAsyncIntTransfer (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpNum,
- OUT UINT8 *DataToggle
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpNum,
+ OUT UINT8 *DataToggle
)
{
LIST_ENTRY *Entry;
@@ -762,7 +749,8 @@ EhciDelAsyncIntTransfer ( Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if ((Urb->Ep.DevAddr == DevAddr) && (Urb->Ep.EpAddr == EpNum) &&
- (Urb->Ep.Direction == Direction)) {
+ (Urb->Ep.Direction == Direction))
+ {
//
// Check the URB status to retrieve the next data toggle
// from the associated queue head.
@@ -782,7 +770,6 @@ EhciDelAsyncIntTransfer ( return EFI_NOT_FOUND;
}
-
/**
Remove all the asynchronous interrutp transfers.
@@ -791,12 +778,12 @@ EhciDelAsyncIntTransfer ( **/
VOID
EhciDelAllAsyncIntTransfers (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- URB *Urb;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *Urb;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -830,21 +817,21 @@ EhciDelAllAsyncIntTransfers ( **/
URB *
EhciInsertAsyncIntTransfer (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
)
{
- VOID *Data;
- URB *Urb;
+ VOID *Data;
+ URB *Urb;
Data = AllocatePool (DataLen);
@@ -899,16 +886,16 @@ EhciInsertAsyncIntTransfer ( **/
EFI_STATUS
EhcFlushAsyncIntMap (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINTN Len;
- VOID *Map;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN Len;
+ VOID *Map;
PciIo = Ehc->PciIo;
Len = Urb->DataLen;
@@ -931,15 +918,14 @@ EhcFlushAsyncIntMap ( goto ON_ERROR;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
return EFI_SUCCESS;
ON_ERROR:
return EFI_DEVICE_ERROR;
}
-
/**
Update the queue head for next round of asynchronous transfer.
@@ -949,17 +935,17 @@ ON_ERROR: **/
VOID
EhcUpdateAsyncRequest (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb
)
{
- LIST_ENTRY *Entry;
- EHC_QTD *FirstQtd;
- QH_HW *QhHw;
- EHC_QTD *Qtd;
- QTD_HW *QtdHw;
- UINTN Index;
- EFI_PHYSICAL_ADDRESS PciAddr;
+ LIST_ENTRY *Entry;
+ EHC_QTD *FirstQtd;
+ QH_HW *QhHw;
+ EHC_QTD *Qtd;
+ QTD_HW *QtdHw;
+ UINTN Index;
+ EFI_PHYSICAL_ADDRESS PciAddr;
Qtd = NULL;
@@ -985,13 +971,13 @@ EhcUpdateAsyncRequest ( QtdHw->Status = QTD_STAT_ACTIVE;
QtdHw->ErrCnt = QTD_MAX_ERR;
QtdHw->CurPage = 0;
- QtdHw->TotalBytes = (UINT32) Qtd->DataLen;
+ QtdHw->TotalBytes = (UINT32)Qtd->DataLen;
//
// calculate physical address by offset.
//
- PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);
- QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);
- QtdHw->PageHigh[0]= EHC_HIGH_32BIT (PciAddr);
+ PciAddr = (UINTN)Urb->DataPhy + ((UINTN)Qtd->Data - (UINTN)Urb->Data);
+ QtdHw->Page[0] = EHC_LOW_32BIT (PciAddr);
+ QtdHw->PageHigh[0] = EHC_HIGH_32BIT (PciAddr);
}
//
@@ -1000,30 +986,29 @@ EhcUpdateAsyncRequest ( // zero out the overlay area and set NextQtd to the first
// QTD. DateToggle bit is left untouched.
//
- QhHw = &Urb->Qh->QhHw;
- QhHw->CurQtd = QTD_LINK (0, TRUE);
- QhHw->AltQtd = 0;
+ QhHw = &Urb->Qh->QhHw;
+ QhHw->CurQtd = QTD_LINK (0, TRUE);
+ QhHw->AltQtd = 0;
- QhHw->Status = 0;
- QhHw->Pid = 0;
- QhHw->ErrCnt = 0;
- QhHw->CurPage = 0;
- QhHw->Ioc = 0;
- QhHw->TotalBytes = 0;
+ QhHw->Status = 0;
+ QhHw->Pid = 0;
+ QhHw->ErrCnt = 0;
+ QhHw->CurPage = 0;
+ QhHw->Ioc = 0;
+ QhHw->TotalBytes = 0;
for (Index = 0; Index < 5; Index++) {
QhHw->Page[Index] = 0;
QhHw->PageHigh[Index] = 0;
}
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));
QhHw->NextQtd = QTD_LINK (PciAddr, FALSE);
}
- return ;
+ return;
}
-
/**
Interrupt transfer periodic check handler.
@@ -1034,21 +1019,21 @@ EhcUpdateAsyncRequest ( VOID
EFIAPI
EhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- USB2_HC_DEV *Ehc;
- EFI_TPL OldTpl;
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- BOOLEAN Finished;
- UINT8 *ProcBuf;
- URB *Urb;
- EFI_STATUS Status;
-
- OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = (USB2_HC_DEV *) Context;
+ USB2_HC_DEV *Ehc;
+ EFI_TPL OldTpl;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ BOOLEAN Finished;
+ UINT8 *ProcBuf;
+ URB *Urb;
+ EFI_STATUS Status;
+
+ OldTpl = gBS->RaiseTPL (EHC_TPL);
+ Ehc = (USB2_HC_DEV *)Context;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1113,7 +1098,7 @@ EhcMonitorAsyncRequests ( // his callback. Some drivers may has a lower TPL restriction.
//
gBS->RestoreTPL (OldTpl);
- (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
+ (Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
OldTpl = gBS->RaiseTPL (EHC_TPL);
}
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.h index 34fb9a3be2..b5fc616952 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_SCHED_H_
#define _EFI_EHCI_SCHED_H_
-
/**
Initialize the schedule data structure such as frame list.
@@ -22,10 +21,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
EhcInitSched (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
-
/**
Free the schedule data. It may be partially initialized.
@@ -34,10 +32,9 @@ EhcInitSched ( **/
VOID
EhcFreeSched (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
-
/**
Link the queue head to the asynchronous schedule list.
UEFI only supports one CTRL/BULK transfer at a time
@@ -51,11 +48,10 @@ EhcFreeSched ( **/
VOID
EhcLinkQhToAsync (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
);
-
/**
Unlink a queue head from the asynchronous schedule list.
Need to synchronize with hardware.
@@ -66,11 +62,10 @@ EhcLinkQhToAsync ( **/
VOID
EhcUnlinkQhFromAsync (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
);
-
/**
Link a queue head for interrupt transfer to the periodic
schedule frame list. This code is very much the same as
@@ -82,11 +77,10 @@ EhcUnlinkQhFromAsync ( **/
VOID
EhcLinkQhToPeriod (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
);
-
/**
Unlink an interrupt queue head from the periodic
schedule frame list.
@@ -97,12 +91,10 @@ EhcLinkQhToPeriod ( **/
VOID
EhcUnlinkQhFromPeriod (
- IN USB2_HC_DEV *Ehc,
- IN EHC_QH *Qh
+ IN USB2_HC_DEV *Ehc,
+ IN EHC_QH *Qh
);
-
-
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -117,12 +109,11 @@ EhcUnlinkQhFromPeriod ( **/
EFI_STATUS
EhcExecTransfer (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb,
- IN UINTN TimeOut
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb,
+ IN UINTN TimeOut
);
-
/**
Delete a single asynchronous interrupt transfer for
the device and endpoint.
@@ -138,13 +129,12 @@ EhcExecTransfer ( **/
EFI_STATUS
EhciDelAsyncIntTransfer (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpNum,
- OUT UINT8 *DataToggle
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpNum,
+ OUT UINT8 *DataToggle
);
-
/**
Remove all the asynchronous interrutp transfers.
@@ -153,7 +143,7 @@ EhciDelAsyncIntTransfer ( **/
VOID
EhciDelAllAsyncIntTransfers (
- IN USB2_HC_DEV *Ehc
+ IN USB2_HC_DEV *Ehc
);
/**
@@ -177,17 +167,17 @@ EhciDelAllAsyncIntTransfers ( **/
URB *
EhciInsertAsyncIntTransfer (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
);
/**
@@ -200,8 +190,8 @@ EhciInsertAsyncIntTransfer ( VOID
EFIAPI
EhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c index 37cef6d130..a2b0b99d33 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c @@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Ehci.h"
-
/**
Create a single QTD to hold the data.
@@ -28,20 +27,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EHC_QTD *
EhcCreateQtd (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 *Data,
- IN UINT8 *DataPhy,
- IN UINTN DataLen,
- IN UINT8 PktId,
- IN UINT8 Toggle,
- IN UINTN MaxPacket
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 *Data,
+ IN UINT8 *DataPhy,
+ IN UINTN DataLen,
+ IN UINT8 PktId,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket
)
{
- EHC_QTD *Qtd;
- QTD_HW *QtdHw;
- UINTN Index;
- UINTN Len;
- UINTN ThisBufLen;
+ EHC_QTD *Qtd;
+ QTD_HW *QtdHw;
+ UINTN Index;
+ UINTN Len;
+ UINTN ThisBufLen;
ASSERT (Ehc != NULL);
@@ -51,9 +50,9 @@ EhcCreateQtd ( return NULL;
}
- Qtd->Signature = EHC_QTD_SIG;
- Qtd->Data = Data;
- Qtd->DataLen = 0;
+ Qtd->Signature = EHC_QTD_SIG;
+ Qtd->Data = Data;
+ Qtd->DataLen = 0;
InitializeListHead (&Qtd->QtdList);
@@ -79,18 +78,18 @@ EhcCreateQtd ( // compute the offset and clear Reserved fields. This is already
// done in the data point.
//
- QtdHw->Page[Index] = EHC_LOW_32BIT (DataPhy);
- QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (DataPhy);
+ QtdHw->Page[Index] = EHC_LOW_32BIT (DataPhy);
+ QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (DataPhy);
- ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (DataPhy) & QTD_BUF_MASK);
+ ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (DataPhy) & QTD_BUF_MASK);
if (Len + ThisBufLen >= DataLen) {
Len = DataLen;
break;
}
- Len += ThisBufLen;
- Data += ThisBufLen;
+ Len += ThisBufLen;
+ Data += ThisBufLen;
DataPhy += ThisBufLen;
}
@@ -104,15 +103,13 @@ EhcCreateQtd ( Len = Len - Len % MaxPacket;
}
- QtdHw->TotalBytes = (UINT32) Len;
+ QtdHw->TotalBytes = (UINT32)Len;
Qtd->DataLen = Len;
}
return Qtd;
}
-
-
/**
Initialize the queue head for interrupt transfer,
that is, initialize the following three fields:
@@ -126,8 +123,8 @@ EhcCreateQtd ( **/
VOID
EhcInitIntQh (
- IN USB_ENDPOINT *Ep,
- IN QH_HW *QhHw
+ IN USB_ENDPOINT *Ep,
+ IN QH_HW *QhHw
)
{
//
@@ -139,7 +136,7 @@ EhcInitIntQh ( //
if (Ep->DevSpeed == EFI_USB_SPEED_HIGH) {
QhHw->SMask = QH_MICROFRAME_0;
- return ;
+ return;
}
//
@@ -157,8 +154,6 @@ EhcInitIntQh ( QhHw->CMask = QH_MICROFRAME_3 | QH_MICROFRAME_4 | QH_MICROFRAME_5;
}
-
-
/**
Allocate and initialize a EHCI queue head.
@@ -170,12 +165,12 @@ EhcInitIntQh ( **/
EHC_QH *
EhcCreateQh (
- IN USB2_HC_DEV *Ehci,
- IN USB_ENDPOINT *Ep
+ IN USB2_HC_DEV *Ehci,
+ IN USB_ENDPOINT *Ep
)
{
- EHC_QH *Qh;
- QH_HW *QhHw;
+ EHC_QH *Qh;
+ QH_HW *QhHw;
Qh = UsbHcAllocateMem (Ehci->MemPool, sizeof (EHC_QH));
@@ -183,68 +178,68 @@ EhcCreateQh ( return NULL;
}
- Qh->Signature = EHC_QH_SIG;
- Qh->NextQh = NULL;
- Qh->Interval = Ep->PollRate;
+ Qh->Signature = EHC_QH_SIG;
+ Qh->NextQh = NULL;
+ Qh->Interval = Ep->PollRate;
InitializeListHead (&Qh->Qtds);
- QhHw = &Qh->QhHw;
- QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
- QhHw->DeviceAddr = Ep->DevAddr;
- QhHw->Inactive = 0;
- QhHw->EpNum = Ep->EpAddr;
- QhHw->EpSpeed = Ep->DevSpeed;
- QhHw->DtCtrl = 0;
- QhHw->ReclaimHead = 0;
- QhHw->MaxPacketLen = (UINT32) Ep->MaxPacket;
- QhHw->CtrlEp = 0;
- QhHw->NakReload = QH_NAK_RELOAD;
- QhHw->HubAddr = Ep->HubAddr;
- QhHw->PortNum = Ep->HubPort;
- QhHw->Multiplier = 1;
- QhHw->DataToggle = Ep->Toggle;
+ QhHw = &Qh->QhHw;
+ QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
+ QhHw->DeviceAddr = Ep->DevAddr;
+ QhHw->Inactive = 0;
+ QhHw->EpNum = Ep->EpAddr;
+ QhHw->EpSpeed = Ep->DevSpeed;
+ QhHw->DtCtrl = 0;
+ QhHw->ReclaimHead = 0;
+ QhHw->MaxPacketLen = (UINT32)Ep->MaxPacket;
+ QhHw->CtrlEp = 0;
+ QhHw->NakReload = QH_NAK_RELOAD;
+ QhHw->HubAddr = Ep->HubAddr;
+ QhHw->PortNum = Ep->HubPort;
+ QhHw->Multiplier = 1;
+ QhHw->DataToggle = Ep->Toggle;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->Status |= QTD_STAT_DO_SS;
}
switch (Ep->Type) {
- case EHC_CTRL_TRANSFER:
- //
- // Special initialization for the control transfer:
- // 1. Control transfer initialize data toggle from each QTD
- // 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
- //
- QhHw->DtCtrl = 1;
+ case EHC_CTRL_TRANSFER:
+ //
+ // Special initialization for the control transfer:
+ // 1. Control transfer initialize data toggle from each QTD
+ // 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
+ //
+ QhHw->DtCtrl = 1;
- if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
- QhHw->CtrlEp = 1;
- }
- break;
+ if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
+ QhHw->CtrlEp = 1;
+ }
- case EHC_INT_TRANSFER_ASYNC:
- case EHC_INT_TRANSFER_SYNC:
- //
- // Special initialization for the interrupt transfer
- // to set the S-Mask and C-Mask
- //
- QhHw->NakReload = 0;
- EhcInitIntQh (Ep, QhHw);
- break;
+ break;
- case EHC_BULK_TRANSFER:
- if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
- QhHw->Status |= QTD_STAT_DO_PING;
- }
+ case EHC_INT_TRANSFER_ASYNC:
+ case EHC_INT_TRANSFER_SYNC:
+ //
+ // Special initialization for the interrupt transfer
+ // to set the S-Mask and C-Mask
+ //
+ QhHw->NakReload = 0;
+ EhcInitIntQh (Ep, QhHw);
+ break;
+
+ case EHC_BULK_TRANSFER:
+ if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
+ QhHw->Status |= QTD_STAT_DO_PING;
+ }
- break;
+ break;
}
return Qh;
}
-
/**
Convert the poll interval from application to that
be used by EHCI interface data structure. Only need
@@ -260,10 +255,10 @@ EhcCreateQh ( **/
UINTN
EhcConvertPollRate (
- IN UINTN Interval
+ IN UINTN Interval
)
{
- UINTN BitCount;
+ UINTN BitCount;
if (Interval == 0) {
return 1;
@@ -282,7 +277,6 @@ EhcConvertPollRate ( return (UINTN)1 << (BitCount - 1);
}
-
/**
Free a list of QTDs.
@@ -292,13 +286,13 @@ EhcConvertPollRate ( **/
VOID
EhcFreeQtds (
- IN USB2_HC_DEV *Ehc,
- IN LIST_ENTRY *Qtds
+ IN USB2_HC_DEV *Ehc,
+ IN LIST_ENTRY *Qtds
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- EHC_QTD *Qtd;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ EHC_QTD *Qtd;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);
@@ -308,7 +302,6 @@ EhcFreeQtds ( }
}
-
/**
Free an allocated URB. It is possible for it to be partially inited.
@@ -318,11 +311,11 @@ EhcFreeQtds ( **/
VOID
EhcFreeUrb (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = Ehc->PciIo;
@@ -346,7 +339,6 @@ EhcFreeUrb ( gBS->FreePool (Urb);
}
-
/**
Create a list of QTDs for the URB.
@@ -359,21 +351,21 @@ EhcFreeUrb ( **/
EFI_STATUS
EhcCreateQtds (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb
)
{
- USB_ENDPOINT *Ep;
- EHC_QH *Qh;
- EHC_QTD *Qtd;
- EHC_QTD *StatusQtd;
- EHC_QTD *NextQtd;
- LIST_ENTRY *Entry;
- UINT32 AlterNext;
- UINT8 Toggle;
- UINTN Len;
- UINT8 Pid;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ USB_ENDPOINT *Ep;
+ EHC_QH *Qh;
+ EHC_QTD *Qtd;
+ EHC_QTD *StatusQtd;
+ EHC_QTD *NextQtd;
+ LIST_ENTRY *Entry;
+ UINT32 AlterNext;
+ UINT8 Toggle;
+ UINTN Len;
+ UINT8 Pid;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Urb != NULL) && (Urb->Qh != NULL));
@@ -389,7 +381,7 @@ EhcCreateQtds ( StatusQtd = NULL;
AlterNext = QTD_LINK (NULL, TRUE);
- PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
+ PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));
if (Ep->Direction == EfiUsbDataIn) {
AlterNext = QTD_LINK (PhyAddr, FALSE);
}
@@ -448,8 +440,8 @@ EhcCreateQtds ( while (Len < Urb->DataLen) {
Qtd = EhcCreateQtd (
Ehc,
- (UINT8 *) Urb->Data + Len,
- (UINT8 *) Urb->DataPhy + Len,
+ (UINT8 *)Urb->Data + Len,
+ (UINT8 *)Urb->DataPhy + Len,
Urb->DataLen - Len,
Pid,
Toggle,
@@ -467,7 +459,7 @@ EhcCreateQtds ( // Switch the Toggle bit if odd number of packets are included in the QTD.
//
if (((Qtd->DataLen + Ep->MaxPacket - 1) / Ep->MaxPacket) % 2) {
- Toggle = (UINT8) (1 - Toggle);
+ Toggle = (UINT8)(1 - Toggle);
}
Len += Qtd->DataLen;
@@ -493,17 +485,17 @@ EhcCreateQtds ( break;
}
- NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, EHC_QTD, QtdList);
- PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
- Qtd->QtdHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
+ NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, EHC_QTD, QtdList);
+ PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
+ Qtd->QtdHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
}
//
// Link the QTDs to the queue head
//
- NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, EHC_QTD, QtdList);
- PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
- Qh->QhHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
+ NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, EHC_QTD, QtdList);
+ PhyAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, NextQtd, sizeof (EHC_QTD));
+ Qh->QhHw.NextQtd = QTD_LINK (PhyAddr, FALSE);
return EFI_SUCCESS;
ON_ERROR:
@@ -511,7 +503,6 @@ ON_ERROR: return EFI_OUT_OF_RESOURCES;
}
-
/**
Create a new URB and its associated QTD.
@@ -535,30 +526,30 @@ ON_ERROR: **/
URB *
EhcCreateUrb (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
)
{
- USB_ENDPOINT *Ep;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINTN Len;
- URB *Urb;
- VOID *Map;
+ USB_ENDPOINT *Ep;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINTN Len;
+ URB *Urb;
+ VOID *Map;
Urb = AllocateZeroPool (sizeof (URB));
@@ -566,38 +557,38 @@ EhcCreateUrb ( return NULL;
}
- Urb->Signature = EHC_URB_SIG;
+ Urb->Signature = EHC_URB_SIG;
InitializeListHead (&Urb->UrbList);
- Ep = &Urb->Ep;
- Ep->DevAddr = DevAddr;
- Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
- Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
- Ep->DevSpeed = DevSpeed;
- Ep->MaxPacket = MaxPacket;
+ Ep = &Urb->Ep;
+ Ep->DevAddr = DevAddr;
+ Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
+ Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
+ Ep->DevSpeed = DevSpeed;
+ Ep->MaxPacket = MaxPacket;
- Ep->HubAddr = 0;
- Ep->HubPort = 0;
+ Ep->HubAddr = 0;
+ Ep->HubPort = 0;
if (DevSpeed != EFI_USB_SPEED_HIGH) {
ASSERT (Hub != NULL);
- Ep->HubAddr = Hub->TranslatorHubAddress;
- Ep->HubPort = Hub->TranslatorPortNumber;
+ Ep->HubAddr = Hub->TranslatorHubAddress;
+ Ep->HubPort = Hub->TranslatorPortNumber;
}
- Ep->Toggle = Toggle;
- Ep->Type = Type;
- Ep->PollRate = EhcConvertPollRate (Interval);
+ Ep->Toggle = Toggle;
+ Ep->Type = Type;
+ Ep->PollRate = EhcConvertPollRate (Interval);
- Urb->Request = Request;
- Urb->Data = Data;
- Urb->DataLen = DataLen;
- Urb->Callback = Callback;
- Urb->Context = Context;
+ Urb->Request = Request;
+ Urb->Data = Data;
+ Urb->DataLen = DataLen;
+ Urb->Callback = Callback;
+ Urb->Context = Context;
- PciIo = Ehc->PciIo;
- Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
+ PciIo = Ehc->PciIo;
+ Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
if (Urb->Qh == NULL) {
goto ON_ERROR;
@@ -607,20 +598,20 @@ EhcCreateUrb ( // Map the request and user data
//
if (Request != NULL) {
- Len = sizeof (EFI_USB_DEVICE_REQUEST);
- MapOp = EfiPciIoOperationBusMasterRead;
- Status = PciIo->Map (PciIo, MapOp, Request, &Len, &PhyAddr, &Map);
+ Len = sizeof (EFI_USB_DEVICE_REQUEST);
+ MapOp = EfiPciIoOperationBusMasterRead;
+ Status = PciIo->Map (PciIo, MapOp, Request, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != sizeof (EFI_USB_DEVICE_REQUEST))) {
goto ON_ERROR;
}
- Urb->RequestPhy = (VOID *) ((UINTN) PhyAddr);
+ Urb->RequestPhy = (VOID *)((UINTN)PhyAddr);
Urb->RequestMap = Map;
}
if (Data != NULL) {
- Len = DataLen;
+ Len = DataLen;
if (Ep->Direction == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
@@ -628,14 +619,14 @@ EhcCreateUrb ( MapOp = EfiPciIoOperationBusMasterRead;
}
- Status = PciIo->Map (PciIo, MapOp, Data, &Len, &PhyAddr, &Map);
+ Status = PciIo->Map (PciIo, MapOp, Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != DataLen)) {
goto ON_ERROR;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
Status = EhcCreateQtds (Ehc, Urb);
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h index 6342bf6b1c..ae8bfc2ba7 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h @@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_URB_H_
#define _EFI_EHCI_URB_H_
-
typedef struct _EHC_QTD EHC_QTD;
typedef struct _EHC_QH EHC_QH;
typedef struct _URB URB;
@@ -24,51 +23,51 @@ typedef struct _URB URB; #define EHC_INT_TRANSFER_SYNC 0x04
#define EHC_INT_TRANSFER_ASYNC 0x08
-#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
-#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
-#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
+#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
+#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// Hardware related bit definitions
//
-#define EHC_TYPE_ITD 0x00
-#define EHC_TYPE_QH 0x02
-#define EHC_TYPE_SITD 0x04
-#define EHC_TYPE_FSTN 0x06
-
-#define QH_NAK_RELOAD 3
-#define QH_HSHBW_MULTI 1
-
-#define QTD_MAX_ERR 3
-#define QTD_PID_OUTPUT 0x00
-#define QTD_PID_INPUT 0x01
-#define QTD_PID_SETUP 0x02
-
-#define QTD_STAT_DO_OUT 0
-#define QTD_STAT_DO_SS 0
-#define QTD_STAT_DO_PING 0x01
-#define QTD_STAT_DO_CS 0x02
-#define QTD_STAT_TRANS_ERR 0x08
-#define QTD_STAT_BABBLE_ERR 0x10
-#define QTD_STAT_BUFF_ERR 0x20
-#define QTD_STAT_HALTED 0x40
-#define QTD_STAT_ACTIVE 0x80
-#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
-
-#define QTD_MAX_BUFFER 4
-#define QTD_BUF_LEN 4096
-#define QTD_BUF_MASK 0x0FFF
-
-#define QH_MICROFRAME_0 0x01
-#define QH_MICROFRAME_1 0x02
-#define QH_MICROFRAME_2 0x04
-#define QH_MICROFRAME_3 0x08
-#define QH_MICROFRAME_4 0x10
-#define QH_MICROFRAME_5 0x20
-#define QH_MICROFRAME_6 0x40
-#define QH_MICROFRAME_7 0x80
-
-#define USB_ERR_SHORT_PACKET 0x200
+#define EHC_TYPE_ITD 0x00
+#define EHC_TYPE_QH 0x02
+#define EHC_TYPE_SITD 0x04
+#define EHC_TYPE_FSTN 0x06
+
+#define QH_NAK_RELOAD 3
+#define QH_HSHBW_MULTI 1
+
+#define QTD_MAX_ERR 3
+#define QTD_PID_OUTPUT 0x00
+#define QTD_PID_INPUT 0x01
+#define QTD_PID_SETUP 0x02
+
+#define QTD_STAT_DO_OUT 0
+#define QTD_STAT_DO_SS 0
+#define QTD_STAT_DO_PING 0x01
+#define QTD_STAT_DO_CS 0x02
+#define QTD_STAT_TRANS_ERR 0x08
+#define QTD_STAT_BABBLE_ERR 0x10
+#define QTD_STAT_BUFF_ERR 0x20
+#define QTD_STAT_HALTED 0x40
+#define QTD_STAT_ACTIVE 0x80
+#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
+
+#define QTD_MAX_BUFFER 4
+#define QTD_BUF_LEN 4096
+#define QTD_BUF_MASK 0x0FFF
+
+#define QH_MICROFRAME_0 0x01
+#define QH_MICROFRAME_1 0x02
+#define QH_MICROFRAME_2 0x04
+#define QH_MICROFRAME_3 0x08
+#define QH_MICROFRAME_4 0x10
+#define QH_MICROFRAME_5 0x20
+#define QH_MICROFRAME_6 0x40
+#define QH_MICROFRAME_7 0x80
+
+#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -77,7 +76,7 @@ typedef struct _URB URB; #define QH_LINK(Addr, Type, Term) \
((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
-#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
+#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
//
// The defination of EHCI hardware used data structure for
@@ -87,77 +86,76 @@ typedef struct _URB URB; //
#pragma pack(1)
typedef struct {
- UINT32 NextQtd;
- UINT32 AltNext;
-
- UINT32 Status : 8;
- UINT32 Pid : 2;
- UINT32 ErrCnt : 2;
- UINT32 CurPage : 3;
- UINT32 Ioc : 1;
- UINT32 TotalBytes : 15;
- UINT32 DataToggle : 1;
-
- UINT32 Page[5];
- UINT32 PageHigh[5];
+ UINT32 NextQtd;
+ UINT32 AltNext;
+
+ UINT32 Status : 8;
+ UINT32 Pid : 2;
+ UINT32 ErrCnt : 2;
+ UINT32 CurPage : 3;
+ UINT32 Ioc : 1;
+ UINT32 TotalBytes : 15;
+ UINT32 DataToggle : 1;
+
+ UINT32 Page[5];
+ UINT32 PageHigh[5];
} QTD_HW;
typedef struct {
- UINT32 HorizonLink;
+ UINT32 HorizonLink;
//
// Endpoint capabilities/Characteristics DWord 1 and DWord 2
//
- UINT32 DeviceAddr : 7;
- UINT32 Inactive : 1;
- UINT32 EpNum : 4;
- UINT32 EpSpeed : 2;
- UINT32 DtCtrl : 1;
- UINT32 ReclaimHead : 1;
- UINT32 MaxPacketLen : 11;
- UINT32 CtrlEp : 1;
- UINT32 NakReload : 4;
-
- UINT32 SMask : 8;
- UINT32 CMask : 8;
- UINT32 HubAddr : 7;
- UINT32 PortNum : 7;
- UINT32 Multiplier : 2;
+ UINT32 DeviceAddr : 7;
+ UINT32 Inactive : 1;
+ UINT32 EpNum : 4;
+ UINT32 EpSpeed : 2;
+ UINT32 DtCtrl : 1;
+ UINT32 ReclaimHead : 1;
+ UINT32 MaxPacketLen : 11;
+ UINT32 CtrlEp : 1;
+ UINT32 NakReload : 4;
+
+ UINT32 SMask : 8;
+ UINT32 CMask : 8;
+ UINT32 HubAddr : 7;
+ UINT32 PortNum : 7;
+ UINT32 Multiplier : 2;
//
// Transaction execution overlay area
//
- UINT32 CurQtd;
- UINT32 NextQtd;
- UINT32 AltQtd;
-
- UINT32 Status : 8;
- UINT32 Pid : 2;
- UINT32 ErrCnt : 2;
- UINT32 CurPage : 3;
- UINT32 Ioc : 1;
- UINT32 TotalBytes : 15;
- UINT32 DataToggle : 1;
-
- UINT32 Page[5];
- UINT32 PageHigh[5];
+ UINT32 CurQtd;
+ UINT32 NextQtd;
+ UINT32 AltQtd;
+
+ UINT32 Status : 8;
+ UINT32 Pid : 2;
+ UINT32 ErrCnt : 2;
+ UINT32 CurPage : 3;
+ UINT32 Ioc : 1;
+ UINT32 TotalBytes : 15;
+ UINT32 DataToggle : 1;
+
+ UINT32 Page[5];
+ UINT32 PageHigh[5];
} QH_HW;
#pragma pack()
-
//
// Endpoint address and its capabilities
//
typedef struct _USB_ENDPOINT {
- UINT8 DevAddr;
- UINT8 EpAddr; // Endpoint address, no direction encoded in
- EFI_USB_DATA_DIRECTION Direction;
- UINT8 DevSpeed;
- UINTN MaxPacket;
- UINT8 HubAddr;
- UINT8 HubPort;
- UINT8 Toggle; // Data toggle, not used for control transfer
- UINTN Type;
- UINTN PollRate; // Polling interval used by EHCI
+ UINT8 DevAddr;
+ UINT8 EpAddr; // Endpoint address, no direction encoded in
+ EFI_USB_DATA_DIRECTION Direction;
+ UINT8 DevSpeed;
+ UINTN MaxPacket;
+ UINT8 HubAddr;
+ UINT8 HubPort;
+ UINT8 Toggle; // Data toggle, not used for control transfer
+ UINTN Type;
+ UINTN PollRate; // Polling interval used by EHCI
} USB_ENDPOINT;
//
@@ -165,11 +163,11 @@ typedef struct _USB_ENDPOINT { // QTD generated from a URB. Don't add fields before QtdHw.
//
struct _EHC_QTD {
- QTD_HW QtdHw;
- UINT32 Signature;
- LIST_ENTRY QtdList; // The list of QTDs to one end point
- UINT8 *Data; // Buffer of the original data
- UINTN DataLen; // Original amount of data in this QTD
+ QTD_HW QtdHw;
+ UINT32 Signature;
+ LIST_ENTRY QtdList; // The list of QTDs to one end point
+ UINT8 *Data; // Buffer of the original data
+ UINTN DataLen; // Original amount of data in this QTD
};
//
@@ -188,11 +186,11 @@ struct _EHC_QTD { // as the reclamation header. New transfer is inserted after this QH.
//
struct _EHC_QH {
- QH_HW QhHw;
- UINT32 Signature;
- EHC_QH *NextQh; // The queue head pointed to by horizontal link
- LIST_ENTRY Qtds; // The list of QTDs to this queue head
- UINTN Interval;
+ QH_HW QhHw;
+ UINT32 Signature;
+ EHC_QH *NextQh; // The queue head pointed to by horizontal link
+ LIST_ENTRY Qtds; // The list of QTDs to this queue head
+ UINTN Interval;
};
//
@@ -200,38 +198,36 @@ struct _EHC_QH { // usb requests.
//
struct _URB {
- UINT32 Signature;
- LIST_ENTRY UrbList;
+ UINT32 Signature;
+ LIST_ENTRY UrbList;
//
// Transaction information
//
- USB_ENDPOINT Ep;
- EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
- VOID *RequestPhy; // Address of the mapped request
- VOID *RequestMap;
- VOID *Data;
- UINTN DataLen;
- VOID *DataPhy; // Address of the mapped user data
- VOID *DataMap;
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ USB_ENDPOINT Ep;
+ EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
+ VOID *RequestPhy; // Address of the mapped request
+ VOID *RequestMap;
+ VOID *Data;
+ UINTN DataLen;
+ VOID *DataPhy; // Address of the mapped user data
+ VOID *DataMap;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
//
// Schedule data
//
- EHC_QH *Qh;
+ EHC_QH *Qh;
//
// Transaction result
//
- UINT32 Result;
- UINTN Completed; // completed data length
- UINT8 DataToggle;
+ UINT32 Result;
+ UINTN Completed; // completed data length
+ UINT8 DataToggle;
};
-
-
/**
Create a single QTD to hold the data.
@@ -248,17 +244,15 @@ struct _URB { **/
EHC_QTD *
EhcCreateQtd (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 *Data,
- IN UINT8 *DataPhy,
- IN UINTN DataLen,
- IN UINT8 PktId,
- IN UINT8 Toggle,
- IN UINTN MaxPacket
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 *Data,
+ IN UINT8 *DataPhy,
+ IN UINTN DataLen,
+ IN UINT8 PktId,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket
);
-
-
/**
Allocate and initialize a EHCI queue head.
@@ -270,11 +264,10 @@ EhcCreateQtd ( **/
EHC_QH *
EhcCreateQh (
- IN USB2_HC_DEV *Ehci,
- IN USB_ENDPOINT *Ep
+ IN USB2_HC_DEV *Ehci,
+ IN USB_ENDPOINT *Ep
);
-
/**
Free an allocated URB. It is possible for it to be partially inited.
@@ -284,11 +277,10 @@ EhcCreateQh ( **/
VOID
EhcFreeUrb (
- IN USB2_HC_DEV *Ehc,
- IN URB *Urb
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb
);
-
/**
Create a new URB and its associated QTD.
@@ -312,19 +304,20 @@ EhcFreeUrb ( **/
URB *
EhcCreateUrb (
- IN USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
);
+
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c b/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c index f39d0b57c0..0a3ceb9f71 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.c @@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#include "Ehci.h"
-
/**
Allocate a block of memory to be used by the buffer pool.
@@ -22,17 +20,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Pages
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Pages
)
{
- USBHC_MEM_BLOCK *Block;
- EFI_PCI_IO_PROTOCOL *PciIo;
- VOID *BufHost;
- VOID *Mapping;
- EFI_PHYSICAL_ADDRESS MappedAddr;
- UINTN Bytes;
- EFI_STATUS Status;
+ USBHC_MEM_BLOCK *Block;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ UINTN Bytes;
+ EFI_STATUS Status;
PciIo = Pool->PciIo;
@@ -47,9 +45,9 @@ UsbHcAllocMemBlock ( //
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
- Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
- Block->Bits = AllocateZeroPool (Block->BitsLen);
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
+ Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
@@ -73,7 +71,7 @@ UsbHcAllocMemBlock ( goto FREE_BITARRAY;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -96,9 +94,9 @@ UsbHcAllocMemBlock ( goto FREE_BUFFER;
}
- Block->BufHost = BufHost;
- Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
- Block->Mapping = Mapping;
+ Block->BufHost = BufHost;
+ Block->Buf = (UINT8 *)((UINTN)MappedAddr);
+ Block->Mapping = Mapping;
return Block;
@@ -111,7 +109,6 @@ FREE_BITARRAY: return NULL;
}
-
/**
Free the memory block from the memory pool.
@@ -121,11 +118,11 @@ FREE_BITARRAY: **/
VOID
UsbHcFreeMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -141,7 +138,6 @@ UsbHcFreeMemBlock ( gBS->FreePool (Block);
}
-
/**
Alloc some memory from the block.
@@ -154,22 +150,22 @@ UsbHcFreeMemBlock ( **/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -185,13 +181,12 @@ UsbHcAllocMemFromBlock ( }
NEXT_BIT (Byte, Bit);
-
} else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -202,13 +197,13 @@ UsbHcAllocMemFromBlock ( //
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -226,16 +221,16 @@ UsbHcAllocMemFromBlock ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -249,7 +244,7 @@ UsbHcGetPciAddressForHostMem ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -258,12 +253,11 @@ UsbHcGetPciAddressForHostMem ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
-
/**
Insert the memory block to the pool's list of the blocks.
@@ -273,8 +267,8 @@ UsbHcGetPciAddressForHostMem ( **/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -282,7 +276,6 @@ UsbHcInsertMemBlockToPool ( Head->Next = Block;
}
-
/**
Is the memory block empty?
@@ -294,10 +287,10 @@ UsbHcInsertMemBlockToPool ( **/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -308,7 +301,6 @@ UsbHcIsMemBlockEmpty ( return TRUE;
}
-
/**
Unlink the memory block from the pool's list.
@@ -318,11 +310,11 @@ UsbHcIsMemBlockEmpty ( **/
VOID
UsbHcUnlinkMemBlock (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *BlockToUnlink
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -335,7 +327,6 @@ UsbHcUnlinkMemBlock ( }
}
-
/**
Initialize the memory management pool for the host controller.
@@ -355,7 +346,7 @@ UsbHcInitMemPool ( IN UINT32 Which4G
)
{
- USBHC_MEM_POOL *Pool;
+ USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -376,7 +367,6 @@ UsbHcInitMemPool ( return Pool;
}
-
/**
Release the memory management pool.
@@ -388,10 +378,10 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -410,7 +400,6 @@ UsbHcFreeMemPool ( return EFI_SUCCESS;
}
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -423,16 +412,16 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -487,7 +476,6 @@ UsbHcAllocateMem ( return Mem;
}
-
/**
Free the allocated memory back to the memory pool.
@@ -498,22 +486,22 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -524,8 +512,8 @@ UsbHcFreeMem ( //
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -533,7 +521,7 @@ UsbHcFreeMem ( for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -556,5 +544,5 @@ UsbHcFreeMem ( UsbHcFreeMemBlock (Pool, Block);
}
- return ;
+ return;
}
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h index ace20832c1..999e795386 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_MEM_H_
#define _EFI_EHCI_MEM_H_
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -20,13 +20,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
@@ -35,16 +35,16 @@ struct _USBHC_MEM_BLOCK { // data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- EFI_PCI_IO_PROTOCOL *PciIo;
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -63,8 +63,6 @@ typedef struct _USBHC_MEM_POOL { } \
} while (0)
-
-
/**
Initialize the memory management pool for the host controller.
@@ -84,7 +82,6 @@ UsbHcInitMemPool ( IN UINT32 Which4G
);
-
/**
Release the memory management pool.
@@ -96,10 +93,9 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
);
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -112,11 +108,10 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
);
-
/**
Free the allocated memory back to the memory pool.
@@ -127,9 +122,9 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -143,9 +138,9 @@ UsbHcFreeMem ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c b/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c index 63870a129a..320fb30bc1 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c @@ -39,8 +39,8 @@ IoMmuMap ( OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- UINT64 Attribute;
+ EFI_STATUS Status;
+ UINT64 Attribute;
if (IoMmu != NULL) {
Status = IoMmu->Map (
@@ -54,23 +54,25 @@ IoMmuMap ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
switch (Operation) {
- case EdkiiIoMmuOperationBusMasterRead:
- case EdkiiIoMmuOperationBusMasterRead64:
- Attribute = EDKII_IOMMU_ACCESS_READ;
- break;
- case EdkiiIoMmuOperationBusMasterWrite:
- case EdkiiIoMmuOperationBusMasterWrite64:
- Attribute = EDKII_IOMMU_ACCESS_WRITE;
- break;
- case EdkiiIoMmuOperationBusMasterCommonBuffer:
- case EdkiiIoMmuOperationBusMasterCommonBuffer64:
- Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
- break;
- default:
- ASSERT(FALSE);
- return EFI_INVALID_PARAMETER;
+ case EdkiiIoMmuOperationBusMasterRead:
+ case EdkiiIoMmuOperationBusMasterRead64:
+ Attribute = EDKII_IOMMU_ACCESS_READ;
+ break;
+ case EdkiiIoMmuOperationBusMasterWrite:
+ case EdkiiIoMmuOperationBusMasterWrite64:
+ Attribute = EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ case EdkiiIoMmuOperationBusMasterCommonBuffer:
+ case EdkiiIoMmuOperationBusMasterCommonBuffer64:
+ Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -82,10 +84,11 @@ IoMmuMap ( return Status;
}
} else {
- *DeviceAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
- *Mapping = NULL;
- Status = EFI_SUCCESS;
+ *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
+ *Mapping = NULL;
+ Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -98,8 +101,8 @@ IoMmuMap ( **/
VOID
IoMmuUnmap (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN VOID *Mapping
)
{
if (IoMmu != NULL) {
@@ -140,9 +143,9 @@ IoMmuAllocateBuffer ( UINTN NumberOfBytes;
EFI_PHYSICAL_ADDRESS HostPhyAddress;
- *HostAddress = NULL;
+ *HostAddress = NULL;
*DeviceAddress = 0;
- *Mapping = NULL;
+ *Mapping = NULL;
if (IoMmu != NULL) {
Status = IoMmu->AllocateBuffer (
@@ -157,19 +160,20 @@ IoMmuAllocateBuffer ( }
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
- Status = IoMmu->Map (
- IoMmu,
- EdkiiIoMmuOperationBusMasterCommonBuffer,
- *HostAddress,
- &NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+ Status = IoMmu->Map (
+ IoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ *HostAddress,
+ &NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
*HostAddress = NULL;
return EFI_OUT_OF_RESOURCES;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -178,7 +182,7 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
IoMmu->Unmap (IoMmu, *Mapping);
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
- *Mapping = NULL;
+ *Mapping = NULL;
*HostAddress = NULL;
return Status;
}
@@ -191,10 +195,12 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *) (UINTN) HostPhyAddress;
+
+ *HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
- *Mapping = NULL;
+ *Mapping = NULL;
}
+
return Status;
}
@@ -209,10 +215,10 @@ IoMmuAllocateBuffer ( **/
VOID
IoMmuFreeBuffer (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
)
{
if (IoMmu != NULL) {
@@ -230,14 +236,13 @@ IoMmuFreeBuffer ( **/
VOID
IoMmuInit (
- OUT EDKII_IOMMU_PPI **IoMmu
+ OUT EDKII_IOMMU_PPI **IoMmu
)
{
PeiServicesLocatePpi (
&gEdkiiIoMmuPpiGuid,
0,
NULL,
- (VOID **) IoMmu
+ (VOID **)IoMmu
);
}
-
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c index cd1f87911b..37dd9012e2 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c @@ -15,19 +15,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
- {PORTSC_CONN, USB_PORT_STAT_CONNECTION},
- {PORTSC_ENABLED, USB_PORT_STAT_ENABLE},
- {PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND},
- {PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT},
- {PORTSC_RESET, USB_PORT_STAT_RESET},
- {PORTSC_POWER, USB_PORT_STAT_POWER},
- {PORTSC_OWNER, USB_PORT_STAT_OWNER}
+ { PORTSC_CONN, USB_PORT_STAT_CONNECTION },
+ { PORTSC_ENABLED, USB_PORT_STAT_ENABLE },
+ { PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND },
+ { PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT },
+ { PORTSC_RESET, USB_PORT_STAT_RESET },
+ { PORTSC_POWER, USB_PORT_STAT_POWER },
+ { PORTSC_OWNER, USB_PORT_STAT_OWNER }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
- {PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION},
- {PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE},
- {PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT}
+ { PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION },
+ { PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE },
+ { PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT }
};
/**
@@ -41,11 +41,11 @@ USB_PORT_STATE_MAP mUsbPortChangeMap[] = { **/
UINT32
EhcReadOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (Ehc->CapLen != 0);
@@ -64,16 +64,14 @@ EhcReadOpReg ( **/
VOID
EhcWriteOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
-
ASSERT (Ehc->CapLen != 0);
- MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);
-
+ MmioWrite32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);
}
/**
@@ -86,12 +84,12 @@ EhcWriteOpReg ( **/
VOID
EhcSetOpRegBit (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data |= Bit;
@@ -108,12 +106,12 @@ EhcSetOpRegBit ( **/
VOID
EhcClearOpRegBit (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data &= ~Bit;
@@ -136,14 +134,14 @@ EhcClearOpRegBit ( **/
EFI_STATUS
EhcWaitOpRegBit (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- UINT32 Index;
+ UINT32 Index;
for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {
if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {
@@ -167,13 +165,13 @@ EhcWaitOpRegBit ( **/
UINT32
EhcReadCapRegister (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
- Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset);
+ Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Offset);
return Data;
}
@@ -191,12 +189,12 @@ EhcReadCapRegister ( **/
EFI_STATUS
EhcSetAndWaitDoorBell (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_STATUS Status;
+ UINT32 Data;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);
@@ -224,7 +222,7 @@ EhcSetAndWaitDoorBell ( **/
VOID
EhcAckAllInterrupt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
@@ -243,11 +241,11 @@ EhcAckAllInterrupt ( **/
EFI_STATUS
EhcEnablePeriodSchd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
@@ -267,11 +265,11 @@ EhcEnablePeriodSchd ( **/
EFI_STATUS
EhcEnableAsyncSchd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
@@ -290,7 +288,7 @@ EhcEnableAsyncSchd ( **/
BOOLEAN
EhcIsHalt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);
@@ -307,7 +305,7 @@ EhcIsHalt ( **/
BOOLEAN
EhcIsSysError (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);
@@ -325,11 +323,11 @@ EhcIsSysError ( **/
EFI_STATUS
EhcResetHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Host can only be reset when it is halt. If not so, halt it
@@ -359,11 +357,11 @@ EhcResetHC ( **/
EFI_STATUS
EhcHaltHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);
@@ -382,11 +380,11 @@ EhcHaltHC ( **/
EFI_STATUS
EhcRunHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);
@@ -401,12 +399,12 @@ EhcRunHC ( **/
VOID
EhcPowerOnAllPorts (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
- UINT8 PortNumber;
- UINT8 Index;
- UINT32 RegVal;
+ UINT8 PortNumber;
+ UINT8 Index;
+ UINT32 RegVal;
PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);
for (Index = 0; Index < PortNumber; Index++) {
@@ -414,7 +412,7 @@ EhcPowerOnAllPorts ( // Do not clear port status bits on initialization. Otherwise devices will
// not enumerate properly at startup.
//
- RegVal = EhcReadOpReg(Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);
+ RegVal = EhcReadOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);
RegVal &= ~PORTSC_CHANGE_MASK;
RegVal |= PORTSC_POWER;
EhcWriteOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index, RegVal);
@@ -438,12 +436,12 @@ EhcPowerOnAllPorts ( **/
EFI_STATUS
EhcInitHC (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS TempPtr;
- UINTN PageNumber;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS TempPtr;
+ UINTN PageNumber;
ASSERT (EhcIsHalt (Ehc));
@@ -454,13 +452,14 @@ EhcInitHC ( if (Ehc->PeriodFrame != NULL) {
EhcFreeSched (Ehc);
}
- PageNumber = sizeof(PEI_URB)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
- Ehc->Urb = (PEI_URB *) ((UINTN) TempPtr);
+
+ PageNumber = sizeof (PEI_URB)/PAGESIZE +1;
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
+ Ehc->Urb = (PEI_URB *)((UINTN)TempPtr);
if (Ehc->Urb == NULL) {
return Status;
}
@@ -473,6 +472,7 @@ EhcInitHC ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// 1. Program the CTRLDSSEGMENT register with the high 32 bit addr
//
@@ -563,15 +563,16 @@ EhcBulkTransfer ( OUT UINT32 *TransferResult
)
{
- PEI_USB2_HC_DEV *Ehc;
- PEI_URB *Urb;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ PEI_URB *Urb;
+ EFI_STATUS Status;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -581,11 +582,12 @@ EhcBulkTransfer ( if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {
+ ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))
+ {
return EFI_INVALID_PARAMETER;
}
- Ehc =PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -656,13 +658,13 @@ ON_EXIT: EFI_STATUS
EFIAPI
EhcGetRootHubPortNumber (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- OUT UINT8 *PortNumber
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ OUT UINT8 *PortNumber
)
{
+ PEI_USB2_HC_DEV *EhcDev;
- PEI_USB2_HC_DEV *EhcDev;
EhcDev = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
if (PortNumber == NULL) {
@@ -671,7 +673,6 @@ EhcGetRootHubPortNumber ( *PortNumber = (UINT8)(EhcDev->HcStructParams & HCSP_NPORTS);
return EFI_SUCCESS;
-
}
/**
@@ -692,20 +693,20 @@ EhcGetRootHubPortNumber ( EFI_STATUS
EFIAPI
EhcClearRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- PEI_USB2_HC_DEV *Ehc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
- Status = EFI_SUCCESS;
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -714,82 +715,82 @@ EhcClearRootHubPortFeature ( goto ON_EXIT;
}
- Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
- State = EhcReadOpReg (Ehc, Offset);
+ Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
+ State = EhcReadOpReg (Ehc, Offset);
State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Clear PORT_ENABLE feature means disable port.
- //
- State &= ~PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnable:
+ //
+ // Clear PORT_ENABLE feature means disable port.
+ //
+ State &= ~PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortSuspend:
- //
- // A write of zero to this bit is ignored by the host
- // controller. The host controller will unconditionally
- // set this bit to a zero when:
- // 1. software sets the Forct Port Resume bit to a zero from a one.
- // 2. software sets the Port Reset bit to a one frome a zero.
- //
- State &= ~PORSTSC_RESUME;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ //
+ // A write of zero to this bit is ignored by the host
+ // controller. The host controller will unconditionally
+ // set this bit to a zero when:
+ // 1. software sets the Forct Port Resume bit to a zero from a one.
+ // 2. software sets the Port Reset bit to a one frome a zero.
+ //
+ State &= ~PORSTSC_RESUME;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortReset:
- //
- // Clear PORT_RESET means clear the reset signal.
- //
- State &= ~PORTSC_RESET;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortReset:
+ //
+ // Clear PORT_RESET means clear the reset signal.
+ //
+ State &= ~PORTSC_RESET;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortOwner:
- //
- // Clear port owner means this port owned by EHC
- //
- State &= ~PORTSC_OWNER;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortOwner:
+ //
+ // Clear port owner means this port owned by EHC
+ //
+ State &= ~PORTSC_OWNER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortConnectChange:
- //
- // Clear connect status change
- //
- State |= PORTSC_CONN_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortConnectChange:
+ //
+ // Clear connect status change
+ //
+ State |= PORTSC_CONN_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortEnableChange:
- //
- // Clear enable status change
- //
- State |= PORTSC_ENABLE_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnableChange:
+ //
+ // Clear enable status change
+ //
+ State |= PORTSC_ENABLE_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortOverCurrentChange:
- //
- // Clear PortOverCurrent change
- //
- State |= PORTSC_OVERCUR_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortOverCurrentChange:
+ //
+ // Clear PortOverCurrent change
+ //
+ State |= PORTSC_OVERCUR_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortPower:
- case EfiUsbPortSuspendChange:
- case EfiUsbPortResetChange:
- //
- // Not supported or not related operation
- //
- break;
+ case EfiUsbPortPower:
+ case EfiUsbPortSuspendChange:
+ case EfiUsbPortResetChange:
+ //
+ // Not supported or not related operation
+ //
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
+ default:
+ Status = EFI_INVALID_PARAMETER;
+ break;
}
ON_EXIT:
@@ -812,20 +813,20 @@ ON_EXIT: EFI_STATUS
EFIAPI
EhcSetRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- PEI_USB2_HC_DEV *Ehc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
- Status = EFI_SUCCESS;
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -834,8 +835,8 @@ EhcSetRootHubPortFeature ( goto ON_EXIT;
}
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
- State = EhcReadOpReg (Ehc, Offset);
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
+ State = EhcReadOpReg (Ehc, Offset);
//
// Mask off the port status change bits, these bits are
@@ -844,54 +845,54 @@ EhcSetRootHubPortFeature ( State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Sofeware can't set this bit, Port can only be enable by
- // EHCI as a part of the reset and enable
- //
- State |= PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnable:
+ //
+ // Sofeware can't set this bit, Port can only be enable by
+ // EHCI as a part of the reset and enable
+ //
+ State |= PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortSuspend:
- State |= PORTSC_SUSPEND;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ State |= PORTSC_SUSPEND;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortReset:
- //
- // Make sure Host Controller not halt before reset it
- //
- if (EhcIsHalt (Ehc)) {
- Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
+ case EfiUsbPortReset:
+ //
+ // Make sure Host Controller not halt before reset it
+ //
+ if (EhcIsHalt (Ehc)) {
+ Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
- if (EFI_ERROR (Status)) {
- break;
+ if (EFI_ERROR (Status)) {
+ break;
+ }
}
- }
- //
- // Set one to PortReset bit must also set zero to PortEnable bit
- //
- State |= PORTSC_RESET;
- State &= ~PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ //
+ // Set one to PortReset bit must also set zero to PortEnable bit
+ //
+ State |= PORTSC_RESET;
+ State &= ~PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortPower:
- //
- // Not supported, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortPower:
+ //
+ // Not supported, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- case EfiUsbPortOwner:
- State |= PORTSC_OWNER;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortOwner:
+ State |= PORTSC_OWNER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -914,26 +915,26 @@ ON_EXIT: EFI_STATUS
EFIAPI
EhcGetRootHubPortStatus (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- OUT EFI_USB_PORT_STATUS *PortStatus
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- PEI_USB2_HC_DEV *Ehc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- UINTN Index;
- UINTN MapSize;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ UINTN Index;
+ UINTN MapSize;
+ EFI_STATUS Status;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
}
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);
- Status = EFI_SUCCESS;
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -942,11 +943,11 @@ EhcGetRootHubPortStatus ( goto ON_EXIT;
}
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
- PortStatus->PortStatus = 0;
- PortStatus->PortChangeStatus = 0;
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
+ PortStatus->PortStatus = 0;
+ PortStatus->PortChangeStatus = 0;
- State = EhcReadOpReg (Ehc, Offset);
+ State = EhcReadOpReg (Ehc, Offset);
//
// Identify device speed. If in K state, it is low speed.
@@ -956,7 +957,6 @@ EhcGetRootHubPortStatus ( //
if (EHC_BIT_IS_SET (State, PORTSC_LINESTATE_K)) {
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
-
} else if (EHC_BIT_IS_SET (State, PORTSC_ENABLED)) {
PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
}
@@ -968,7 +968,7 @@ EhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
@@ -976,7 +976,7 @@ EhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -1027,10 +1027,10 @@ EhcControlTransfer ( OUT UINT32 *TransferResult
)
{
- PEI_USB2_HC_DEV *Ehc;
- PEI_URB *Urb;
- UINT8 Endpoint;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ PEI_URB *Urb;
+ UINT8 Endpoint;
+ EFI_STATUS Status;
//
// Validate parameters
@@ -1041,33 +1041,37 @@ EhcControlTransfer ( if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
- (TransferDirection != EfiUsbNoData)) {
+ (TransferDirection != EfiUsbNoData))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
- ((Data != NULL) || (*DataLength != 0))) {
+ ((Data != NULL) || (*DataLength != 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
- ((Data == NULL) || (*DataLength == 0))) {
+ ((Data == NULL) || (*DataLength == 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
- (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {
+ (MaximumPacketLength != 32) && (MaximumPacketLength != 64))
+ {
return EFI_INVALID_PARAMETER;
}
-
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {
+ ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))
+ {
return EFI_INVALID_PARAMETER;
}
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
@@ -1088,23 +1092,23 @@ EhcControlTransfer ( // endpoint is bidirectional. EhcCreateUrb expects this
// combination of Ep addr and its direction.
//
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
- Urb = EhcCreateUrb (
- Ehc,
- DeviceAddress,
- Endpoint,
- DeviceSpeed,
- 0,
- MaximumPacketLength,
- Translator,
- EHC_CTRL_TRANSFER,
- Request,
- Data,
- *DataLength,
- NULL,
- NULL,
- 1
- );
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
+ Urb = EhcCreateUrb (
+ Ehc,
+ DeviceAddress,
+ Endpoint,
+ DeviceSpeed,
+ 0,
+ MaximumPacketLength,
+ Translator,
+ EHC_CTRL_TRANSFER,
+ Request,
+ Data,
+ *DataLength,
+ NULL,
+ NULL,
+ 1
+ );
if (Urb == NULL) {
Status = EFI_OUT_OF_RESOURCES;
@@ -1152,7 +1156,7 @@ EhcEndOfPei ( IN VOID *Ppi
)
{
- PEI_USB2_HC_DEV *Ehc;
+ PEI_USB2_HC_DEV *Ehc;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY (NotifyDescriptor);
@@ -1177,14 +1181,14 @@ EhcPeimEntry ( IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
- EFI_STATUS Status;
- UINT8 Index;
- UINTN ControllerType;
- UINTN BaseAddress;
- UINTN MemPages;
- PEI_USB2_HC_DEV *EhcDev;
- EFI_PHYSICAL_ADDRESS TempPtr;
+ PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
+ EFI_STATUS Status;
+ UINT8 Index;
+ UINTN ControllerType;
+ UINTN BaseAddress;
+ UINTN MemPages;
+ PEI_USB2_HC_DEV *EhcDev;
+ EFI_PHYSICAL_ADDRESS TempPtr;
//
// Shadow this PEIM to run from memory
@@ -1197,7 +1201,7 @@ EhcPeimEntry ( &gPeiUsbControllerPpiGuid,
0,
NULL,
- (VOID **) &ChipSetUsbControllerPpi
+ (VOID **)&ChipSetUsbControllerPpi
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
@@ -1206,7 +1210,7 @@ EhcPeimEntry ( Index = 0;
while (TRUE) {
Status = ChipSetUsbControllerPpi->GetUsbController (
- (EFI_PEI_SERVICES **) PeiServices,
+ (EFI_PEI_SERVICES **)PeiServices,
ChipSetUsbControllerPpi,
Index,
&ControllerType,
@@ -1228,24 +1232,23 @@ EhcPeimEntry ( }
MemPages = sizeof (PEI_USB2_HC_DEV) / PAGESIZE + 1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- MemPages,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ MemPages,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- ZeroMem((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);
- EhcDev = (PEI_USB2_HC_DEV *) ((UINTN) TempPtr);
+ ZeroMem ((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);
+ EhcDev = (PEI_USB2_HC_DEV *)((UINTN)TempPtr);
EhcDev->Signature = USB2_HC_DEV_SIGNATURE;
IoMmuInit (&EhcDev->IoMmu);
- EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;
-
+ EhcDev->UsbHostControllerBaseAddress = (UINT32)BaseAddress;
EhcDev->HcStructParams = EhcReadCapRegister (EhcDev, EHC_HCSPARAMS_OFFSET);
EhcDev->HcCapParams = EhcReadCapRegister (EhcDev, EHC_HCCPARAMS_OFFSET);
@@ -1258,16 +1261,16 @@ EhcPeimEntry ( return Status;
}
- EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;
- EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;
- EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;
- EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;
- EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;
- EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
+ EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;
+ EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;
+ EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;
+ EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;
+ EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;
+ EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
EhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
- EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;
+ EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
+ EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;
Status = PeiServicesInstallPpi (&EhcDev->PpiDescriptor);
if (EFI_ERROR (Status)) {
@@ -1275,8 +1278,8 @@ EhcPeimEntry ( continue;
}
- EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
+ EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+ EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
EhcDev->EndOfPeiNotifyList.Notify = EhcEndOfPei;
PeiServicesNotifyPpi (&EhcDev->EndOfPeiNotifyList);
@@ -1296,12 +1299,11 @@ EhcPeimEntry ( **/
EFI_STATUS
InitializeUsbHC (
- IN PEI_USB2_HC_DEV *EhcDev
+ IN PEI_USB2_HC_DEV *EhcDev
)
{
EFI_STATUS Status;
-
EhcResetHC (EhcDev, EHC_RESET_TIMEOUT);
Status = EhcInitHC (EhcDev);
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h index 8e5b6418e6..c83886c240 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h @@ -28,46 +28,44 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;
-#define EFI_LIST_ENTRY LIST_ENTRY
+#define EFI_LIST_ENTRY LIST_ENTRY
#include "UsbHcMem.h"
#include "EhciReg.h"
#include "EhciUrb.h"
#include "EhciSched.h"
-#define EFI_USB_SPEED_FULL 0x0000
-#define EFI_USB_SPEED_LOW 0x0001
-#define EFI_USB_SPEED_HIGH 0x0002
+#define EFI_USB_SPEED_FULL 0x0000
+#define EFI_USB_SPEED_LOW 0x0001
+#define EFI_USB_SPEED_HIGH 0x0002
-#define PAGESIZE 4096
+#define PAGESIZE 4096
-#define EHC_1_MICROSECOND 1
-#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
-#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
+#define EHC_1_MICROSECOND 1
+#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
+#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
//
// EHCI register operation timeout, set by experience
//
-#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
-#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
-
+#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
+#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
-#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
+#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
//
// Sync transfer polling interval, set by experience.
//
-#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
-
-#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
+#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
+#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
-#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
-#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
+#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
+#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
(EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
@@ -75,18 +73,18 @@ typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV; #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
struct _PEI_USB2_HC_DEV {
- UINTN Signature;
- PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
- EDKII_IOMMU_PPI *IoMmu;
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ UINTN Signature;
+ PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
+ EDKII_IOMMU_PPI *IoMmu;
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
//
// EndOfPei callback is used to stop the EHC DMA operation
// after exit PEI phase.
//
- EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
- UINT32 UsbHostControllerBaseAddress;
- PEI_URB *Urb;
- USBHC_MEM_POOL *MemPool;
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
+ UINT32 UsbHostControllerBaseAddress;
+ PEI_URB *Urb;
+ USBHC_MEM_POOL *MemPool;
//
// Schedule data shared between asynchronous and periodic
@@ -97,36 +95,36 @@ struct _PEI_USB2_HC_DEV { // For control transfer, even the short read happens, try the
// status stage.
//
- PEI_EHC_QTD *ShortReadStop;
- EFI_EVENT PollTimer;
+ PEI_EHC_QTD *ShortReadStop;
+ EFI_EVENT PollTimer;
//
// Asynchronous(bulk and control) transfer schedule data:
// ReclaimHead is used as the head of the asynchronous transfer
// list. It acts as the reclamation header.
//
- PEI_EHC_QH *ReclaimHead;
+ PEI_EHC_QH *ReclaimHead;
//
// Periodic (interrupt) transfer schedule data:
//
- VOID *PeriodFrame; // Mapped as common buffer
- VOID *PeriodFrameMap;
+ VOID *PeriodFrame; // Mapped as common buffer
+ VOID *PeriodFrameMap;
- PEI_EHC_QH *PeriodOne;
- EFI_LIST_ENTRY AsyncIntTransfers;
+ PEI_EHC_QH *PeriodOne;
+ EFI_LIST_ENTRY AsyncIntTransfers;
//
// EHCI configuration data
//
- UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
- UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
- UINT32 CapLen; // Capability length
- UINT32 High32bitAddr;
+ UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
+ UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
+ UINT32 CapLen; // Capability length
+ UINT32 High32bitAddr;
};
-#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
-#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
/**
@param EhcDev EHCI Device.
@@ -137,7 +135,7 @@ struct _PEI_USB2_HC_DEV { **/
EFI_STATUS
InitializeUsbHC (
- IN PEI_USB2_HC_DEV *EhcDev
+ IN PEI_USB2_HC_DEV *EhcDev
);
/**
@@ -154,9 +152,9 @@ InitializeUsbHC ( **/
USBHC_MEM_POOL *
UsbHcInitMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN BOOLEAN Check4G,
- IN UINT32 Which4G
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN BOOLEAN Check4G,
+ IN UINT32 Which4G
)
;
@@ -172,8 +170,8 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool
)
;
@@ -190,9 +188,9 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
;
@@ -207,10 +205,10 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
;
@@ -253,8 +251,8 @@ IoMmuMap ( **/
VOID
IoMmuUnmap (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN VOID *Mapping
);
/**
@@ -296,10 +294,10 @@ IoMmuAllocateBuffer ( **/
VOID
IoMmuFreeBuffer (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
);
/**
@@ -310,7 +308,7 @@ IoMmuFreeBuffer ( **/
VOID
IoMmuInit (
- OUT EDKII_IOMMU_PPI **IoMmu
+ OUT EDKII_IOMMU_PPI **IoMmu
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h index 98113519a5..2a438f1bbe 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h @@ -10,20 +10,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_REG_H_
#define _EFI_EHCI_REG_H_
-
-
//
// Capability register offset
//
-#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
-#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
-#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
-#define HCSP_NPORTS 0x0F // Number of root hub port
-#define HCCP_64BIT 0x01 // 64-bit addressing capability
+#define HCSP_NPORTS 0x0F // Number of root hub port
+#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -38,61 +36,61 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
-#define EHC_FRAME_LEN 1024
+#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
-#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
-
-#define USBCMD_RUN 0x01 // Run/stop
-#define USBCMD_RESET 0x02 // Start the host controller reset
-#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
-#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
-#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
-
-#define USBSTS_IAA 0x20 // Interrupt on async advance
-#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
-#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
-#define USBSTS_HALT 0x1000 // Host controller halted
-#define USBSTS_SYS_ERROR 0x10 // Host system error
-#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
+
+#define USBCMD_RUN 0x01 // Run/stop
+#define USBCMD_RESET 0x02 // Start the host controller reset
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
+
+#define USBSTS_IAA 0x20 // Interrupt on async advance
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
+#define USBSTS_HALT 0x1000 // Host controller halted
+#define USBSTS_SYS_ERROR 0x10 // Host system error
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
-#define PORTSC_CONN 0x01 // Current Connect Status
-#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
-#define PORTSC_ENABLED 0x04 // Port Enable / Disable
-#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
-#define PORTSC_OVERCUR 0x10 // Over current Active
-#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
-#define PORSTSC_RESUME 0x40 // Force Port Resume
-#define PORTSC_SUSPEND 0x80 // Port Suspend State
-#define PORTSC_RESET 0x100 // Port Reset
-#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
-#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
-#define PORTSC_POWER 0x1000 // Port Power
-#define PORTSC_OWNER 0x2000 // Port Owner
-#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
+#define PORTSC_CONN 0x01 // Current Connect Status
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
+#define PORTSC_OVERCUR 0x10 // Over current Active
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
+#define PORSTSC_RESUME 0x40 // Force Port Resume
+#define PORTSC_SUSPEND 0x80 // Port Suspend State
+#define PORTSC_RESET 0x100 // Port Reset
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
+#define PORTSC_POWER 0x1000 // Port Power
+#define PORTSC_OWNER 0x2000 // Port Owner
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
-#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
-#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
+#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
-#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
+#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
- UINT16 HwState;
- UINT16 UefiState;
+ UINT16 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -100,13 +98,12 @@ typedef struct { //
#pragma pack(1)
typedef struct {
- UINT8 Pi;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 Pi;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
-
/**
Read EHCI capability register.
@@ -118,8 +115,8 @@ typedef struct { **/
UINT32
EhcReadCapRegister (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
;
@@ -134,8 +131,8 @@ EhcReadCapRegister ( **/
UINT32
EhcReadOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
;
@@ -149,9 +146,9 @@ EhcReadOpReg ( **/
VOID
EhcWriteOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
;
@@ -163,7 +160,7 @@ EhcWriteOpReg ( **/
VOID
EhcClearLegacySupport (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -180,8 +177,8 @@ EhcClearLegacySupport ( **/
EFI_STATUS
EhcSetAndWaitDoorBell (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -194,7 +191,7 @@ EhcSetAndWaitDoorBell ( **/
VOID
EhcAckAllInterrupt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -209,7 +206,7 @@ EhcAckAllInterrupt ( **/
BOOLEAN
EhcIsHalt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -224,7 +221,7 @@ EhcIsHalt ( **/
BOOLEAN
EhcIsSysError (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -240,8 +237,8 @@ EhcIsSysError ( **/
EFI_STATUS
EhcResetHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -257,8 +254,8 @@ EhcResetHC ( **/
EFI_STATUS
EhcHaltHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -274,8 +271,8 @@ EhcHaltHC ( **/
EFI_STATUS
EhcRunHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -296,7 +293,7 @@ EhcRunHC ( **/
EFI_STATUS
EhcInitHC (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c index 311f501980..db2406b0d2 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c @@ -22,13 +22,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
EhcCreateHelpQ (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
- USB_ENDPOINT Ep;
- PEI_EHC_QH *Qh;
- QH_HW *QhHw;
- PEI_EHC_QTD *Qtd;
+ USB_ENDPOINT Ep;
+ PEI_EHC_QH *Qh;
+ QH_HW *QhHw;
+ PEI_EHC_QTD *Qtd;
//
// Create an inactive Qtd to terminate the short packet read.
@@ -39,25 +39,25 @@ EhcCreateHelpQ ( return EFI_OUT_OF_RESOURCES;
}
- Qtd->QtdHw.Status = QTD_STAT_HALTED;
- Ehc->ShortReadStop = Qtd;
+ Qtd->QtdHw.Status = QTD_STAT_HALTED;
+ Ehc->ShortReadStop = Qtd;
//
// Create a QH to act as the EHC reclamation header.
// Set the header to loopback to itself.
//
- Ep.DevAddr = 0;
- Ep.EpAddr = 1;
- Ep.Direction = EfiUsbDataIn;
- Ep.DevSpeed = EFI_USB_SPEED_HIGH;
- Ep.MaxPacket = 64;
- Ep.HubAddr = 0;
- Ep.HubPort = 0;
- Ep.Toggle = 0;
- Ep.Type = EHC_BULK_TRANSFER;
- Ep.PollRate = 1;
-
- Qh = EhcCreateQh (Ehc, &Ep);
+ Ep.DevAddr = 0;
+ Ep.EpAddr = 1;
+ Ep.Direction = EfiUsbDataIn;
+ Ep.DevSpeed = EFI_USB_SPEED_HIGH;
+ Ep.MaxPacket = 64;
+ Ep.HubAddr = 0;
+ Ep.HubPort = 0;
+ Ep.Toggle = 0;
+ Ep.Type = EHC_BULK_TRANSFER;
+ Ep.PollRate = 1;
+
+ Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -72,10 +72,10 @@ EhcCreateHelpQ ( //
// Create a dummy QH to act as the terminator for periodical schedule
//
- Ep.EpAddr = 2;
- Ep.Type = EHC_INT_TRANSFER_SYNC;
+ Ep.EpAddr = 2;
+ Ep.Type = EHC_INT_TRANSFER_SYNC;
- Qh = EhcCreateQh (Ehc, &Ep);
+ Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -98,7 +98,7 @@ EhcCreateHelpQ ( **/
EFI_STATUS
EhcInitSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
VOID *Buf;
@@ -132,9 +132,9 @@ EhcInitSched ( return EFI_OUT_OF_RESOURCES;
}
- Ehc->PeriodFrame = Buf;
- Ehc->PeriodFrameMap = Map;
- Ehc->High32bitAddr = EHC_HIGH_32BIT (PhyAddr);
+ Ehc->PeriodFrame = Buf;
+ Ehc->PeriodFrameMap = Map;
+ Ehc->High32bitAddr = EHC_HIGH_32BIT (PhyAddr);
//
// Init memory pool management then create the helper
@@ -160,8 +160,8 @@ EhcInitSched ( //
// Initialize the frame list entries then set the registers
//
- Desc = (UINT32 *) Ehc->PeriodFrame;
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (PEI_EHC_QH));
+ Desc = (UINT32 *)Ehc->PeriodFrame;
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (PEI_EHC_QH));
for (Index = 0; Index < EHC_FRAME_LEN; Index++) {
Desc[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
@@ -173,7 +173,7 @@ EhcInitSched ( // Only need to set the AsynListAddr register to
// the reclamation header
//
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (PEI_EHC_QH));
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (PEI_EHC_QH));
EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, EHC_LOW_32BIT (PciAddr));
return EFI_SUCCESS;
}
@@ -186,7 +186,7 @@ EhcInitSched ( **/
VOID
EhcFreeSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
@@ -231,24 +231,24 @@ EhcFreeSched ( **/
VOID
EhcLinkQhToAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
{
- PEI_EHC_QH *Head;
+ PEI_EHC_QH *Head;
//
// Append the queue head after the reclaim header, then
// fix the hardware visiable parts (EHCI R1.0 page 72).
// ReclaimHead is always linked to the EHCI's AsynListAddr.
//
- Head = Ehc->ReclaimHead;
+ Head = Ehc->ReclaimHead;
- Qh->NextQh = Head->NextQh;
- Head->NextQh = Qh;
+ Qh->NextQh = Head->NextQh;
+ Head->NextQh = Qh;
- Qh->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);;
- Head->QhHw.HorizonLink = QH_LINK (Qh, EHC_TYPE_QH, FALSE);
+ Qh->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
+ Head->QhHw.HorizonLink = QH_LINK (Qh, EHC_TYPE_QH, FALSE);
}
/**
@@ -261,11 +261,11 @@ EhcLinkQhToAsync ( **/
VOID
EhcUnlinkQhFromAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
{
- PEI_EHC_QH *Head;
+ PEI_EHC_QH *Head;
ASSERT (Ehc->ReclaimHead->NextQh == Qh);
@@ -274,12 +274,12 @@ EhcUnlinkQhFromAsync ( // visiable part: Only need to loopback the ReclaimHead. The Qh
// is pointing to ReclaimHead (which is staill in the list).
//
- Head = Ehc->ReclaimHead;
+ Head = Ehc->ReclaimHead;
- Head->NextQh = Qh->NextQh;
- Qh->NextQh = NULL;
+ Head->NextQh = Qh->NextQh;
+ Qh->NextQh = NULL;
- Head->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
+ Head->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
//
// Set and wait the door bell to synchronize with the hardware
@@ -302,22 +302,22 @@ EhcUnlinkQhFromAsync ( **/
BOOLEAN
EhcCheckUrbResult (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
{
- EFI_LIST_ENTRY *Entry;
- PEI_EHC_QTD *Qtd;
- QTD_HW *QtdHw;
- UINT8 State;
- BOOLEAN Finished;
+ EFI_LIST_ENTRY *Entry;
+ PEI_EHC_QTD *Qtd;
+ QTD_HW *QtdHw;
+ UINT8 State;
+ BOOLEAN Finished;
ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));
- Finished = TRUE;
- Urb->Completed = 0;
+ Finished = TRUE;
+ Urb->Completed = 0;
- Urb->Result = EFI_USB_NOERROR;
+ Urb->Result = EFI_USB_NOERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
Urb->Result |= EFI_USB_ERR_SYSTEM;
@@ -327,7 +327,7 @@ EhcCheckUrbResult ( BASE_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, PEI_EHC_QTD, QtdList);
QtdHw = &Qtd->QtdHw;
- State = (UINT8) QtdHw->Status;
+ State = (UINT8)QtdHw->Status;
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
//
@@ -352,7 +352,6 @@ EhcCheckUrbResult ( Finished = TRUE;
goto ON_EXIT;
-
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
//
// The QTD is still active, no need to check furthur.
@@ -361,7 +360,6 @@ EhcCheckUrbResult ( Finished = FALSE;
goto ON_EXIT;
-
} else {
//
// This QTD is finished OK or met short packet read. Update the
@@ -372,7 +370,7 @@ EhcCheckUrbResult ( }
if ((QtdHw->TotalBytes != 0) && (QtdHw->Pid == QTD_PID_INPUT)) {
- //EHC_DUMP_QH ((Urb->Qh, "Short packet read", FALSE));
+ // EHC_DUMP_QH ((Urb->Qh, "Short packet read", FALSE));
//
// Short packet read condition. If it isn't a setup transfer,
@@ -381,7 +379,6 @@ EhcCheckUrbResult ( // Status Stage of the setup transfer to get the finial result
//
if (QtdHw->AltNext == QTD_LINK (Ehc->ShortReadStop, FALSE)) {
-
Finished = TRUE;
goto ON_EXIT;
}
@@ -399,7 +396,7 @@ ON_EXIT: // NOTICE: don't move DT update before the loop, otherwise there is
// a race condition that DT is wrong.
//
- Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;
+ Urb->DataToggle = (UINT8)Urb->Qh->QhHw.DataToggle;
return Finished;
}
@@ -418,19 +415,19 @@ ON_EXIT: **/
EFI_STATUS
EhcExecTransfer (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb,
- IN UINTN TimeOut
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb,
+ IN UINTN TimeOut
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINTN Loop;
- BOOLEAN Finished;
- BOOLEAN InfiniteLoop;
-
- Status = EFI_SUCCESS;
- Loop = TimeOut * EHC_1_MILLISECOND;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN Loop;
+ BOOLEAN Finished;
+ BOOLEAN InfiniteLoop;
+
+ Status = EFI_SUCCESS;
+ Loop = TimeOut * EHC_1_MILLISECOND;
Finished = FALSE;
InfiniteLoop = FALSE;
@@ -460,4 +457,3 @@ EhcExecTransfer ( return Status;
}
-
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h index 60f8cb8152..6cba2d3e35 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h @@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
EhcInitSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -33,7 +33,7 @@ EhcInitSched ( **/
VOID
EhcFreeSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -50,8 +50,8 @@ EhcFreeSched ( **/
VOID
EhcLinkQhToAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
;
@@ -65,8 +65,8 @@ EhcLinkQhToAsync ( **/
VOID
EhcUnlinkQhFromAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
;
@@ -84,9 +84,9 @@ EhcUnlinkQhFromAsync ( **/
EFI_STATUS
EhcExecTransfer (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb,
- IN UINTN TimeOut
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb,
+ IN UINTN TimeOut
)
;
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c index df512ed6fa..1ad7f3a56a 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c @@ -27,19 +27,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
PEI_EHC_QTD *
EhcCreateQtd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 *Data,
- IN UINTN DataLen,
- IN UINT8 PktId,
- IN UINT8 Toggle,
- IN UINTN MaxPacket
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 *Data,
+ IN UINTN DataLen,
+ IN UINT8 PktId,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket
)
{
- PEI_EHC_QTD *Qtd;
- QTD_HW *QtdHw;
- UINTN Index;
- UINTN Len;
- UINTN ThisBufLen;
+ PEI_EHC_QTD *Qtd;
+ QTD_HW *QtdHw;
+ UINTN Index;
+ UINTN Len;
+ UINTN ThisBufLen;
ASSERT (Ehc != NULL);
@@ -49,9 +49,9 @@ EhcCreateQtd ( return NULL;
}
- Qtd->Signature = EHC_QTD_SIG;
- Qtd->Data = Data;
- Qtd->DataLen = 0;
+ Qtd->Signature = EHC_QTD_SIG;
+ Qtd->Data = Data;
+ Qtd->DataLen = 0;
InitializeListHead (&Qtd->QtdList);
@@ -77,17 +77,17 @@ EhcCreateQtd ( // compute the offset and clear Reserved fields. This is already
// done in the data point.
//
- QtdHw->Page[Index] = EHC_LOW_32BIT (Data);
- QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (Data);
+ QtdHw->Page[Index] = EHC_LOW_32BIT (Data);
+ QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (Data);
- ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (Data) & QTD_BUF_MASK);
+ ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (Data) & QTD_BUF_MASK);
if (Len + ThisBufLen >= DataLen) {
Len = DataLen;
break;
}
- Len += ThisBufLen;
+ Len += ThisBufLen;
Data += ThisBufLen;
}
@@ -101,7 +101,7 @@ EhcCreateQtd ( Len = Len - Len % MaxPacket;
}
- QtdHw->TotalBytes = (UINT32) Len;
+ QtdHw->TotalBytes = (UINT32)Len;
Qtd->DataLen = Len;
}
@@ -121,8 +121,8 @@ EhcCreateQtd ( **/
VOID
EhcInitIntQh (
- IN USB_ENDPOINT *Ep,
- IN QH_HW *QhHw
+ IN USB_ENDPOINT *Ep,
+ IN QH_HW *QhHw
)
{
//
@@ -134,7 +134,7 @@ EhcInitIntQh ( //
if (Ep->DevSpeed == EFI_USB_SPEED_HIGH) {
QhHw->SMask = QH_MICROFRAME_0;
- return ;
+ return;
}
//
@@ -163,12 +163,12 @@ EhcInitIntQh ( **/
PEI_EHC_QH *
EhcCreateQh (
- IN PEI_USB2_HC_DEV *Ehci,
- IN USB_ENDPOINT *Ep
+ IN PEI_USB2_HC_DEV *Ehci,
+ IN USB_ENDPOINT *Ep
)
{
- PEI_EHC_QH *Qh;
- QH_HW *QhHw;
+ PEI_EHC_QH *Qh;
+ QH_HW *QhHw;
Qh = UsbHcAllocateMem (Ehci, Ehci->MemPool, sizeof (PEI_EHC_QH));
@@ -176,62 +176,63 @@ EhcCreateQh ( return NULL;
}
- Qh->Signature = EHC_QH_SIG;
- Qh->NextQh = NULL;
- Qh->Interval = Ep->PollRate;
+ Qh->Signature = EHC_QH_SIG;
+ Qh->NextQh = NULL;
+ Qh->Interval = Ep->PollRate;
InitializeListHead (&Qh->Qtds);
- QhHw = &Qh->QhHw;
- QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
- QhHw->DeviceAddr = Ep->DevAddr;
- QhHw->Inactive = 0;
- QhHw->EpNum = Ep->EpAddr;
- QhHw->EpSpeed = Ep->DevSpeed;
- QhHw->DtCtrl = 0;
- QhHw->ReclaimHead = 0;
- QhHw->MaxPacketLen = (UINT32) Ep->MaxPacket;
- QhHw->CtrlEp = 0;
- QhHw->NakReload = QH_NAK_RELOAD;
- QhHw->HubAddr = Ep->HubAddr;
- QhHw->PortNum = Ep->HubPort;
- QhHw->Multiplier = 1;
- QhHw->DataToggle = Ep->Toggle;
+ QhHw = &Qh->QhHw;
+ QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
+ QhHw->DeviceAddr = Ep->DevAddr;
+ QhHw->Inactive = 0;
+ QhHw->EpNum = Ep->EpAddr;
+ QhHw->EpSpeed = Ep->DevSpeed;
+ QhHw->DtCtrl = 0;
+ QhHw->ReclaimHead = 0;
+ QhHw->MaxPacketLen = (UINT32)Ep->MaxPacket;
+ QhHw->CtrlEp = 0;
+ QhHw->NakReload = QH_NAK_RELOAD;
+ QhHw->HubAddr = Ep->HubAddr;
+ QhHw->PortNum = Ep->HubPort;
+ QhHw->Multiplier = 1;
+ QhHw->DataToggle = Ep->Toggle;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->Status |= QTD_STAT_DO_SS;
}
switch (Ep->Type) {
- case EHC_CTRL_TRANSFER:
- //
- // Special initialization for the control transfer:
- // 1. Control transfer initialize data toggle from each QTD
- // 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
- //
- QhHw->DtCtrl = 1;
+ case EHC_CTRL_TRANSFER:
+ //
+ // Special initialization for the control transfer:
+ // 1. Control transfer initialize data toggle from each QTD
+ // 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
+ //
+ QhHw->DtCtrl = 1;
- if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
- QhHw->CtrlEp = 1;
- }
- break;
+ if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
+ QhHw->CtrlEp = 1;
+ }
- case EHC_INT_TRANSFER_ASYNC:
- case EHC_INT_TRANSFER_SYNC:
- //
- // Special initialization for the interrupt transfer
- // to set the S-Mask and C-Mask
- //
- QhHw->NakReload = 0;
- EhcInitIntQh (Ep, QhHw);
- break;
+ break;
- case EHC_BULK_TRANSFER:
- if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
- QhHw->Status |= QTD_STAT_DO_PING;
- }
+ case EHC_INT_TRANSFER_ASYNC:
+ case EHC_INT_TRANSFER_SYNC:
+ //
+ // Special initialization for the interrupt transfer
+ // to set the S-Mask and C-Mask
+ //
+ QhHw->NakReload = 0;
+ EhcInitIntQh (Ep, QhHw);
+ break;
+
+ case EHC_BULK_TRANSFER:
+ if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
+ QhHw->Status |= QTD_STAT_DO_PING;
+ }
- break;
+ break;
}
return Qh;
@@ -252,10 +253,10 @@ EhcCreateQh ( **/
UINTN
EhcConvertPollRate (
- IN UINTN Interval
+ IN UINTN Interval
)
{
- UINTN BitCount;
+ UINTN BitCount;
if (Interval == 0) {
return 1;
@@ -283,13 +284,13 @@ EhcConvertPollRate ( **/
VOID
EhcFreeQtds (
- IN PEI_USB2_HC_DEV *Ehc,
- IN EFI_LIST_ENTRY *Qtds
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN EFI_LIST_ENTRY *Qtds
)
{
- EFI_LIST_ENTRY *Entry;
- EFI_LIST_ENTRY *Next;
- PEI_EHC_QTD *Qtd;
+ EFI_LIST_ENTRY *Entry;
+ EFI_LIST_ENTRY *Next;
+ PEI_EHC_QTD *Qtd;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, PEI_EHC_QTD, QtdList);
@@ -308,8 +309,8 @@ EhcFreeQtds ( **/
VOID
EhcFreeUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
{
if (Urb->RequestPhy != NULL) {
@@ -342,20 +343,20 @@ EhcFreeUrb ( **/
EFI_STATUS
EhcCreateQtds (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
{
- USB_ENDPOINT *Ep;
- PEI_EHC_QH *Qh;
- PEI_EHC_QTD *Qtd;
- PEI_EHC_QTD *StatusQtd;
- PEI_EHC_QTD *NextQtd;
- EFI_LIST_ENTRY *Entry;
- UINT32 AlterNext;
- UINT8 Toggle;
- UINTN Len;
- UINT8 Pid;
+ USB_ENDPOINT *Ep;
+ PEI_EHC_QH *Qh;
+ PEI_EHC_QTD *Qtd;
+ PEI_EHC_QTD *StatusQtd;
+ PEI_EHC_QTD *NextQtd;
+ EFI_LIST_ENTRY *Entry;
+ UINT32 AlterNext;
+ UINT8 Toggle;
+ UINTN Len;
+ UINT8 Pid;
ASSERT ((Urb != NULL) && (Urb->Qh != NULL));
@@ -428,7 +429,7 @@ EhcCreateQtds ( while (Len < Urb->DataLen) {
Qtd = EhcCreateQtd (
Ehc,
- (UINT8 *) Urb->DataPhy + Len,
+ (UINT8 *)Urb->DataPhy + Len,
Urb->DataLen - Len,
Pid,
Toggle,
@@ -446,7 +447,7 @@ EhcCreateQtds ( // Switch the Toggle bit if odd number of packets are included in the QTD.
//
if (((Qtd->DataLen + Ep->MaxPacket - 1) / Ep->MaxPacket) % 2) {
- Toggle = (UINT8) (1 - Toggle);
+ Toggle = (UINT8)(1 - Toggle);
}
Len += Qtd->DataLen;
@@ -472,15 +473,15 @@ EhcCreateQtds ( break;
}
- NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, PEI_EHC_QTD, QtdList);
- Qtd->QtdHw.NextQtd = QTD_LINK (NextQtd, FALSE);
+ NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, PEI_EHC_QTD, QtdList);
+ Qtd->QtdHw.NextQtd = QTD_LINK (NextQtd, FALSE);
}
//
// Link the QTDs to the queue head
//
- NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, PEI_EHC_QTD, QtdList);
- Qh->QhHw.NextQtd = QTD_LINK (NextQtd, FALSE);
+ NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, PEI_EHC_QTD, QtdList);
+ Qh->QhHw.NextQtd = QTD_LINK (NextQtd, FALSE);
return EFI_SUCCESS;
ON_ERROR:
@@ -511,63 +512,63 @@ ON_ERROR: **/
PEI_URB *
EhcCreateUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
)
{
- USB_ENDPOINT *Ep;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EDKII_IOMMU_OPERATION MapOp;
- EFI_STATUS Status;
- UINTN Len;
- PEI_URB *Urb;
- VOID *Map;
+ USB_ENDPOINT *Ep;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EDKII_IOMMU_OPERATION MapOp;
+ EFI_STATUS Status;
+ UINTN Len;
+ PEI_URB *Urb;
+ VOID *Map;
Map = NULL;
- Urb = Ehc->Urb;
- Urb->Signature = EHC_URB_SIG;
+ Urb = Ehc->Urb;
+ Urb->Signature = EHC_URB_SIG;
InitializeListHead (&Urb->UrbList);
- Ep = &Urb->Ep;
- Ep->DevAddr = DevAddr;
- Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
- Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
- Ep->DevSpeed = DevSpeed;
- Ep->MaxPacket = MaxPacket;
+ Ep = &Urb->Ep;
+ Ep->DevAddr = DevAddr;
+ Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
+ Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
+ Ep->DevSpeed = DevSpeed;
+ Ep->MaxPacket = MaxPacket;
- Ep->HubAddr = 0;
- Ep->HubPort = 0;
+ Ep->HubAddr = 0;
+ Ep->HubPort = 0;
if (DevSpeed != EFI_USB_SPEED_HIGH) {
ASSERT (Hub != NULL);
- Ep->HubAddr = Hub->TranslatorHubAddress;
- Ep->HubPort = Hub->TranslatorPortNumber;
+ Ep->HubAddr = Hub->TranslatorHubAddress;
+ Ep->HubPort = Hub->TranslatorPortNumber;
}
- Ep->Toggle = Toggle;
- Ep->Type = Type;
- Ep->PollRate = EhcConvertPollRate (Interval);
+ Ep->Toggle = Toggle;
+ Ep->Type = Type;
+ Ep->PollRate = EhcConvertPollRate (Interval);
- Urb->Request = Request;
- Urb->Data = Data;
- Urb->DataLen = DataLen;
- Urb->Callback = Callback;
- Urb->Context = Context;
- Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
+ Urb->Request = Request;
+ Urb->Data = Data;
+ Urb->DataLen = DataLen;
+ Urb->Callback = Callback;
+ Urb->Context = Context;
+ Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
if (Urb->Qh == NULL) {
goto ON_ERROR;
@@ -575,27 +576,27 @@ EhcCreateUrb ( Urb->RequestPhy = NULL;
Urb->RequestMap = NULL;
- Urb->DataPhy = NULL;
- Urb->DataMap = NULL;
+ Urb->DataPhy = NULL;
+ Urb->DataMap = NULL;
//
// Map the request and user data
//
if (Request != NULL) {
- Len = sizeof (EFI_USB_DEVICE_REQUEST);
- MapOp = EdkiiIoMmuOperationBusMasterRead;
- Status = IoMmuMap (Ehc->IoMmu, MapOp, Request, &Len, &PhyAddr, &Map);
+ Len = sizeof (EFI_USB_DEVICE_REQUEST);
+ MapOp = EdkiiIoMmuOperationBusMasterRead;
+ Status = IoMmuMap (Ehc->IoMmu, MapOp, Request, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != sizeof (EFI_USB_DEVICE_REQUEST))) {
goto ON_ERROR;
}
- Urb->RequestPhy = (VOID *) ((UINTN) PhyAddr);
+ Urb->RequestPhy = (VOID *)((UINTN)PhyAddr);
Urb->RequestMap = Map;
}
if (Data != NULL) {
- Len = DataLen;
+ Len = DataLen;
if (Ep->Direction == EfiUsbDataIn) {
MapOp = EdkiiIoMmuOperationBusMasterWrite;
@@ -603,14 +604,14 @@ EhcCreateUrb ( MapOp = EdkiiIoMmuOperationBusMasterRead;
}
- Status = IoMmuMap (Ehc->IoMmu, MapOp, Data, &Len, &PhyAddr, &Map);
+ Status = IoMmuMap (Ehc->IoMmu, MapOp, Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != DataLen)) {
goto ON_ERROR;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
Status = EhcCreateQtds (Ehc, Urb);
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h index 756b663fdb..9b8aa5de62 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h @@ -10,60 +10,60 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_URB_H_
#define _EFI_EHCI_URB_H_
-typedef struct _PEI_EHC_QTD PEI_EHC_QTD;
-typedef struct _PEI_EHC_QH PEI_EHC_QH;
-typedef struct _PEI_URB PEI_URB;
+typedef struct _PEI_EHC_QTD PEI_EHC_QTD;
+typedef struct _PEI_EHC_QH PEI_EHC_QH;
+typedef struct _PEI_URB PEI_URB;
#define EHC_CTRL_TRANSFER 0x01
#define EHC_BULK_TRANSFER 0x02
#define EHC_INT_TRANSFER_SYNC 0x04
#define EHC_INT_TRANSFER_ASYNC 0x08
-#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
-#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
-#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
+#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
+#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// Hardware related bit definitions
//
-#define EHC_TYPE_ITD 0x00
-#define EHC_TYPE_QH 0x02
-#define EHC_TYPE_SITD 0x04
-#define EHC_TYPE_FSTN 0x06
-
-#define QH_NAK_RELOAD 3
-#define QH_HSHBW_MULTI 1
-
-#define QTD_MAX_ERR 3
-#define QTD_PID_OUTPUT 0x00
-#define QTD_PID_INPUT 0x01
-#define QTD_PID_SETUP 0x02
-
-#define QTD_STAT_DO_OUT 0
-#define QTD_STAT_DO_SS 0
-#define QTD_STAT_DO_PING 0x01
-#define QTD_STAT_DO_CS 0x02
-#define QTD_STAT_TRANS_ERR 0x08
-#define QTD_STAT_BABBLE_ERR 0x10
-#define QTD_STAT_BUFF_ERR 0x20
-#define QTD_STAT_HALTED 0x40
-#define QTD_STAT_ACTIVE 0x80
-#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
-
-#define QTD_MAX_BUFFER 4
-#define QTD_BUF_LEN 4096
-#define QTD_BUF_MASK 0x0FFF
-
-#define QH_MICROFRAME_0 0x01
-#define QH_MICROFRAME_1 0x02
-#define QH_MICROFRAME_2 0x04
-#define QH_MICROFRAME_3 0x08
-#define QH_MICROFRAME_4 0x10
-#define QH_MICROFRAME_5 0x20
-#define QH_MICROFRAME_6 0x40
-#define QH_MICROFRAME_7 0x80
-
-#define USB_ERR_SHORT_PACKET 0x200
+#define EHC_TYPE_ITD 0x00
+#define EHC_TYPE_QH 0x02
+#define EHC_TYPE_SITD 0x04
+#define EHC_TYPE_FSTN 0x06
+
+#define QH_NAK_RELOAD 3
+#define QH_HSHBW_MULTI 1
+
+#define QTD_MAX_ERR 3
+#define QTD_PID_OUTPUT 0x00
+#define QTD_PID_INPUT 0x01
+#define QTD_PID_SETUP 0x02
+
+#define QTD_STAT_DO_OUT 0
+#define QTD_STAT_DO_SS 0
+#define QTD_STAT_DO_PING 0x01
+#define QTD_STAT_DO_CS 0x02
+#define QTD_STAT_TRANS_ERR 0x08
+#define QTD_STAT_BABBLE_ERR 0x10
+#define QTD_STAT_BUFF_ERR 0x20
+#define QTD_STAT_HALTED 0x40
+#define QTD_STAT_ACTIVE 0x80
+#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
+
+#define QTD_MAX_BUFFER 4
+#define QTD_BUF_LEN 4096
+#define QTD_BUF_MASK 0x0FFF
+
+#define QH_MICROFRAME_0 0x01
+#define QH_MICROFRAME_1 0x02
+#define QH_MICROFRAME_2 0x04
+#define QH_MICROFRAME_3 0x08
+#define QH_MICROFRAME_4 0x10
+#define QH_MICROFRAME_5 0x20
+#define QH_MICROFRAME_6 0x40
+#define QH_MICROFRAME_7 0x80
+
+#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -72,7 +72,7 @@ typedef struct _PEI_URB PEI_URB; #define QH_LINK(Addr, Type, Term) \
((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
-#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
+#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
//
// The defination of EHCI hardware used data structure for
@@ -82,77 +82,76 @@ typedef struct _PEI_URB PEI_URB; //
#pragma pack(1)
typedef struct {
- UINT32 NextQtd;
- UINT32 AltNext;
-
- UINT32 Status : 8;
- UINT32 Pid : 2;
- UINT32 ErrCnt : 2;
- UINT32 CurPage : 3;
- UINT32 Ioc : 1;
- UINT32 TotalBytes : 15;
- UINT32 DataToggle : 1;
-
- UINT32 Page[5];
- UINT32 PageHigh[5];
+ UINT32 NextQtd;
+ UINT32 AltNext;
+
+ UINT32 Status : 8;
+ UINT32 Pid : 2;
+ UINT32 ErrCnt : 2;
+ UINT32 CurPage : 3;
+ UINT32 Ioc : 1;
+ UINT32 TotalBytes : 15;
+ UINT32 DataToggle : 1;
+
+ UINT32 Page[5];
+ UINT32 PageHigh[5];
} QTD_HW;
typedef struct {
- UINT32 HorizonLink;
+ UINT32 HorizonLink;
//
// Endpoint capabilities/Characteristics DWord 1 and DWord 2
//
- UINT32 DeviceAddr : 7;
- UINT32 Inactive : 1;
- UINT32 EpNum : 4;
- UINT32 EpSpeed : 2;
- UINT32 DtCtrl : 1;
- UINT32 ReclaimHead : 1;
- UINT32 MaxPacketLen : 11;
- UINT32 CtrlEp : 1;
- UINT32 NakReload : 4;
-
- UINT32 SMask : 8;
- UINT32 CMask : 8;
- UINT32 HubAddr : 7;
- UINT32 PortNum : 7;
- UINT32 Multiplier : 2;
+ UINT32 DeviceAddr : 7;
+ UINT32 Inactive : 1;
+ UINT32 EpNum : 4;
+ UINT32 EpSpeed : 2;
+ UINT32 DtCtrl : 1;
+ UINT32 ReclaimHead : 1;
+ UINT32 MaxPacketLen : 11;
+ UINT32 CtrlEp : 1;
+ UINT32 NakReload : 4;
+
+ UINT32 SMask : 8;
+ UINT32 CMask : 8;
+ UINT32 HubAddr : 7;
+ UINT32 PortNum : 7;
+ UINT32 Multiplier : 2;
//
// Transaction execution overlay area
//
- UINT32 CurQtd;
- UINT32 NextQtd;
- UINT32 AltQtd;
-
- UINT32 Status : 8;
- UINT32 Pid : 2;
- UINT32 ErrCnt : 2;
- UINT32 CurPage : 3;
- UINT32 Ioc : 1;
- UINT32 TotalBytes : 15;
- UINT32 DataToggle : 1;
-
- UINT32 Page[5];
- UINT32 PageHigh[5];
+ UINT32 CurQtd;
+ UINT32 NextQtd;
+ UINT32 AltQtd;
+
+ UINT32 Status : 8;
+ UINT32 Pid : 2;
+ UINT32 ErrCnt : 2;
+ UINT32 CurPage : 3;
+ UINT32 Ioc : 1;
+ UINT32 TotalBytes : 15;
+ UINT32 DataToggle : 1;
+
+ UINT32 Page[5];
+ UINT32 PageHigh[5];
} QH_HW;
#pragma pack()
-
//
// Endpoint address and its capabilities
//
typedef struct _USB_ENDPOINT {
- UINT8 DevAddr;
- UINT8 EpAddr; // Endpoint address, no direction encoded in
- EFI_USB_DATA_DIRECTION Direction;
- UINT8 DevSpeed;
- UINTN MaxPacket;
- UINT8 HubAddr;
- UINT8 HubPort;
- UINT8 Toggle; // Data toggle, not used for control transfer
- UINTN Type;
- UINTN PollRate; // Polling interval used by EHCI
+ UINT8 DevAddr;
+ UINT8 EpAddr; // Endpoint address, no direction encoded in
+ EFI_USB_DATA_DIRECTION Direction;
+ UINT8 DevSpeed;
+ UINTN MaxPacket;
+ UINT8 HubAddr;
+ UINT8 HubPort;
+ UINT8 Toggle; // Data toggle, not used for control transfer
+ UINTN Type;
+ UINTN PollRate; // Polling interval used by EHCI
} USB_ENDPOINT;
//
@@ -160,15 +159,13 @@ typedef struct _USB_ENDPOINT { // QTD generated from a URB. Don't add fields before QtdHw.
//
struct _PEI_EHC_QTD {
- QTD_HW QtdHw;
- UINT32 Signature;
- EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point
- UINT8 *Data; // Buffer of the original data
- UINTN DataLen; // Original amount of data in this QTD
+ QTD_HW QtdHw;
+ UINT32 Signature;
+ EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point
+ UINT8 *Data; // Buffer of the original data
+ UINTN DataLen; // Original amount of data in this QTD
};
-
-
//
// Software QH structure. All three different transaction types
// supported by UEFI USB, that is the control/bulk/interrupt
@@ -185,11 +182,11 @@ struct _PEI_EHC_QTD { // as the reclamation header. New transfer is inserted after this QH.
//
struct _PEI_EHC_QH {
- QH_HW QhHw;
- UINT32 Signature;
- PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link
- EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head
- UINTN Interval;
+ QH_HW QhHw;
+ UINT32 Signature;
+ PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link
+ EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head
+ UINTN Interval;
};
//
@@ -197,34 +194,34 @@ struct _PEI_EHC_QH { // usb requests.
//
struct _PEI_URB {
- UINT32 Signature;
- EFI_LIST_ENTRY UrbList;
+ UINT32 Signature;
+ EFI_LIST_ENTRY UrbList;
//
// Transaction information
//
- USB_ENDPOINT Ep;
- EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
- VOID *RequestPhy; // Address of the mapped request
- VOID *RequestMap;
- VOID *Data;
- UINTN DataLen;
- VOID *DataPhy; // Address of the mapped user data
- VOID *DataMap;
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ USB_ENDPOINT Ep;
+ EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
+ VOID *RequestPhy; // Address of the mapped request
+ VOID *RequestMap;
+ VOID *Data;
+ UINTN DataLen;
+ VOID *DataPhy; // Address of the mapped user data
+ VOID *DataMap;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
//
// Schedule data
//
- PEI_EHC_QH *Qh;
+ PEI_EHC_QH *Qh;
//
// Transaction result
//
- UINT32 Result;
- UINTN Completed; // completed data length
- UINT8 DataToggle;
+ UINT32 Result;
+ UINTN Completed; // completed data length
+ UINT8 DataToggle;
};
/**
@@ -243,12 +240,12 @@ struct _PEI_URB { **/
PEI_EHC_QTD *
EhcCreateQtd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 *Data,
- IN UINTN DataLen,
- IN UINT8 PktId,
- IN UINT8 Toggle,
- IN UINTN MaxPacket
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 *Data,
+ IN UINTN DataLen,
+ IN UINT8 PktId,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket
)
;
@@ -263,8 +260,8 @@ EhcCreateQtd ( **/
PEI_EHC_QH *
EhcCreateQh (
- IN PEI_USB2_HC_DEV *Ehci,
- IN USB_ENDPOINT *Ep
+ IN PEI_USB2_HC_DEV *Ehci,
+ IN USB_ENDPOINT *Ep
)
;
@@ -277,8 +274,8 @@ EhcCreateQh ( **/
VOID
EhcFreeUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
;
@@ -305,20 +302,21 @@ EhcFreeUrb ( **/
PEI_URB *
EhcCreateUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
)
;
+
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c index 269b3edb84..4b1fdcec80 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c @@ -22,30 +22,31 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Pages
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Pages
)
{
- USBHC_MEM_BLOCK *Block;
- VOID *BufHost;
- VOID *Mapping;
- EFI_PHYSICAL_ADDRESS MappedAddr;
- EFI_STATUS Status;
- UINTN PageNumber;
- EFI_PHYSICAL_ADDRESS TempPtr;
-
- Mapping = NULL;
- PageNumber = sizeof(USBHC_MEM_BLOCK)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
+ USBHC_MEM_BLOCK *Block;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ EFI_STATUS Status;
+ UINTN PageNumber;
+ EFI_PHYSICAL_ADDRESS TempPtr;
+
+ Mapping = NULL;
+ PageNumber = sizeof (USBHC_MEM_BLOCK)/PAGESIZE +1;
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
- return NULL;
+ return NULL;
}
+
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
//
@@ -54,34 +55,36 @@ UsbHcAllocMemBlock ( //
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block = (USBHC_MEM_BLOCK*)(UINTN)TempPtr;
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
- Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
+ Block = (USBHC_MEM_BLOCK *)(UINTN)TempPtr;
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
PageNumber = (Block->BitsLen)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
+
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
- if (EFI_ERROR (Status)) {
- return NULL;
- }
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
- Block->Bits = (UINT8 *)(UINTN)TempPtr;
+ Block->Bits = (UINT8 *)(UINTN)TempPtr;
Status = IoMmuAllocateBuffer (
Ehc->IoMmu,
Pages,
- (VOID **) &BufHost,
+ (VOID **)&BufHost,
&MappedAddr,
&Mapping
);
if (EFI_ERROR (Status)) {
return NULL;
}
+
ZeroMem (BufHost, Pages*EFI_PAGE_SIZE);
//
@@ -89,16 +92,15 @@ UsbHcAllocMemBlock ( // should be restricted into the same 4G
//
if (Pool->Check4G && (Pool->Which4G != USB_HC_HIGH_32BIT (MappedAddr))) {
- return NULL;
+ return NULL;
}
- Block->BufHost = BufHost;
- Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
- Block->Mapping = Mapping;
- Block->Next = NULL;
+ Block->BufHost = BufHost;
+ Block->Buf = (UINT8 *)((UINTN)MappedAddr);
+ Block->Mapping = Mapping;
+ Block->Next = NULL;
return Block;
-
}
/**
@@ -111,9 +113,9 @@ UsbHcAllocMemBlock ( **/
VOID
UsbHcFreeMemBlock (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -133,22 +135,22 @@ UsbHcFreeMemBlock ( **/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -164,13 +166,12 @@ UsbHcAllocMemFromBlock ( }
NEXT_BIT (Byte, Bit);
-
} else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -181,13 +182,13 @@ UsbHcAllocMemFromBlock ( //
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | (UINT8)USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -205,16 +206,16 @@ UsbHcAllocMemFromBlock ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -228,7 +229,7 @@ UsbHcGetPciAddressForHostMem ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -237,8 +238,8 @@ UsbHcGetPciAddressForHostMem ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -251,8 +252,8 @@ UsbHcGetPciAddressForHostMem ( **/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -271,11 +272,10 @@ UsbHcInsertMemBlockToPool ( **/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
-
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -286,7 +286,6 @@ UsbHcIsMemBlockEmpty ( return TRUE;
}
-
/**
Initialize the memory management pool for the host controller.
@@ -301,29 +300,30 @@ UsbHcIsMemBlockEmpty ( **/
USBHC_MEM_POOL *
UsbHcInitMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN BOOLEAN Check4G,
- IN UINT32 Which4G
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN BOOLEAN Check4G,
+ IN UINT32 Which4G
)
{
- USBHC_MEM_POOL *Pool;
- UINTN PageNumber;
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS TempPtr;
-
- PageNumber = sizeof(USBHC_MEM_POOL)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
+ USBHC_MEM_POOL *Pool;
+ UINTN PageNumber;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS TempPtr;
+
+ PageNumber = sizeof (USBHC_MEM_POOL)/PAGESIZE +1;
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
+
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
- if (EFI_ERROR (Status)) {
- return NULL;
- }
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
- Pool = (USBHC_MEM_POOL *) ((UINTN) TempPtr);
+ Pool = (USBHC_MEM_POOL *)((UINTN)TempPtr);
Pool->Check4G = Check4G;
Pool->Which4G = Which4G;
@@ -348,11 +348,11 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -381,17 +381,17 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -425,7 +425,8 @@ UsbHcAllocateMem ( } else {
Pages = USBHC_MEM_DEFAULT_PAGES;
}
- NewBlock = UsbHcAllocMemBlock (Ehc,Pool, Pages);
+
+ NewBlock = UsbHcAllocMemBlock (Ehc, Pool, Pages);
if (NewBlock == NULL) {
return NULL;
@@ -455,23 +456,23 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -482,8 +483,8 @@ UsbHcFreeMem ( //
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -491,7 +492,7 @@ UsbHcFreeMem ( for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -513,5 +514,5 @@ UsbHcFreeMem ( UsbHcFreeMemBlock (Ehc, Pool, Block);
}
- return ;
+ return;
}
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h index 21b2d7fa9f..7151dbc6e4 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h @@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Uefi.h>
#include <IndustryStandard/Pci22.h>
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -24,13 +24,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
@@ -39,15 +39,15 @@ struct _USBHC_MEM_BLOCK { // data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -66,7 +66,6 @@ typedef struct _USBHC_MEM_POOL { } \
} while (0)
-
/**
Calculate the corresponding pci bus address according to the Mem parameter.
@@ -78,9 +77,9 @@ typedef struct _USBHC_MEM_POOL { **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c b/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c index 436d5971d0..3f5462c257 100644 --- a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c +++ b/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c @@ -26,8 +26,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_STATUS
EFIAPI
AtapiPeimEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
PEI_ATA_CONTROLLER_PPI *AtaControllerPpi;
@@ -40,11 +40,11 @@ AtapiPeimEntry ( }
Status = PeiServicesLocatePpi (
- &gPeiAtaControllerPpiGuid,
- 0,
- NULL,
- (VOID **) &AtaControllerPpi
- );
+ &gPeiAtaControllerPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&AtaControllerPpi
+ );
ASSERT_EFI_ERROR (Status);
AtapiBlkIoDev = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (*AtapiBlkIoDev)));
@@ -60,21 +60,21 @@ AtapiPeimEntry ( //
AtapiEnumerateDevices (AtapiBlkIoDev);
- AtapiBlkIoDev->AtapiBlkIo.GetNumberOfBlockDevices = AtapiGetNumberOfBlockDevices;
- AtapiBlkIoDev->AtapiBlkIo.GetBlockDeviceMediaInfo = AtapiGetBlockDeviceMediaInfo;
- AtapiBlkIoDev->AtapiBlkIo.ReadBlocks = AtapiReadBlocks;
+ AtapiBlkIoDev->AtapiBlkIo.GetNumberOfBlockDevices = AtapiGetNumberOfBlockDevices;
+ AtapiBlkIoDev->AtapiBlkIo.GetBlockDeviceMediaInfo = AtapiGetBlockDeviceMediaInfo;
+ AtapiBlkIoDev->AtapiBlkIo.ReadBlocks = AtapiReadBlocks;
AtapiBlkIoDev->AtapiBlkIo2.Revision = EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION;
AtapiBlkIoDev->AtapiBlkIo2.GetNumberOfBlockDevices = AtapiGetNumberOfBlockDevices2;
AtapiBlkIoDev->AtapiBlkIo2.GetBlockDeviceMediaInfo = AtapiGetBlockDeviceMediaInfo2;
AtapiBlkIoDev->AtapiBlkIo2.ReadBlocks = AtapiReadBlocks2;
- AtapiBlkIoDev->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI;
- AtapiBlkIoDev->PpiDescriptor.Guid = &gEfiPeiVirtualBlockIoPpiGuid;
- AtapiBlkIoDev->PpiDescriptor.Ppi = &AtapiBlkIoDev->AtapiBlkIo;
+ AtapiBlkIoDev->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI;
+ AtapiBlkIoDev->PpiDescriptor.Guid = &gEfiPeiVirtualBlockIoPpiGuid;
+ AtapiBlkIoDev->PpiDescriptor.Ppi = &AtapiBlkIoDev->AtapiBlkIo;
- AtapiBlkIoDev->PpiDescriptor2.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- AtapiBlkIoDev->PpiDescriptor2.Guid = &gEfiPeiVirtualBlockIo2PpiGuid;
- AtapiBlkIoDev->PpiDescriptor2.Ppi = &AtapiBlkIoDev->AtapiBlkIo2;
+ AtapiBlkIoDev->PpiDescriptor2.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+ AtapiBlkIoDev->PpiDescriptor2.Guid = &gEfiPeiVirtualBlockIo2PpiGuid;
+ AtapiBlkIoDev->PpiDescriptor2.Ppi = &AtapiBlkIoDev->AtapiBlkIo2;
DEBUG ((DEBUG_INFO, "Atatpi Device Count is %d\n", AtapiBlkIoDev->DeviceCount));
if (AtapiBlkIoDev->DeviceCount != 0) {
@@ -109,16 +109,16 @@ AtapiPeimEntry ( EFI_STATUS
EFIAPI
AtapiGetNumberOfBlockDevices (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
- OUT UINTN *NumberBlockDevices
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ OUT UINTN *NumberBlockDevices
)
{
ATAPI_BLK_IO_DEV *AtapiBlkIoDev;
AtapiBlkIoDev = NULL;
- AtapiBlkIoDev = PEI_RECOVERY_ATAPI_FROM_BLKIO_THIS (This);
+ AtapiBlkIoDev = PEI_RECOVERY_ATAPI_FROM_BLKIO_THIS (This);
*NumberBlockDevices = AtapiBlkIoDev->DeviceCount;
@@ -156,10 +156,10 @@ AtapiGetNumberOfBlockDevices ( EFI_STATUS
EFIAPI
AtapiGetBlockDeviceMediaInfo (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
- IN UINTN DeviceIndex,
- OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
)
{
UINTN DeviceCount;
@@ -169,13 +169,13 @@ AtapiGetBlockDeviceMediaInfo ( AtapiBlkIoDev = NULL;
- if (This == NULL || MediaInfo == NULL) {
+ if ((This == NULL) || (MediaInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
AtapiBlkIoDev = PEI_RECOVERY_ATAPI_FROM_BLKIO_THIS (This);
- DeviceCount = AtapiBlkIoDev->DeviceCount;
+ DeviceCount = AtapiBlkIoDev->DeviceCount;
//
// DeviceIndex is a value from 1 to NumberBlockDevices.
@@ -214,7 +214,7 @@ AtapiGetBlockDeviceMediaInfo ( //
// Get media info from AtapiBlkIoDev
//
- CopyMem (MediaInfo, &AtapiBlkIoDev->DeviceInfo[Index].MediaInfo, sizeof(EFI_PEI_BLOCK_IO_MEDIA));
+ CopyMem (MediaInfo, &AtapiBlkIoDev->DeviceInfo[Index].MediaInfo, sizeof (EFI_PEI_BLOCK_IO_MEDIA));
return EFI_SUCCESS;
}
@@ -256,15 +256,14 @@ AtapiGetBlockDeviceMediaInfo ( EFI_STATUS
EFIAPI
AtapiReadBlocks (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
- IN UINTN DeviceIndex,
- IN EFI_PEI_LBA StartLBA,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
)
{
-
EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
EFI_STATUS Status;
UINTN NumberOfBlocks;
@@ -288,11 +287,11 @@ AtapiReadBlocks ( }
Status = AtapiGetBlockDeviceMediaInfo (
- PeiServices,
- This,
- DeviceIndex,
- &MediaInfo
- );
+ PeiServices,
+ This,
+ DeviceIndex,
+ &MediaInfo
+ );
if (Status != EFI_SUCCESS) {
return EFI_DEVICE_ERROR;
}
@@ -314,13 +313,13 @@ AtapiReadBlocks ( }
Status = ReadSectors (
- AtapiBlkIoDev,
- AtapiBlkIoDev->DeviceInfo[DeviceIndex - 1].DevicePosition,
- Buffer,
- StartLBA,
- NumberOfBlocks,
- BlockSize
- );
+ AtapiBlkIoDev,
+ AtapiBlkIoDev->DeviceInfo[DeviceIndex - 1].DevicePosition,
+ Buffer,
+ StartLBA,
+ NumberOfBlocks,
+ BlockSize
+ );
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
@@ -350,9 +349,9 @@ AtapiReadBlocks ( EFI_STATUS
EFIAPI
AtapiGetNumberOfBlockDevices2 (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
- OUT UINTN *NumberBlockDevices
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ OUT UINTN *NumberBlockDevices
)
{
EFI_STATUS Status;
@@ -400,19 +399,19 @@ AtapiGetNumberOfBlockDevices2 ( EFI_STATUS
EFIAPI
AtapiGetBlockDeviceMediaInfo2 (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
- IN UINTN DeviceIndex,
- OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
)
{
- ATAPI_BLK_IO_DEV *AtapiBlkIoDev;
- EFI_STATUS Status;
- EFI_PEI_BLOCK_IO_MEDIA Media;
+ ATAPI_BLK_IO_DEV *AtapiBlkIoDev;
+ EFI_STATUS Status;
+ EFI_PEI_BLOCK_IO_MEDIA Media;
AtapiBlkIoDev = NULL;
- if (This == NULL || MediaInfo == NULL) {
+ if ((This == NULL) || (MediaInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -427,10 +426,11 @@ AtapiGetBlockDeviceMediaInfo2 ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Get media info from AtapiBlkIoDev
//
- CopyMem (MediaInfo, &AtapiBlkIoDev->DeviceInfo[DeviceIndex - 1].MediaInfo2, sizeof(EFI_PEI_BLOCK_IO2_MEDIA));
+ CopyMem (MediaInfo, &AtapiBlkIoDev->DeviceInfo[DeviceIndex - 1].MediaInfo2, sizeof (EFI_PEI_BLOCK_IO2_MEDIA));
return EFI_SUCCESS;
}
@@ -472,16 +472,16 @@ AtapiGetBlockDeviceMediaInfo2 ( EFI_STATUS
EFIAPI
AtapiReadBlocks2 (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
- IN UINTN DeviceIndex,
- IN EFI_PEI_LBA StartLBA,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- ATAPI_BLK_IO_DEV *AtapiBlkIoDev;
+ EFI_STATUS Status;
+ ATAPI_BLK_IO_DEV *AtapiBlkIoDev;
AtapiBlkIoDev = NULL;
@@ -503,7 +503,6 @@ AtapiReadBlocks2 ( return Status;
}
-
/**
Enumerate Atapi devices.
@@ -517,19 +516,19 @@ AtapiEnumerateDevices ( IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev
)
{
- UINT8 Index1;
- UINT8 Index2;
- UINTN DevicePosition;
- EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
- EFI_PEI_BLOCK_IO2_MEDIA MediaInfo2;
- EFI_STATUS Status;
- UINTN DeviceCount;
- UINT16 CommandBlockBaseAddr;
- UINT16 ControlBlockBaseAddr;
- UINT32 IdeEnabledNumber;
- IDE_REGS_BASE_ADDR IdeRegsBaseAddr[MAX_IDE_CHANNELS];
-
- DeviceCount = 0;
+ UINT8 Index1;
+ UINT8 Index2;
+ UINTN DevicePosition;
+ EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
+ EFI_PEI_BLOCK_IO2_MEDIA MediaInfo2;
+ EFI_STATUS Status;
+ UINTN DeviceCount;
+ UINT16 CommandBlockBaseAddr;
+ UINT16 ControlBlockBaseAddr;
+ UINT32 IdeEnabledNumber;
+ IDE_REGS_BASE_ADDR IdeRegsBaseAddr[MAX_IDE_CHANNELS];
+
+ DeviceCount = 0;
DevicePosition = 0;
//
@@ -540,10 +539,10 @@ AtapiEnumerateDevices ( // Enable Sata and IDE controller.
//
AtapiBlkIoDev->AtaControllerPpi->EnableAtaChannel (
- (EFI_PEI_SERVICES **) GetPeiServicesTablePointer(),
- AtapiBlkIoDev->AtaControllerPpi,
- PEI_ICH_IDE_PRIMARY | PEI_ICH_IDE_SECONDARY
- );
+ (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (),
+ AtapiBlkIoDev->AtaControllerPpi,
+ PEI_ICH_IDE_PRIMARY | PEI_ICH_IDE_SECONDARY
+ );
//
// Allow SATA Devices to spin-up. This is needed if
@@ -556,28 +555,28 @@ AtapiEnumerateDevices ( // Get four channels (primary or secondary Pata, Sata Channel) Command and Control Regs Base address.
//
IdeEnabledNumber = AtapiBlkIoDev->AtaControllerPpi->GetIdeRegsBaseAddr (
- (EFI_PEI_SERVICES **) GetPeiServicesTablePointer(),
- AtapiBlkIoDev->AtaControllerPpi,
- IdeRegsBaseAddr
- );
+ (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (),
+ AtapiBlkIoDev->AtaControllerPpi,
+ IdeRegsBaseAddr
+ );
//
// Using Command and Control Regs Base Address to fill other registers.
//
- for (Index1 = 0; Index1 < IdeEnabledNumber; Index1 ++) {
- CommandBlockBaseAddr = IdeRegsBaseAddr[Index1].CommandBlockBaseAddr;
+ for (Index1 = 0; Index1 < IdeEnabledNumber; Index1++) {
+ CommandBlockBaseAddr = IdeRegsBaseAddr[Index1].CommandBlockBaseAddr;
AtapiBlkIoDev->IdeIoPortReg[Index1].Data = CommandBlockBaseAddr;
- AtapiBlkIoDev->IdeIoPortReg[Index1].Reg1.Feature = (UINT16) (CommandBlockBaseAddr + 0x1);
- AtapiBlkIoDev->IdeIoPortReg[Index1].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x2);
- AtapiBlkIoDev->IdeIoPortReg[Index1].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x3);
- AtapiBlkIoDev->IdeIoPortReg[Index1].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x4);
- AtapiBlkIoDev->IdeIoPortReg[Index1].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x5);
- AtapiBlkIoDev->IdeIoPortReg[Index1].Head = (UINT16) (CommandBlockBaseAddr + 0x6);
- AtapiBlkIoDev->IdeIoPortReg[Index1].Reg.Command = (UINT16) (CommandBlockBaseAddr + 0x7);
-
- ControlBlockBaseAddr = IdeRegsBaseAddr[Index1].ControlBlockBaseAddr;
+ AtapiBlkIoDev->IdeIoPortReg[Index1].Reg1.Feature = (UINT16)(CommandBlockBaseAddr + 0x1);
+ AtapiBlkIoDev->IdeIoPortReg[Index1].SectorCount = (UINT16)(CommandBlockBaseAddr + 0x2);
+ AtapiBlkIoDev->IdeIoPortReg[Index1].SectorNumber = (UINT16)(CommandBlockBaseAddr + 0x3);
+ AtapiBlkIoDev->IdeIoPortReg[Index1].CylinderLsb = (UINT16)(CommandBlockBaseAddr + 0x4);
+ AtapiBlkIoDev->IdeIoPortReg[Index1].CylinderMsb = (UINT16)(CommandBlockBaseAddr + 0x5);
+ AtapiBlkIoDev->IdeIoPortReg[Index1].Head = (UINT16)(CommandBlockBaseAddr + 0x6);
+ AtapiBlkIoDev->IdeIoPortReg[Index1].Reg.Command = (UINT16)(CommandBlockBaseAddr + 0x7);
+
+ ControlBlockBaseAddr = IdeRegsBaseAddr[Index1].ControlBlockBaseAddr;
AtapiBlkIoDev->IdeIoPortReg[Index1].Alt.DeviceControl = ControlBlockBaseAddr;
- AtapiBlkIoDev->IdeIoPortReg[Index1].DriveAddress = (UINT16) (ControlBlockBaseAddr + 0x1);
+ AtapiBlkIoDev->IdeIoPortReg[Index1].DriveAddress = (UINT16)(ControlBlockBaseAddr + 0x1);
//
// Scan IDE bus for ATAPI devices IDE or Sata device
@@ -596,7 +595,7 @@ AtapiEnumerateDevices ( //
// Retrieve Media Info
//
- Status = DetectMedia (AtapiBlkIoDev, DevicePosition, &MediaInfo, &MediaInfo2);
+ Status = DetectMedia (AtapiBlkIoDev, DevicePosition, &MediaInfo, &MediaInfo2);
CopyMem (&(AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo), &MediaInfo, sizeof (MediaInfo));
CopyMem (&(AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo2), &MediaInfo2, sizeof (MediaInfo2));
@@ -606,11 +605,12 @@ AtapiEnumerateDevices ( DEBUG ((DEBUG_INFO, "Atatpi BlockSize is 0x%x\n", MediaInfo.BlockSize));
if (EFI_ERROR (Status)) {
- AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo.MediaPresent = FALSE;
- AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo.LastBlock = 0;
+ AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo.MediaPresent = FALSE;
+ AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo.LastBlock = 0;
AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo2.MediaPresent = FALSE;
AtapiBlkIoDev->DeviceInfo[DeviceCount].MediaInfo2.LastBlock = 0;
}
+
DeviceCount += 1;
}
}
@@ -633,10 +633,10 @@ AtapiEnumerateDevices ( **/
BOOLEAN
DiscoverAtapiDevice (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
)
{
EFI_STATUS Status;
@@ -644,11 +644,11 @@ DiscoverAtapiDevice ( if (!DetectIDEController (AtapiBlkIoDev, DevicePosition)) {
return FALSE;
}
+
//
// test if it is an ATAPI device (only supported device)
//
if (ATAPIIdentify (AtapiBlkIoDev, DevicePosition) == EFI_SUCCESS) {
-
Status = Inquiry (AtapiBlkIoDev, DevicePosition, MediaInfo, MediaInfo2);
if (!EFI_ERROR (Status)) {
return TRUE;
@@ -673,9 +673,9 @@ DiscoverAtapiDevice ( **/
EFI_STATUS
CheckPowerMode (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN UINT8 AtaCommand
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN UINT8 AtaCommand
)
{
UINT8 Channel;
@@ -690,8 +690,8 @@ CheckPowerMode ( UINT8 ErrorValue;
UINT8 SectorCountValue;
- Channel = (UINT8) (DevicePosition / 2);
- Device = (UINT8) (DevicePosition % 2);
+ Channel = (UINT8)(DevicePosition / 2);
+ Device = (UINT8)(DevicePosition % 2);
ASSERT (Channel < MAX_IDE_CHANNELS);
@@ -704,7 +704,7 @@ CheckPowerMode ( //
// select device
//
- IoWrite8 (HeadRegister, (UINT8) ((Device << 4) | 0xe0));
+ IoWrite8 (HeadRegister, (UINT8)((Device << 4) | 0xe0));
//
// refresh the SectorCount register
@@ -715,14 +715,14 @@ CheckPowerMode ( //
// select device
//
- IoWrite8 (HeadRegister, (UINT8) ((Device << 4) | 0xe0));
+ IoWrite8 (HeadRegister, (UINT8)((Device << 4) | 0xe0));
Status = DRDYReady (AtapiBlkIoDev, &(AtapiBlkIoDev->IdeIoPortReg[Channel]), 100);
//
// select device
//
- IoWrite8 (HeadRegister, (UINT8) ((Device << 4) | 0xe0));
+ IoWrite8 (HeadRegister, (UINT8)((Device << 4) | 0xe0));
//
// send 'check power' commandd via Command Register
//
@@ -766,7 +766,7 @@ CheckPowerMode ( // Write SectorCount 0x55 but return valid state value. Maybe no device
// exists or some slow kind of ATAPI device exists.
//
- IoWrite8 (HeadRegister, (UINT8) ((Device << 4) | 0xe0));
+ IoWrite8 (HeadRegister, (UINT8)((Device << 4) | 0xe0));
//
// write 0x55 and 0xaa to SectorCounter register,
@@ -781,6 +781,7 @@ CheckPowerMode ( if (SectorCountValue != 0x55) {
return EFI_NOT_FOUND;
}
+
//
// Send a "ATAPI TEST UNIT READY" command ... slow but accurate
//
@@ -803,15 +804,15 @@ CheckPowerMode ( **/
BOOLEAN
DetectIDEController (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition
)
{
UINT8 Channel;
EFI_STATUS Status;
UINT8 AtaCommand;
- Channel = (UINT8) (DevicePosition / 2);
+ Channel = (UINT8)(DevicePosition / 2);
ASSERT (Channel < MAX_IDE_CHANNELS);
//
@@ -821,11 +822,12 @@ DetectIDEController ( if (EFI_ERROR (Status)) {
return FALSE;
}
+
//
// Send 'check power' command for IDE device
//
- AtaCommand = 0xE5;
- Status = CheckPowerMode (AtapiBlkIoDev, DevicePosition, AtaCommand);
+ AtaCommand = 0xE5;
+ Status = CheckPowerMode (AtapiBlkIoDev, DevicePosition, AtaCommand);
if ((Status == EFI_ABORTED) || (Status == EFI_SUCCESS)) {
return TRUE;
}
@@ -855,20 +857,20 @@ WaitForBSYClear ( UINT16 StatusRegister;
UINT8 StatusValue;
- StatusValue = 0;
+ StatusValue = 0;
- StatusRegister = IdeIoRegisters->Reg.Status;
+ StatusRegister = IdeIoRegisters->Reg.Status;
- Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
+ Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
do {
StatusValue = IoRead8 (StatusRegister);
if ((StatusValue & ATA_STSREG_BSY) == 0x00) {
break;
}
+
MicroSecondDelay (250);
Delay--;
-
} while (Delay != 0);
if (Delay == 0) {
@@ -901,11 +903,11 @@ DRDYReady ( UINT8 StatusValue;
UINT8 ErrValue;
- StatusValue = 0;
+ StatusValue = 0;
- StatusRegister = IdeIoRegisters->Reg.Status;
+ StatusRegister = IdeIoRegisters->Reg.Status;
- Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
+ Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
do {
StatusValue = IoRead8 (StatusRegister);
//
@@ -915,17 +917,16 @@ DRDYReady ( break;
}
- if ((StatusValue & (ATA_STSREG_ERR | ATA_STSREG_BSY)) == ATA_STSREG_ERR) {
- ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
- if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
- return EFI_ABORTED;
+ if ((StatusValue & (ATA_STSREG_ERR | ATA_STSREG_BSY)) == ATA_STSREG_ERR) {
+ ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
+ if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
+ return EFI_ABORTED;
+ }
}
- }
MicroSecondDelay (250);
Delay--;
-
} while (Delay != 0);
if (Delay == 0) {
@@ -958,13 +959,12 @@ DRQClear ( UINT8 StatusValue;
UINT8 ErrValue;
- StatusValue = 0;
+ StatusValue = 0;
- StatusRegister = IdeIoRegisters->Reg.Status;
+ StatusRegister = IdeIoRegisters->Reg.Status;
- Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
+ Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
do {
-
StatusValue = IoRead8 (StatusRegister);
//
@@ -974,12 +974,12 @@ DRQClear ( break;
}
- if ((StatusValue & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
- ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
- if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
- return EFI_ABORTED;
+ if ((StatusValue & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
+ ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
+ if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
+ return EFI_ABORTED;
+ }
}
- }
MicroSecondDelay (250);
@@ -1016,13 +1016,12 @@ DRQClear2 ( UINT8 AltStatusValue;
UINT8 ErrValue;
- AltStatusValue = 0;
+ AltStatusValue = 0;
AltStatusRegister = IdeIoRegisters->Alt.AltStatus;
- Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
+ Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
do {
-
AltStatusValue = IoRead8 (AltStatusRegister);
//
@@ -1032,12 +1031,12 @@ DRQClear2 ( break;
}
- if ((AltStatusValue & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
- ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
- if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
- return EFI_ABORTED;
+ if ((AltStatusValue & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
+ ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
+ if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
+ return EFI_ABORTED;
+ }
}
- }
MicroSecondDelay (250);
@@ -1075,12 +1074,12 @@ DRQReady ( UINT8 StatusValue;
UINT8 ErrValue;
- StatusValue = 0;
- ErrValue = 0;
+ StatusValue = 0;
+ ErrValue = 0;
- StatusRegister = IdeIoRegisters->Reg.Status;
+ StatusRegister = IdeIoRegisters->Reg.Status;
- Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
+ Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
do {
//
// read Status Register will clear interrupt
@@ -1095,12 +1094,12 @@ DRQReady ( }
if ((StatusValue & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
-
ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
return EFI_ABORTED;
}
}
+
MicroSecondDelay (250);
Delay--;
@@ -1137,13 +1136,12 @@ DRQReady2 ( UINT8 AltStatusValue;
UINT8 ErrValue;
- AltStatusValue = 0;
+ AltStatusValue = 0;
AltStatusRegister = IdeIoRegisters->Alt.AltStatus;
- Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
+ Delay = ((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 250) + 1;
do {
-
AltStatusValue = IoRead8 (AltStatusRegister);
//
@@ -1154,12 +1152,12 @@ DRQReady2 ( }
if ((AltStatusValue & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
-
ErrValue = IoRead8 (IdeIoRegisters->Reg1.Error);
if ((ErrValue & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
return EFI_ABORTED;
}
}
+
MicroSecondDelay (250);
Delay--;
@@ -1184,21 +1182,19 @@ DRQReady2 ( **/
EFI_STATUS
CheckErrorStatus (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINT16 StatusReg
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINT16 StatusReg
)
{
- UINT8 StatusValue;
+ UINT8 StatusValue;
StatusValue = IoRead8 (StatusReg);
if ((StatusValue & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {
-
return EFI_SUCCESS;
}
return EFI_DEVICE_ERROR;
-
}
/**
@@ -1213,8 +1209,8 @@ CheckErrorStatus ( **/
EFI_STATUS
ATAPIIdentify (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition
)
{
ATAPI_IDENTIFY_DATA AtapiIdentifyData;
@@ -1229,19 +1225,19 @@ ATAPIIdentify ( UINT16 CylinderLsbReg;
UINT16 CylinderMsbReg;
- UINT32 WordCount;
- UINT32 Increment;
- UINT32 Index;
- UINT32 ByteCount;
- UINT16 *Buffer16;
+ UINT32 WordCount;
+ UINT32 Increment;
+ UINT32 Index;
+ UINT32 ByteCount;
+ UINT16 *Buffer16;
- EFI_STATUS Status;
+ EFI_STATUS Status;
- ByteCount = sizeof (AtapiIdentifyData);
- Buffer16 = (UINT16 *) &AtapiIdentifyData;
+ ByteCount = sizeof (AtapiIdentifyData);
+ Buffer16 = (UINT16 *)&AtapiIdentifyData;
- Channel = (UINT8) (DevicePosition / 2);
- Device = (UINT8) (DevicePosition % 2);
+ Channel = (UINT8)(DevicePosition / 2);
+ Device = (UINT8)(DevicePosition % 2);
ASSERT (Channel < MAX_IDE_CHANNELS);
@@ -1261,9 +1257,11 @@ ATAPIIdentify ( AtapiBlkIoDev,
&(AtapiBlkIoDev->IdeIoPortReg[Channel]),
ATATIMEOUT
- ) != EFI_SUCCESS) {
+ ) != EFI_SUCCESS)
+ {
return EFI_DEVICE_ERROR;
}
+
//
// select device via Head/Device register.
// Before write Head/Device register, BSY and DRQ must be 0.
@@ -1271,11 +1269,12 @@ ATAPIIdentify ( if (DRQClear2 (AtapiBlkIoDev, &(AtapiBlkIoDev->IdeIoPortReg[Channel]), ATATIMEOUT) != EFI_SUCCESS) {
return EFI_DEVICE_ERROR;
}
+
//
// e0:1110,0000-- bit7 and bit5 are reserved bits.
// bit6 set means LBA mode
//
- IoWrite8 (HeadReg, (UINT8) ((Device << 4) | 0xe0));
+ IoWrite8 (HeadReg, (UINT8)((Device << 4) | 0xe0));
//
// set all the command parameters
@@ -1285,8 +1284,8 @@ ATAPIIdentify ( AtapiBlkIoDev,
&(AtapiBlkIoDev->IdeIoPortReg[Channel]),
ATATIMEOUT
- ) != EFI_SUCCESS) {
-
+ ) != EFI_SUCCESS)
+ {
return EFI_DEVICE_ERROR;
}
@@ -1330,15 +1329,16 @@ ATAPIIdentify ( }
if (CheckErrorStatus (AtapiBlkIoDev, StatusReg) != EFI_SUCCESS) {
-
return EFI_DEVICE_ERROR;
}
+
//
// Get the byte count for one series of read
//
if ((WordCount + Increment) > ByteCount / 2) {
Increment = ByteCount / 2 - WordCount;
}
+
//
// perform a series of read without check DRQ ready
//
@@ -1347,8 +1347,8 @@ ATAPIIdentify ( }
WordCount += Increment;
-
}
+
//
// while
//
@@ -1356,12 +1356,12 @@ ATAPIIdentify ( AtapiBlkIoDev,
&(AtapiBlkIoDev->IdeIoPortReg[Channel]),
ATATIMEOUT
- ) != EFI_SUCCESS) {
+ ) != EFI_SUCCESS)
+ {
return CheckErrorStatus (AtapiBlkIoDev, StatusReg);
}
return EFI_SUCCESS;
-
}
/**
@@ -1377,8 +1377,8 @@ ATAPIIdentify ( **/
EFI_STATUS
TestUnitReady (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition
)
{
ATAPI_PACKET_COMMAND Packet;
@@ -1442,26 +1442,26 @@ AtapiPacketCommandIn ( //
// required transfer data in word unit.
//
- UINT32 RequiredWordCount;
+ UINT32 RequiredWordCount;
//
// actual transfer data in word unit.
//
- UINT32 ActualWordCount;
+ UINT32 ActualWordCount;
- Channel = (UINT8) (DevicePosition / 2);
- Device = (UINT8) (DevicePosition % 2);
+ Channel = (UINT8)(DevicePosition / 2);
+ Device = (UINT8)(DevicePosition % 2);
ASSERT (Channel < MAX_IDE_CHANNELS);
- StatusReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg.Status;
- HeadReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Head;
- CommandReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg.Command;
- FeatureReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg1.Feature;
- CylinderLsbReg = AtapiBlkIoDev->IdeIoPortReg[Channel].CylinderLsb;
- CylinderMsbReg = AtapiBlkIoDev->IdeIoPortReg[Channel].CylinderMsb;
- DeviceControlReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Alt.DeviceControl;
- DataReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Data;
+ StatusReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg.Status;
+ HeadReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Head;
+ CommandReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg.Command;
+ FeatureReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg1.Feature;
+ CylinderLsbReg = AtapiBlkIoDev->IdeIoPortReg[Channel].CylinderLsb;
+ CylinderMsbReg = AtapiBlkIoDev->IdeIoPortReg[Channel].CylinderMsb;
+ DeviceControlReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Alt.DeviceControl;
+ DataReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Data;
//
// Set all the command parameters by fill related registers.
@@ -1471,14 +1471,16 @@ AtapiPacketCommandIn ( AtapiBlkIoDev,
&(AtapiBlkIoDev->IdeIoPortReg[Channel]),
ATATIMEOUT
- ) != EFI_SUCCESS) {
+ ) != EFI_SUCCESS)
+ {
return EFI_DEVICE_ERROR;
}
+
//
// Select device via Device/Head Register.
// DEFAULT_CMD: 0xa0 (1010,0000)
//
- IoWrite8 (HeadReg, (UINT8) ((Device << 4) | ATA_DEFAULT_CMD));
+ IoWrite8 (HeadReg, (UINT8)((Device << 4) | ATA_DEFAULT_CMD));
//
// No OVL; No DMA
@@ -1489,8 +1491,8 @@ AtapiPacketCommandIn ( // set the transfersize to MAX_ATAPI_BYTE_COUNT to let the device
// determine how many data should be transfered.
//
- IoWrite8 (CylinderLsbReg, (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff));
- IoWrite8 (CylinderMsbReg, (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8));
+ IoWrite8 (CylinderLsbReg, (UINT8)(ATAPI_MAX_BYTE_COUNT & 0x00ff));
+ IoWrite8 (CylinderMsbReg, (UINT8)(ATAPI_MAX_BYTE_COUNT >> 8));
//
// DEFAULT_CTL:0x0a (0000,1010)
@@ -1508,6 +1510,7 @@ AtapiPacketCommandIn ( if (Status != EFI_SUCCESS) {
return Status;
}
+
//
// Send out command packet
//
@@ -1527,9 +1530,10 @@ AtapiPacketCommandIn ( return EFI_DEVICE_ERROR;
}
- if (Buffer == NULL || ByteCount == 0) {
+ if ((Buffer == NULL) || (ByteCount == 0)) {
return EFI_SUCCESS;
}
+
//
// call PioReadWriteData() function to get
// requested transfer data form device.
@@ -1541,7 +1545,7 @@ AtapiPacketCommandIn ( //
ActualWordCount = 0;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
while ((Status == EFI_SUCCESS) && (ActualWordCount < RequiredWordCount)) {
//
// before each data transfer stream, the host should poll DRQ bit ready,
@@ -1551,9 +1555,11 @@ AtapiPacketCommandIn ( AtapiBlkIoDev,
&(AtapiBlkIoDev->IdeIoPortReg[Channel]),
TimeoutInMilliSeconds
- ) != EFI_SUCCESS) {
+ ) != EFI_SUCCESS)
+ {
return CheckErrorStatus (AtapiBlkIoDev, StatusReg);
}
+
//
// read Status Register will clear interrupt
//
@@ -1562,30 +1568,28 @@ AtapiPacketCommandIn ( //
// get current data transfer size from Cylinder Registers.
//
- WordCount = IoRead8 (CylinderMsbReg) << 8;
- WordCount = WordCount | IoRead8 (CylinderLsbReg);
- WordCount = WordCount & 0xffff;
+ WordCount = IoRead8 (CylinderMsbReg) << 8;
+ WordCount = WordCount | IoRead8 (CylinderLsbReg);
+ WordCount = WordCount & 0xffff;
WordCount /= 2;
//
// perform a series data In/Out.
//
for (Index = 0; (Index < WordCount) && (ActualWordCount < RequiredWordCount); Index++, ActualWordCount++) {
-
*PtrBuffer = IoRead16 (DataReg);
PtrBuffer++;
-
}
- if (((ATAPI_REQUEST_SENSE_CMD *) Packet)->opcode == ATA_CMD_REQUEST_SENSE && ActualWordCount >= 4) {
+ if ((((ATAPI_REQUEST_SENSE_CMD *)Packet)->opcode == ATA_CMD_REQUEST_SENSE) && (ActualWordCount >= 4)) {
RequiredWordCount = MIN (
RequiredWordCount,
- (UINT32) (4 + (((ATAPI_REQUEST_SENSE_DATA *) Buffer)->addnl_sense_length / 2))
+ (UINT32)(4 + (((ATAPI_REQUEST_SENSE_DATA *)Buffer)->addnl_sense_length / 2))
);
}
-
}
+
//
// After data transfer is completed, normally, DRQ bit should clear.
//
@@ -1593,6 +1597,7 @@ AtapiPacketCommandIn ( if (Status != EFI_SUCCESS) {
return EFI_DEVICE_ERROR;
}
+
//
// read status register to check whether error happens.
//
@@ -1616,15 +1621,15 @@ AtapiPacketCommandIn ( **/
EFI_STATUS
Inquiry (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
)
{
- ATAPI_PACKET_COMMAND Packet;
- EFI_STATUS Status;
- ATAPI_INQUIRY_DATA Idata;
+ ATAPI_PACKET_COMMAND Packet;
+ EFI_STATUS Status;
+ ATAPI_INQUIRY_DATA Idata;
//
// prepare command packet for the ATAPI Inquiry Packet Command.
@@ -1632,64 +1637,65 @@ Inquiry ( ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
ZeroMem (&Idata, sizeof (ATAPI_INQUIRY_DATA));
- Packet.Inquiry.opcode = ATA_CMD_INQUIRY;
- Packet.Inquiry.page_code = 0;
- Packet.Inquiry.allocation_length = (UINT8) sizeof (ATAPI_INQUIRY_DATA);
+ Packet.Inquiry.opcode = ATA_CMD_INQUIRY;
+ Packet.Inquiry.page_code = 0;
+ Packet.Inquiry.allocation_length = (UINT8)sizeof (ATAPI_INQUIRY_DATA);
//
// Send command packet and get requested Inquiry data.
//
Status = AtapiPacketCommandIn (
- AtapiBlkIoDev,
- DevicePosition,
- &Packet,
- (UINT16 *) (&Idata),
- sizeof (ATAPI_INQUIRY_DATA),
- ATAPITIMEOUT
- //50
- );
+ AtapiBlkIoDev,
+ DevicePosition,
+ &Packet,
+ (UINT16 *)(&Idata),
+ sizeof (ATAPI_INQUIRY_DATA),
+ ATAPITIMEOUT
+ // 50
+ );
if (Status != EFI_SUCCESS) {
return EFI_DEVICE_ERROR;
}
+
//
// Identify device type via INQUIRY data.
//
switch (Idata.peripheral_type & 0x1f) {
- case 0x00:
- //
- // Magnetic Disk
- //
- MediaInfo->DeviceType = IdeLS120;
- MediaInfo->MediaPresent = FALSE;
- MediaInfo->LastBlock = 0;
- MediaInfo->BlockSize = 0x200;
- MediaInfo2->InterfaceType = MSG_ATAPI_DP;
- MediaInfo2->RemovableMedia = TRUE;
- MediaInfo2->MediaPresent = FALSE;
- MediaInfo2->ReadOnly = FALSE;
- MediaInfo2->BlockSize = 0x200;
- MediaInfo2->LastBlock = 0;
- break;
-
- case 0x05:
- //
- // CD-ROM
- //
- MediaInfo->DeviceType = IdeCDROM;
- MediaInfo->MediaPresent = FALSE;
- MediaInfo->LastBlock = 0;
- MediaInfo->BlockSize = 0x800;
- MediaInfo2->InterfaceType = MSG_ATAPI_DP;
- MediaInfo2->RemovableMedia = TRUE;
- MediaInfo2->MediaPresent = FALSE;
- MediaInfo2->ReadOnly = TRUE;
- MediaInfo2->BlockSize = 0x200;
- MediaInfo2->LastBlock = 0;
- break;
-
- default:
- return EFI_UNSUPPORTED;
+ case 0x00:
+ //
+ // Magnetic Disk
+ //
+ MediaInfo->DeviceType = IdeLS120;
+ MediaInfo->MediaPresent = FALSE;
+ MediaInfo->LastBlock = 0;
+ MediaInfo->BlockSize = 0x200;
+ MediaInfo2->InterfaceType = MSG_ATAPI_DP;
+ MediaInfo2->RemovableMedia = TRUE;
+ MediaInfo2->MediaPresent = FALSE;
+ MediaInfo2->ReadOnly = FALSE;
+ MediaInfo2->BlockSize = 0x200;
+ MediaInfo2->LastBlock = 0;
+ break;
+
+ case 0x05:
+ //
+ // CD-ROM
+ //
+ MediaInfo->DeviceType = IdeCDROM;
+ MediaInfo->MediaPresent = FALSE;
+ MediaInfo->LastBlock = 0;
+ MediaInfo->BlockSize = 0x800;
+ MediaInfo2->InterfaceType = MSG_ATAPI_DP;
+ MediaInfo2->RemovableMedia = TRUE;
+ MediaInfo2->MediaPresent = FALSE;
+ MediaInfo2->ReadOnly = TRUE;
+ MediaInfo2->BlockSize = 0x200;
+ MediaInfo2->LastBlock = 0;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
@@ -1712,13 +1718,12 @@ Inquiry ( **/
EFI_STATUS
DetectMedia (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
)
{
-
UINTN Index;
UINTN RetryNum;
UINTN MaxRetryNum;
@@ -1738,7 +1743,6 @@ DetectMedia ( // the device will produce corresponding Sense data.
//
for (Index = 0; Index < 2; Index++) {
-
Status = TestUnitReady (AtapiBlkIoDev, DevicePosition);
if (Status != EFI_SUCCESS) {
Status = ResetDevice (AtapiBlkIoDev, DevicePosition, FALSE);
@@ -1746,24 +1750,23 @@ DetectMedia ( if (Status != EFI_SUCCESS) {
ResetDevice (AtapiBlkIoDev, DevicePosition, TRUE);
}
-
} else {
break;
}
}
- SenseCounts = MAX_SENSE_KEY_COUNT;
- Status = EFI_SUCCESS;
- NeedReadCapacity = TRUE;
+ SenseCounts = MAX_SENSE_KEY_COUNT;
+ Status = EFI_SUCCESS;
+ NeedReadCapacity = TRUE;
for (Index = 0; Index < 5; Index++) {
SenseCounts = MAX_SENSE_KEY_COUNT;
- Status = RequestSense (
- AtapiBlkIoDev,
- DevicePosition,
- SenseBuffers,
- &SenseCounts
- );
+ Status = RequestSense (
+ AtapiBlkIoDev,
+ DevicePosition,
+ SenseBuffers,
+ &SenseCounts
+ );
DEBUG ((DEBUG_INFO, "Atapi Request Sense Count is %d\n", SenseCounts));
if (IsDeviceStateUnclear (SenseBuffers, SenseCounts) || IsNoMedia (SenseBuffers, SenseCounts)) {
//
@@ -1776,12 +1779,10 @@ DetectMedia ( }
if (Status == EFI_SUCCESS) {
-
if (IsNoMedia (SenseBuffers, SenseCounts)) {
-
- NeedReadCapacity = FALSE;
- MediaInfo->MediaPresent = FALSE;
- MediaInfo->LastBlock = 0;
+ NeedReadCapacity = FALSE;
+ MediaInfo->MediaPresent = FALSE;
+ MediaInfo->LastBlock = 0;
MediaInfo2->MediaPresent = FALSE;
MediaInfo2->LastBlock = 0;
}
@@ -1801,19 +1802,16 @@ DetectMedia ( // initial retry once
//
for (Index = 0; (Index < RetryNum) && (Index < MaxRetryNum); Index++) {
-
Status = ReadCapacity (AtapiBlkIoDev, DevicePosition, MediaInfo, MediaInfo2);
MicroSecondDelay (200000);
SenseCounts = MAX_SENSE_KEY_COUNT;
if (Status != EFI_SUCCESS) {
-
Status = RequestSense (AtapiBlkIoDev, DevicePosition, SenseBuffers, &SenseCounts);
//
// If Request Sense data failed, reset the device and retry.
//
if (Status != EFI_SUCCESS) {
-
Status = ResetDevice (AtapiBlkIoDev, DevicePosition, FALSE);
//
// if ATAPI soft reset fail,
@@ -1829,13 +1827,13 @@ DetectMedia ( //
continue;
}
+
//
// No Media
//
if (IsNoMedia (SenseBuffers, SenseCounts)) {
-
- MediaInfo->MediaPresent = FALSE;
- MediaInfo->LastBlock = 0;
+ MediaInfo->MediaPresent = FALSE;
+ MediaInfo->LastBlock = 0;
MediaInfo2->MediaPresent = FALSE;
MediaInfo2->LastBlock = 0;
break;
@@ -1857,15 +1855,13 @@ DetectMedia ( return EFI_DEVICE_ERROR;
}
}
+
//
// if read capacity fail not for above reasons, retry once more
//
RetryNum++;
-
}
-
}
-
}
return EFI_SUCCESS;
@@ -1898,18 +1894,17 @@ ResetDevice ( UINT8 Channel;
UINT8 Device;
- Channel = (UINT8) (DevicePosition / 2);
- Device = (UINT8) (DevicePosition % 2);
+ Channel = (UINT8)(DevicePosition / 2);
+ Device = (UINT8)(DevicePosition % 2);
ASSERT (Channel < MAX_IDE_CHANNELS);
- DeviceControlReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Alt.DeviceControl;
- CommandReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg.Command;
- HeadReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Head;
+ DeviceControlReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Alt.DeviceControl;
+ CommandReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Reg.Command;
+ HeadReg = AtapiBlkIoDev->IdeIoPortReg[Channel].Head;
if (Extensive) {
-
- DevControl = 0;
+ DevControl = 0;
DevControl |= ATA_CTLREG_SRST;
//
// set SRST bit to initiate soft reset
@@ -1940,13 +1935,12 @@ ResetDevice ( if (WaitForBSYClear (AtapiBlkIoDev, &(AtapiBlkIoDev->IdeIoPortReg[Channel]), 31000) == EFI_TIMEOUT) {
return EFI_DEVICE_ERROR;
}
-
} else {
//
// for ATAPI device, no need to wait DRDY ready after device selecting.
// bit7 and bit5 are both set to 1 for backward compatibility
//
- DeviceSelect = (UINT8) (((BIT7 | BIT5) | (Device << 4)));
+ DeviceSelect = (UINT8)(((BIT7 | BIT5) | (Device << 4)));
IoWrite8 (HeadReg, DeviceSelect);
Command = ATA_CMD_SOFT_RESET;
@@ -1959,6 +1953,7 @@ ResetDevice ( if (WaitForBSYClear (AtapiBlkIoDev, &(AtapiBlkIoDev->IdeIoPortReg[Channel]), 31000) != EFI_SUCCESS) {
return EFI_DEVICE_ERROR;
}
+
//
// stall 5 seconds to make the device status stable
//
@@ -1966,7 +1961,6 @@ ResetDevice ( }
return EFI_SUCCESS;
-
}
/**
@@ -1983,17 +1977,17 @@ ResetDevice ( **/
EFI_STATUS
RequestSense (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN ATAPI_REQUEST_SENSE_DATA *SenseBuffers,
- IN OUT UINT8 *SenseCounts
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN ATAPI_REQUEST_SENSE_DATA *SenseBuffers,
+ IN OUT UINT8 *SenseCounts
)
{
- EFI_STATUS Status;
- ATAPI_REQUEST_SENSE_DATA *Sense;
- UINT16 *Ptr;
- BOOLEAN SenseReq;
- ATAPI_PACKET_COMMAND Packet;
+ EFI_STATUS Status;
+ ATAPI_REQUEST_SENSE_DATA *Sense;
+ UINT16 *Ptr;
+ BOOLEAN SenseReq;
+ ATAPI_PACKET_COMMAND Packet;
ZeroMem (SenseBuffers, sizeof (ATAPI_REQUEST_SENSE_DATA) * (*SenseCounts));
//
@@ -2001,9 +1995,9 @@ RequestSense ( //
ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
Packet.RequestSence.opcode = ATA_CMD_REQUEST_SENSE;
- Packet.RequestSence.allocation_length = (UINT8) sizeof (ATAPI_REQUEST_SENSE_DATA);
+ Packet.RequestSence.allocation_length = (UINT8)sizeof (ATAPI_REQUEST_SENSE_DATA);
- Ptr = (UINT16 *) SenseBuffers;
+ Ptr = (UINT16 *)SenseBuffers;
//
// initialize pointer
//
@@ -2012,20 +2006,19 @@ RequestSense ( // request sense data from device continiously until no sense data exists in the device.
//
for (SenseReq = TRUE; SenseReq;) {
-
- Sense = (ATAPI_REQUEST_SENSE_DATA *) Ptr;
+ Sense = (ATAPI_REQUEST_SENSE_DATA *)Ptr;
//
// send out Request Sense Packet Command and get one Sense data form device
//
Status = AtapiPacketCommandIn (
- AtapiBlkIoDev,
- DevicePosition,
- &Packet,
- Ptr,
- sizeof (ATAPI_REQUEST_SENSE_DATA),
- ATAPITIMEOUT
- );
+ AtapiBlkIoDev,
+ DevicePosition,
+ &Packet,
+ Ptr,
+ sizeof (ATAPI_REQUEST_SENSE_DATA),
+ ATAPITIMEOUT
+ );
//
// failed to get Sense data
//
@@ -2042,6 +2035,7 @@ RequestSense ( if (*SenseCounts > MAX_SENSE_KEY_COUNT) {
return EFI_SUCCESS;
}
+
//
// We limit MAX sense data count to 20 in order to avoid dead loop. Some
// incompatible ATAPI devices don't retrive NO_SENSE when there is no media.
@@ -2049,7 +2043,6 @@ RequestSense ( // supposed to be large enough for any ATAPI device.
//
if ((Sense->sense_key != ATA_SK_NO_SENSE) && ((*SenseCounts) < 20)) {
-
Ptr += sizeof (ATAPI_REQUEST_SENSE_DATA) / 2;
//
// Ptr is word based pointer
@@ -2081,65 +2074,61 @@ RequestSense ( **/
EFI_STATUS
ReadCapacity (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
)
{
- EFI_STATUS Status;
- ATAPI_PACKET_COMMAND Packet;
+ EFI_STATUS Status;
+ ATAPI_PACKET_COMMAND Packet;
//
// used for capacity data returned from ATAPI device
//
- ATAPI_READ_CAPACITY_DATA Data;
- ATAPI_READ_FORMAT_CAPACITY_DATA FormatData;
+ ATAPI_READ_CAPACITY_DATA Data;
+ ATAPI_READ_FORMAT_CAPACITY_DATA FormatData;
ZeroMem (&Data, sizeof (Data));
ZeroMem (&FormatData, sizeof (FormatData));
if (MediaInfo->DeviceType == IdeCDROM) {
-
ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
Packet.Inquiry.opcode = ATA_CMD_READ_CAPACITY;
- Status = AtapiPacketCommandIn (
- AtapiBlkIoDev,
- DevicePosition,
- &Packet,
- (UINT16 *) (&Data),
- sizeof (ATAPI_READ_CAPACITY_DATA),
- ATAPITIMEOUT
- );
-
+ Status = AtapiPacketCommandIn (
+ AtapiBlkIoDev,
+ DevicePosition,
+ &Packet,
+ (UINT16 *)(&Data),
+ sizeof (ATAPI_READ_CAPACITY_DATA),
+ ATAPITIMEOUT
+ );
} else {
//
// DeviceType == IdeLS120
//
ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
- Packet.ReadFormatCapacity.opcode = ATA_CMD_READ_FORMAT_CAPACITY;
- Packet.ReadFormatCapacity.allocation_length_lo = 12;
- Status = AtapiPacketCommandIn (
- AtapiBlkIoDev,
- DevicePosition,
- &Packet,
- (UINT16 *) (&FormatData),
- sizeof (ATAPI_READ_FORMAT_CAPACITY_DATA),
- ATAPITIMEOUT*10
- );
+ Packet.ReadFormatCapacity.opcode = ATA_CMD_READ_FORMAT_CAPACITY;
+ Packet.ReadFormatCapacity.allocation_length_lo = 12;
+ Status = AtapiPacketCommandIn (
+ AtapiBlkIoDev,
+ DevicePosition,
+ &Packet,
+ (UINT16 *)(&FormatData),
+ sizeof (ATAPI_READ_FORMAT_CAPACITY_DATA),
+ ATAPITIMEOUT*10
+ );
}
if (Status == EFI_SUCCESS) {
-
if (MediaInfo->DeviceType == IdeCDROM) {
-
- MediaInfo->LastBlock = ((UINT32) Data.LastLba3 << 24) | (Data.LastLba2 << 16) | (Data.LastLba1 << 8) | Data.LastLba0;
+ MediaInfo->LastBlock = ((UINT32)Data.LastLba3 << 24) | (Data.LastLba2 << 16) | (Data.LastLba1 << 8) | Data.LastLba0;
MediaInfo->MediaPresent = TRUE;
//
// Because the user data portion in the sector of the Data CD supported
// is always 800h
//
- MediaInfo->BlockSize = 0x800;
+ MediaInfo->BlockSize = 0x800;
MediaInfo2->LastBlock = MediaInfo->LastBlock;
MediaInfo2->MediaPresent = MediaInfo->MediaPresent;
@@ -2147,32 +2136,29 @@ ReadCapacity ( }
if (MediaInfo->DeviceType == IdeLS120) {
-
if (FormatData.DesCode == 3) {
- MediaInfo->MediaPresent = FALSE;
- MediaInfo->LastBlock = 0;
+ MediaInfo->MediaPresent = FALSE;
+ MediaInfo->LastBlock = 0;
MediaInfo2->MediaPresent = FALSE;
MediaInfo2->LastBlock = 0;
} else {
- MediaInfo->LastBlock = ((UINT32) FormatData.LastLba3 << 24) |
- (FormatData.LastLba2 << 16) |
- (FormatData.LastLba1 << 8) |
- FormatData.LastLba0;
+ MediaInfo->LastBlock = ((UINT32)FormatData.LastLba3 << 24) |
+ (FormatData.LastLba2 << 16) |
+ (FormatData.LastLba1 << 8) |
+ FormatData.LastLba0;
MediaInfo->LastBlock--;
MediaInfo->MediaPresent = TRUE;
- MediaInfo->BlockSize = 0x200;
+ MediaInfo->BlockSize = 0x200;
MediaInfo2->LastBlock = MediaInfo->LastBlock;
MediaInfo2->MediaPresent = MediaInfo->MediaPresent;
MediaInfo2->BlockSize = (UINT32)MediaInfo->BlockSize;
-
}
}
return EFI_SUCCESS;
-
} else {
return EFI_DEVICE_ERROR;
}
@@ -2194,15 +2180,14 @@ ReadCapacity ( **/
EFI_STATUS
ReadSectors (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN VOID *Buffer,
- IN EFI_PEI_LBA StartLba,
- IN UINTN NumberOfBlocks,
- IN UINTN BlockSize
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN VOID *Buffer,
+ IN EFI_PEI_LBA StartLba,
+ IN UINTN NumberOfBlocks,
+ IN UINTN BlockSize
)
{
-
ATAPI_PACKET_COMMAND Packet;
ATAPI_READ10_CMD *Read10Packet;
EFI_STATUS Status;
@@ -2217,27 +2202,27 @@ ReadSectors ( // fill command packet for Read(10) command
//
ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
- Read10Packet = &Packet.Read10;
- Lba32 = (UINT32) StartLba;
- PtrBuffer = Buffer;
+ Read10Packet = &Packet.Read10;
+ Lba32 = (UINT32)StartLba;
+ PtrBuffer = Buffer;
//
// limit the data bytes that can be transfered by one Read(10) Command
//
- MaxBlock = (UINT16) (0x10000 / BlockSize);
+ MaxBlock = (UINT16)(0x10000 / BlockSize);
//
// (64k bytes)
//
BlocksRemaining = NumberOfBlocks;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
while (BlocksRemaining > 0) {
-
if (BlocksRemaining <= MaxBlock) {
- SectorCount = (UINT16) BlocksRemaining;
+ SectorCount = (UINT16)BlocksRemaining;
} else {
SectorCount = MaxBlock;
}
+
//
// fill the Packet data sturcture
//
@@ -2247,34 +2232,34 @@ ReadSectors ( // Lba0 ~ Lba3 specify the start logical block address of the data transfer.
// Lba0 is MSB, Lba3 is LSB
//
- Read10Packet->Lba3 = (UINT8) (Lba32 & 0xff);
- Read10Packet->Lba2 = (UINT8) (Lba32 >> 8);
- Read10Packet->Lba1 = (UINT8) (Lba32 >> 16);
- Read10Packet->Lba0 = (UINT8) (Lba32 >> 24);
+ Read10Packet->Lba3 = (UINT8)(Lba32 & 0xff);
+ Read10Packet->Lba2 = (UINT8)(Lba32 >> 8);
+ Read10Packet->Lba1 = (UINT8)(Lba32 >> 16);
+ Read10Packet->Lba0 = (UINT8)(Lba32 >> 24);
//
// TranLen0 ~ TranLen1 specify the transfer length in block unit.
// TranLen0 is MSB, TranLen is LSB
//
- Read10Packet->TranLen1 = (UINT8) (SectorCount & 0xff);
- Read10Packet->TranLen0 = (UINT8) (SectorCount >> 8);
+ Read10Packet->TranLen1 = (UINT8)(SectorCount & 0xff);
+ Read10Packet->TranLen0 = (UINT8)(SectorCount >> 8);
- ByteCount = (UINT32) (SectorCount * BlockSize);
+ ByteCount = (UINT32)(SectorCount * BlockSize);
Status = AtapiPacketCommandIn (
- AtapiBlkIoDev,
- DevicePosition,
- &Packet,
- (UINT16 *) PtrBuffer,
- ByteCount,
- ATAPILONGTIMEOUT
- );
+ AtapiBlkIoDev,
+ DevicePosition,
+ &Packet,
+ (UINT16 *)PtrBuffer,
+ ByteCount,
+ ATAPILONGTIMEOUT
+ );
if (Status != EFI_SUCCESS) {
return Status;
}
- Lba32 += SectorCount;
- PtrBuffer = (UINT8 *) PtrBuffer + SectorCount * BlockSize;
+ Lba32 += SectorCount;
+ PtrBuffer = (UINT8 *)PtrBuffer + SectorCount * BlockSize;
BlocksRemaining -= SectorCount;
}
@@ -2303,10 +2288,9 @@ IsNoMedia ( IsNoMedia = FALSE;
- SensePtr = SenseData;
+ SensePtr = SenseData;
for (Index = 0; Index < SenseCounts; Index++) {
-
if ((SensePtr->sense_key == ATA_SK_NOT_READY) && (SensePtr->addnl_sense_code == ATA_ASC_NO_MEDIA)) {
IsNoMedia = TRUE;
}
@@ -2329,20 +2313,19 @@ IsNoMedia ( **/
BOOLEAN
IsDeviceStateUnclear (
- IN ATAPI_REQUEST_SENSE_DATA *SenseData,
- IN UINTN SenseCounts
+ IN ATAPI_REQUEST_SENSE_DATA *SenseData,
+ IN UINTN SenseCounts
)
{
ATAPI_REQUEST_SENSE_DATA *SensePtr;
UINTN Index;
BOOLEAN Unclear;
- Unclear = FALSE;
+ Unclear = FALSE;
- SensePtr = SenseData;
+ SensePtr = SenseData;
for (Index = 0; Index < SenseCounts; Index++) {
-
if (SensePtr->sense_key == 0x06) {
//
// Sense key is 0x06 means the device is just be reset or media just
@@ -2378,51 +2361,50 @@ IsMediaError ( UINTN Index;
BOOLEAN IsError;
- IsError = FALSE;
+ IsError = FALSE;
- SensePtr = SenseData;
+ SensePtr = SenseData;
for (Index = 0; Index < SenseCounts; Index++) {
-
switch (SensePtr->sense_key) {
+ case ATA_SK_MEDIUM_ERROR:
+ switch (SensePtr->addnl_sense_code) {
+ case ATA_ASC_MEDIA_ERR1:
+ //
+ // fall through
+ //
+ case ATA_ASC_MEDIA_ERR2:
+ //
+ // fall through
+ //
+ case ATA_ASC_MEDIA_ERR3:
+ //
+ // fall through
+ //
+ case ATA_ASC_MEDIA_ERR4:
+ IsError = TRUE;
+ break;
- case ATA_SK_MEDIUM_ERROR:
- switch (SensePtr->addnl_sense_code) {
- case ATA_ASC_MEDIA_ERR1:
- //
- // fall through
- //
- case ATA_ASC_MEDIA_ERR2:
- //
- // fall through
- //
- case ATA_ASC_MEDIA_ERR3:
- //
- // fall through
- //
- case ATA_ASC_MEDIA_ERR4:
- IsError = TRUE;
- break;
+ default:
+ break;
+ }
- default:
break;
- }
- break;
+ case ATA_SK_NOT_READY:
+ switch (SensePtr->addnl_sense_code) {
+ case ATA_ASC_MEDIA_UPSIDE_DOWN:
+ IsError = TRUE;
+ break;
+
+ default:
+ break;
+ }
- case ATA_SK_NOT_READY:
- switch (SensePtr->addnl_sense_code) {
- case ATA_ASC_MEDIA_UPSIDE_DOWN:
- IsError = TRUE;
break;
default:
break;
- }
- break;
-
- default:
- break;
}
SensePtr++;
@@ -2444,47 +2426,47 @@ IsMediaError ( **/
BOOLEAN
IsDriveReady (
- IN ATAPI_REQUEST_SENSE_DATA *SenseData,
- IN UINTN SenseCounts,
- OUT BOOLEAN *NeedRetry
+ IN ATAPI_REQUEST_SENSE_DATA *SenseData,
+ IN UINTN SenseCounts,
+ OUT BOOLEAN *NeedRetry
)
{
ATAPI_REQUEST_SENSE_DATA *SensePtr;
UINTN Index;
BOOLEAN IsReady;
- IsReady = TRUE;
- *NeedRetry = FALSE;
+ IsReady = TRUE;
+ *NeedRetry = FALSE;
- SensePtr = SenseData;
+ SensePtr = SenseData;
for (Index = 0; Index < SenseCounts; Index++) {
-
switch (SensePtr->sense_key) {
-
- case ATA_SK_NOT_READY:
- switch (SensePtr->addnl_sense_code) {
- case ATA_ASC_NOT_READY:
- switch (SensePtr->addnl_sense_code_qualifier) {
- case ATA_ASCQ_IN_PROGRESS:
- IsReady = FALSE;
- *NeedRetry = TRUE;
- break;
-
- default:
- IsReady = FALSE;
- *NeedRetry = FALSE;
- break;
+ case ATA_SK_NOT_READY:
+ switch (SensePtr->addnl_sense_code) {
+ case ATA_ASC_NOT_READY:
+ switch (SensePtr->addnl_sense_code_qualifier) {
+ case ATA_ASCQ_IN_PROGRESS:
+ IsReady = FALSE;
+ *NeedRetry = TRUE;
+ break;
+
+ default:
+ IsReady = FALSE;
+ *NeedRetry = FALSE;
+ break;
+ }
+
+ break;
+
+ default:
+ break;
}
+
break;
default:
break;
- }
- break;
-
- default:
- break;
}
SensePtr++;
diff --git a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.h b/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.h index 8851b11185..abc1dc661b 100644 --- a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.h +++ b/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.h @@ -26,12 +26,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
-
#include <IndustryStandard/Atapi.h>
-#define MAX_SENSE_KEY_COUNT 6
-#define MAX_IDE_CHANNELS 4 // Ide and Sata Primary, Secondary Channel.
-#define MAX_IDE_DEVICES 8 // Ide, Sata Primary, Secondary and Master, Slave device.
+#define MAX_SENSE_KEY_COUNT 6
+#define MAX_IDE_CHANNELS 4 // Ide and Sata Primary, Secondary Channel.
+#define MAX_IDE_DEVICES 8 // Ide, Sata Primary, Secondary and Master, Slave device.
typedef enum {
IdePrimary = 0,
@@ -40,72 +39,69 @@ typedef enum { } EFI_IDE_CHANNEL;
typedef enum {
- IdeMaster = 0,
- IdeSlave = 1,
- IdeMaxDevice = 2
+ IdeMaster = 0,
+ IdeSlave = 1,
+ IdeMaxDevice = 2
} EFI_IDE_DEVICE;
//
// IDE Registers
//
typedef union {
- UINT16 Command; /* when write */
- UINT16 Status; /* when read */
+ UINT16 Command; /* when write */
+ UINT16 Status; /* when read */
} IDE_CMD_OR_STATUS;
typedef union {
- UINT16 Error; /* when read */
- UINT16 Feature; /* when write */
+ UINT16 Error; /* when read */
+ UINT16 Feature; /* when write */
} IDE_ERROR_OR_FEATURE;
typedef union {
- UINT16 AltStatus; /* when read */
- UINT16 DeviceControl; /* when write */
+ UINT16 AltStatus; /* when read */
+ UINT16 DeviceControl; /* when write */
} IDE_ALTSTATUS_OR_DEVICECONTROL;
//
// IDE registers set
//
typedef struct {
- UINT16 Data;
- IDE_ERROR_OR_FEATURE Reg1;
- UINT16 SectorCount;
- UINT16 SectorNumber;
- UINT16 CylinderLsb;
- UINT16 CylinderMsb;
- UINT16 Head;
- IDE_CMD_OR_STATUS Reg;
-
- IDE_ALTSTATUS_OR_DEVICECONTROL Alt;
- UINT16 DriveAddress;
+ UINT16 Data;
+ IDE_ERROR_OR_FEATURE Reg1;
+ UINT16 SectorCount;
+ UINT16 SectorNumber;
+ UINT16 CylinderLsb;
+ UINT16 CylinderMsb;
+ UINT16 Head;
+ IDE_CMD_OR_STATUS Reg;
+
+ IDE_ALTSTATUS_OR_DEVICECONTROL Alt;
+ UINT16 DriveAddress;
} IDE_BASE_REGISTERS;
typedef struct {
-
- UINTN DevicePosition;
- EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
- EFI_PEI_BLOCK_IO2_MEDIA MediaInfo2;
-
+ UINTN DevicePosition;
+ EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
+ EFI_PEI_BLOCK_IO2_MEDIA MediaInfo2;
} PEI_ATAPI_DEVICE_INFO;
#define ATAPI_BLK_IO_DEV_SIGNATURE SIGNATURE_32 ('a', 'b', 'i', 'o')
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_PEI_RECOVERY_BLOCK_IO_PPI AtapiBlkIo;
- EFI_PEI_RECOVERY_BLOCK_IO2_PPI AtapiBlkIo2;
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor2;
- PEI_ATA_CONTROLLER_PPI *AtaControllerPpi;
+ EFI_PEI_RECOVERY_BLOCK_IO_PPI AtapiBlkIo;
+ EFI_PEI_RECOVERY_BLOCK_IO2_PPI AtapiBlkIo2;
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor2;
+ PEI_ATA_CONTROLLER_PPI *AtaControllerPpi;
- UINTN DeviceCount;
- PEI_ATAPI_DEVICE_INFO DeviceInfo[MAX_IDE_DEVICES]; //for max 8 device
- IDE_BASE_REGISTERS IdeIoPortReg[MAX_IDE_CHANNELS]; //for max 4 channel.
+ UINTN DeviceCount;
+ PEI_ATAPI_DEVICE_INFO DeviceInfo[MAX_IDE_DEVICES]; // for max 8 device
+ IDE_BASE_REGISTERS IdeIoPortReg[MAX_IDE_CHANNELS]; // for max 4 channel.
} ATAPI_BLK_IO_DEV;
-#define PEI_RECOVERY_ATAPI_FROM_BLKIO_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo, ATAPI_BLK_IO_DEV_SIGNATURE)
-#define PEI_RECOVERY_ATAPI_FROM_BLKIO2_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo2, ATAPI_BLK_IO_DEV_SIGNATURE)
-
+#define PEI_RECOVERY_ATAPI_FROM_BLKIO_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo, ATAPI_BLK_IO_DEV_SIGNATURE)
+#define PEI_RECOVERY_ATAPI_FROM_BLKIO2_THIS(a) CR (a, ATAPI_BLK_IO_DEV, AtapiBlkIo2, ATAPI_BLK_IO_DEV_SIGNATURE)
#define STALL_1_MILLI_SECOND 1000 // stall 1 ms
#define STALL_1_SECONDS 1000 * STALL_1_MILLI_SECOND
@@ -152,9 +148,9 @@ typedef struct { EFI_STATUS
EFIAPI
AtapiGetNumberOfBlockDevices (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
- OUT UINTN *NumberBlockDevices
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ OUT UINTN *NumberBlockDevices
);
/**
@@ -188,10 +184,10 @@ AtapiGetNumberOfBlockDevices ( EFI_STATUS
EFIAPI
AtapiGetBlockDeviceMediaInfo (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
- IN UINTN DeviceIndex,
- OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
);
/**
@@ -231,12 +227,12 @@ AtapiGetBlockDeviceMediaInfo ( EFI_STATUS
EFIAPI
AtapiReadBlocks (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
- IN UINTN DeviceIndex,
- IN EFI_PEI_LBA StartLBA,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
);
/**
@@ -261,9 +257,9 @@ AtapiReadBlocks ( EFI_STATUS
EFIAPI
AtapiGetNumberOfBlockDevices2 (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
- OUT UINTN *NumberBlockDevices
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ OUT UINTN *NumberBlockDevices
);
/**
@@ -297,10 +293,10 @@ AtapiGetNumberOfBlockDevices2 ( EFI_STATUS
EFIAPI
AtapiGetBlockDeviceMediaInfo2 (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
- IN UINTN DeviceIndex,
- OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
);
/**
@@ -340,12 +336,12 @@ AtapiGetBlockDeviceMediaInfo2 ( EFI_STATUS
EFIAPI
AtapiReadBlocks2 (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
- IN UINTN DeviceIndex,
- IN EFI_PEI_LBA StartLBA,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
);
//
@@ -379,10 +375,10 @@ AtapiEnumerateDevices ( **/
BOOLEAN
DiscoverAtapiDevice (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -397,8 +393,8 @@ DiscoverAtapiDevice ( **/
BOOLEAN
DetectIDEController (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition
);
/**
@@ -523,8 +519,8 @@ DRQReady2 ( **/
EFI_STATUS
CheckErrorStatus (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINT16 StatusReg
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINT16 StatusReg
);
/**
@@ -539,8 +535,8 @@ CheckErrorStatus ( **/
EFI_STATUS
ATAPIIdentify (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition
);
/**
@@ -556,9 +552,9 @@ ATAPIIdentify ( **/
EFI_STATUS
TestUnitReady (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition
- ) ;
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition
+ );
/**
Send out ATAPI commands conforms to the Packet Command with PIO Data In Protocol.
@@ -600,10 +596,10 @@ AtapiPacketCommandIn ( **/
EFI_STATUS
Inquiry (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -623,10 +619,10 @@ Inquiry ( **/
EFI_STATUS
DetectMedia (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -683,10 +679,10 @@ RequestSense ( **/
EFI_STATUS
ReadCapacity (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
- IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo,
+ IN OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo2
);
/**
@@ -705,12 +701,12 @@ ReadCapacity ( **/
EFI_STATUS
ReadSectors (
- IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
- IN UINTN DevicePosition,
- IN VOID *Buffer,
- IN EFI_PEI_LBA StartLba,
- IN UINTN NumberOfBlocks,
- IN UINTN BlockSize
+ IN ATAPI_BLK_IO_DEV *AtapiBlkIoDev,
+ IN UINTN DevicePosition,
+ IN VOID *Buffer,
+ IN EFI_PEI_LBA StartLba,
+ IN UINTN NumberOfBlocks,
+ IN UINTN BlockSize
);
/**
@@ -725,8 +721,8 @@ ReadSectors ( **/
BOOLEAN
IsNoMedia (
- IN ATAPI_REQUEST_SENSE_DATA *SenseData,
- IN UINTN SenseCounts
+ IN ATAPI_REQUEST_SENSE_DATA *SenseData,
+ IN UINTN SenseCounts
);
/**
@@ -741,8 +737,8 @@ IsNoMedia ( **/
BOOLEAN
IsDeviceStateUnclear (
- IN ATAPI_REQUEST_SENSE_DATA *SenseData,
- IN UINTN SenseCounts
+ IN ATAPI_REQUEST_SENSE_DATA *SenseData,
+ IN UINTN SenseCounts
);
/**
@@ -757,8 +753,8 @@ IsDeviceStateUnclear ( **/
BOOLEAN
IsMediaError (
- IN ATAPI_REQUEST_SENSE_DATA *SenseData,
- IN UINTN SenseCounts
+ IN ATAPI_REQUEST_SENSE_DATA *SenseData,
+ IN UINTN SenseCounts
);
/**
@@ -774,9 +770,9 @@ IsMediaError ( **/
BOOLEAN
IsDriveReady (
- IN ATAPI_REQUEST_SENSE_DATA *SenseData,
- IN UINTN SenseCounts,
- OUT BOOLEAN *NeedRetry
+ IN ATAPI_REQUEST_SENSE_DATA *SenseData,
+ IN UINTN SenseCounts,
+ OUT BOOLEAN *NeedRetry
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.c b/MdeModulePkg/Bus/Pci/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.c index be9f873c39..aae16cd856 100644 --- a/MdeModulePkg/Bus/Pci/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.c @@ -21,32 +21,32 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <IndustryStandard/Acpi.h>
typedef struct {
- UINT64 VendorId;
- UINT64 DeviceId;
- UINT64 RevisionId;
- UINT64 SubsystemVendorId;
- UINT64 SubsystemDeviceId;
+ UINT64 VendorId;
+ UINT64 DeviceId;
+ UINT64 RevisionId;
+ UINT64 SubsystemVendorId;
+ UINT64 SubsystemDeviceId;
} EFI_PCI_DEVICE_HEADER_INFO;
typedef struct {
- UINT64 ResType;
- UINT64 GenFlag;
- UINT64 SpecificFlag;
- UINT64 AddrSpaceGranularity;
- UINT64 AddrRangeMin;
- UINT64 AddrRangeMax;
- UINT64 AddrTranslationOffset;
- UINT64 AddrLen;
+ UINT64 ResType;
+ UINT64 GenFlag;
+ UINT64 SpecificFlag;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
} EFI_PCI_RESOUCE_DESCRIPTOR;
#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \
VendorId, DeviceId, Revision, SubVendorId, SubDeviceId
-#define DEVICE_INF_TAG 0xFFF2
-#define DEVICE_RES_TAG 0xFFF1
-#define LIST_END_TAG 0x0000
+#define DEVICE_INF_TAG 0xFFF2
+#define DEVICE_RES_TAG 0xFFF1
+#define LIST_END_TAG 0x0000
-#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
+#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
/**
Returns a list of ACPI resource descriptors that detail the special
@@ -82,7 +82,7 @@ PCheckDevice ( //
// Handle onto which the Incompatible PCI Device List is installed
//
-EFI_HANDLE mIncompatiblePciDeviceSupportHandle = NULL;
+EFI_HANDLE mIncompatiblePciDeviceSupportHandle = NULL;
//
// The Incompatible PCI Device Support Protocol instance produced by this driver
@@ -94,7 +94,7 @@ EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL mIncompatiblePciDeviceSupport = { //
// The incompatible PCI devices list template
//
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = {
//
// DEVICE_INF_TAG,
// PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),
@@ -106,7 +106,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = { // Device Adaptec 9004
//
DEVICE_INF_TAG,
- PCI_DEVICE_ID(0x9004, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
+ PCI_DEVICE_ID (0x9004, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -120,7 +120,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = { // Device Adaptec 9005
//
DEVICE_INF_TAG,
- PCI_DEVICE_ID(0x9005, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
+ PCI_DEVICE_ID (0x9005, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -134,7 +134,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = { // Device QLogic 1007
//
DEVICE_INF_TAG,
- PCI_DEVICE_ID(0x1077, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
+ PCI_DEVICE_ID (0x1077, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -148,7 +148,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = { // Device Agilent 103C
//
DEVICE_INF_TAG,
- PCI_DEVICE_ID(0x103C, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
+ PCI_DEVICE_ID (0x103C, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -162,7 +162,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = { // Device Agilent 15BC
//
DEVICE_INF_TAG,
- PCI_DEVICE_ID(0x15BC, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
+ PCI_DEVICE_ID (0x15BC, MAX_UINT64, MAX_UINT64, MAX_UINT64, MAX_UINT64),
DEVICE_RES_TAG,
ACPI_ADDRESS_SPACE_TYPE_IO,
0,
@@ -178,7 +178,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = { LIST_END_TAG
};
-
/**
Entry point of the incompatible pci device support code. Setup an incompatible device list template
and install EFI Incompatible PCI Device Support protocol.
@@ -193,11 +192,11 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mIncompatiblePciDeviceList[] = { EFI_STATUS
EFIAPI
IncompatiblePciDeviceSupportEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Install EFI Incompatible PCI Device Support Protocol on a new handle
@@ -244,15 +243,15 @@ PCheckDevice ( OUT VOID **Configuration
)
{
- UINT64 Tag;
- UINT64 *ListPtr;
- UINT64 *TempListPtr;
- EFI_PCI_DEVICE_HEADER_INFO *Header;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;
- EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;
- EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
- UINTN Index;
+ UINT64 Tag;
+ UINT64 *ListPtr;
+ UINT64 *TempListPtr;
+ EFI_PCI_DEVICE_HEADER_INFO *Header;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;
+ EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;
+ EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
+ UINTN Index;
//
// Validate the parameters
@@ -260,120 +259,121 @@ PCheckDevice ( if (Configuration == NULL) {
return EFI_INVALID_PARAMETER;
}
+
//
// Initialize the return value to NULL
//
- * (VOID **) Configuration = NULL;
+ *(VOID **)Configuration = NULL;
- ListPtr = mIncompatiblePciDeviceList;
+ ListPtr = mIncompatiblePciDeviceList;
while (*ListPtr != LIST_END_TAG) {
-
Tag = *ListPtr;
switch (Tag) {
- case DEVICE_INF_TAG:
- Header = (EFI_PCI_DEVICE_HEADER_INFO *) (ListPtr + 1);
- ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_HEADER_INFO) / sizeof (UINT64);
- //
- // See if the Header matches the parameters passed in
- //
- if ((Header->VendorId != MAX_UINT64) && (VendorId != MAX_UINTN)) {
- if (Header->VendorId != VendorId) {
- continue;
+ case DEVICE_INF_TAG:
+ Header = (EFI_PCI_DEVICE_HEADER_INFO *)(ListPtr + 1);
+ ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_HEADER_INFO) / sizeof (UINT64);
+ //
+ // See if the Header matches the parameters passed in
+ //
+ if ((Header->VendorId != MAX_UINT64) && (VendorId != MAX_UINTN)) {
+ if (Header->VendorId != VendorId) {
+ continue;
+ }
}
- }
- if ((Header->DeviceId != MAX_UINT64) && (DeviceId != MAX_UINTN)) {
- if (DeviceId != Header->DeviceId) {
- continue;
+ if ((Header->DeviceId != MAX_UINT64) && (DeviceId != MAX_UINTN)) {
+ if (DeviceId != Header->DeviceId) {
+ continue;
+ }
}
- }
- if ((Header->RevisionId != MAX_UINT64) && (RevisionId != MAX_UINTN)) {
- if (RevisionId != Header->RevisionId) {
- continue;
+ if ((Header->RevisionId != MAX_UINT64) && (RevisionId != MAX_UINTN)) {
+ if (RevisionId != Header->RevisionId) {
+ continue;
+ }
}
- }
- if ((Header->SubsystemVendorId != MAX_UINT64) && (SubsystemVendorId != MAX_UINTN)) {
- if (SubsystemVendorId != Header->SubsystemVendorId) {
- continue;
+ if ((Header->SubsystemVendorId != MAX_UINT64) && (SubsystemVendorId != MAX_UINTN)) {
+ if (SubsystemVendorId != Header->SubsystemVendorId) {
+ continue;
+ }
}
- }
- if ((Header->SubsystemDeviceId != MAX_UINT64) && (SubsystemDeviceId != MAX_UINTN)) {
- if (SubsystemDeviceId != Header->SubsystemDeviceId) {
- continue;
+ if ((Header->SubsystemDeviceId != MAX_UINT64) && (SubsystemDeviceId != MAX_UINTN)) {
+ if (SubsystemDeviceId != Header->SubsystemDeviceId) {
+ continue;
+ }
}
- }
- //
- // Matched an item, so construct the ACPI descriptor for the resource.
- //
- //
- // Count the resource items so that to allocate space
- //
- for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {
- TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
- }
- //
- // If there is at least one type of resource request,
- // allocate an acpi resource node
- //
- if (Index == 0) {
- return EFI_UNSUPPORTED;
- }
-
- AcpiPtr = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
- if (AcpiPtr == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- OldAcpiPtr = AcpiPtr;
- //
- // Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure
- // according to the EFI_PCI_RESOUCE_DESCRIPTOR structure
- //
- for (; *ListPtr == DEVICE_RES_TAG;) {
-
- Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *) (ListPtr + 1);
-
- AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- AcpiPtr->Len = (UINT16) sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
- AcpiPtr->ResType = (UINT8) Dsc->ResType;
- AcpiPtr->GenFlag = (UINT8) Dsc->GenFlag;
- AcpiPtr->SpecificFlag = (UINT8) Dsc->SpecificFlag;
- AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;;
- AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;
- AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;
- AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;
- AcpiPtr->AddrLen = Dsc->AddrLen;
+ //
+ // Matched an item, so construct the ACPI descriptor for the resource.
+ //
+ //
+ // Count the resource items so that to allocate space
+ //
+ for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {
+ TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
+ }
+
+ //
+ // If there is at least one type of resource request,
+ // allocate an acpi resource node
+ //
+ if (Index == 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ AcpiPtr = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
+ if (AcpiPtr == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ OldAcpiPtr = AcpiPtr;
+ //
+ // Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure
+ // according to the EFI_PCI_RESOUCE_DESCRIPTOR structure
+ //
+ for ( ; *ListPtr == DEVICE_RES_TAG;) {
+ Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *)(ListPtr + 1);
+
+ AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ AcpiPtr->Len = (UINT16)sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ AcpiPtr->ResType = (UINT8)Dsc->ResType;
+ AcpiPtr->GenFlag = (UINT8)Dsc->GenFlag;
+ AcpiPtr->SpecificFlag = (UINT8)Dsc->SpecificFlag;
+ AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;
+ AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;
+ AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;
+ AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;
+ AcpiPtr->AddrLen = Dsc->AddrLen;
+
+ ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
+ AcpiPtr++;
+ }
+
+ //
+ // Put the checksum
+ //
+ PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *)(AcpiPtr);
+ PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
+ PtrEnd->Checksum = 0;
+
+ *(VOID **)Configuration = OldAcpiPtr;
+
+ return EFI_SUCCESS;
+
+ case DEVICE_RES_TAG:
+ //
+ // Adjust the pointer to the next PCI resource descriptor item
+ //
ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
- AcpiPtr++;
- }
- //
- // Put the checksum
- //
- PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AcpiPtr);
- PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
- PtrEnd->Checksum = 0;
-
- *(VOID **) Configuration = OldAcpiPtr;
-
- return EFI_SUCCESS;
-
- case DEVICE_RES_TAG:
- //
- // Adjust the pointer to the next PCI resource descriptor item
- //
- ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));
- break;
-
- default:
- return EFI_UNSUPPORTED;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
}
}
return EFI_UNSUPPORTED;
}
-
diff --git a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/ComponentName.c index 74b6e281b3..af1b2e5526 100644 --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/ComponentName.c @@ -17,12 +17,12 @@ //
STATIC
-EFI_UNICODE_STRING_TABLE mDriverNameTable[] = {
+EFI_UNICODE_STRING_TABLE mDriverNameTable[] = {
{ "eng;en", L"PCI I/O protocol emulation driver for non-discoverable devices" },
- { NULL, NULL }
+ { NULL, NULL }
};
-EFI_COMPONENT_NAME_PROTOCOL gComponentName;
+EFI_COMPONENT_NAME_PROTOCOL gComponentName;
/**
Retrieves a Unicode string that is the user readable name of the UEFI Driver.
@@ -49,9 +49,9 @@ STATIC EFI_STATUS
EFIAPI
NonDiscoverablePciGetDriverName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN CHAR8 *Language,
- OUT CHAR16 **DriverName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -93,24 +93,24 @@ STATIC EFI_STATUS
EFIAPI
NonDiscoverablePciGetDeviceName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE DeviceHandle,
- IN EFI_HANDLE ChildHandle,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE DeviceHandle,
+ IN EFI_HANDLE ChildHandle,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
return EFI_UNSUPPORTED;
}
-EFI_COMPONENT_NAME_PROTOCOL gComponentName = {
+EFI_COMPONENT_NAME_PROTOCOL gComponentName = {
&NonDiscoverablePciGetDriverName,
&NonDiscoverablePciGetDeviceName,
"eng" // SupportedLanguages, ISO 639-2 language codes
};
-EFI_COMPONENT_NAME2_PROTOCOL gComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) &NonDiscoverablePciGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) &NonDiscoverablePciGetDeviceName,
+EFI_COMPONENT_NAME2_PROTOCOL gComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)&NonDiscoverablePciGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)&NonDiscoverablePciGetDeviceName,
"en" // SupportedLanguages, RFC 4646 language codes
};
diff --git a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.c b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.c index 5c93e2a766..96fc03979c 100644 --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.c +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.c @@ -10,16 +10,16 @@ #include <Protocol/DriverBinding.h>
-#define MAX_NON_DISCOVERABLE_PCI_DEVICE_ID (32 * 256)
+#define MAX_NON_DISCOVERABLE_PCI_DEVICE_ID (32 * 256)
-STATIC UINTN mUniqueIdCounter = 0;
-EFI_CPU_ARCH_PROTOCOL *mCpu;
+STATIC UINTN mUniqueIdCounter = 0;
+EFI_CPU_ARCH_PROTOCOL *mCpu;
//
// We only support the following device types
//
STATIC
-CONST EFI_GUID * CONST
+CONST EFI_GUID *CONST
SupportedNonDiscoverableDevices[] = {
&gEdkiiNonDiscoverableAhciDeviceGuid,
&gEdkiiNonDiscoverableEhciDeviceGuid,
@@ -63,27 +63,31 @@ STATIC EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE DeviceHandle,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE DeviceHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- NON_DISCOVERABLE_DEVICE *Device;
- EFI_STATUS Status;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- INTN Idx;
-
- Status = gBS->OpenProtocol (DeviceHandle,
- &gEdkiiNonDiscoverableDeviceProtocolGuid, (VOID **)&Device,
- This->DriverBindingHandle, DeviceHandle,
- EFI_OPEN_PROTOCOL_BY_DRIVER);
+ NON_DISCOVERABLE_DEVICE *Device;
+ EFI_STATUS Status;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ INTN Idx;
+
+ Status = gBS->OpenProtocol (
+ DeviceHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ (VOID **)&Device,
+ This->DriverBindingHandle,
+ DeviceHandle,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
if (EFI_ERROR (Status)) {
return Status;
}
Status = EFI_UNSUPPORTED;
for (Idx = 0; Idx < ARRAY_SIZE (SupportedNonDiscoverableDevices); Idx++) {
- if (CompareGuid (Device->Type, SupportedNonDiscoverableDevices [Idx])) {
+ if (CompareGuid (Device->Type, SupportedNonDiscoverableDevices[Idx])) {
Status = EFI_SUCCESS;
break;
}
@@ -98,17 +102,23 @@ NonDiscoverablePciDeviceSupported ( // that they only describe things that we can handle
//
for (Desc = Device->Resources; Desc->Desc != ACPI_END_TAG_DESCRIPTOR;
- Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3)) {
- if (Desc->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR ||
- Desc->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3))
+ {
+ if ((Desc->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) ||
+ (Desc->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM))
+ {
Status = EFI_UNSUPPORTED;
break;
}
}
CloseProtocol:
- gBS->CloseProtocol (DeviceHandle, &gEdkiiNonDiscoverableDeviceProtocolGuid,
- This->DriverBindingHandle, DeviceHandle);
+ gBS->CloseProtocol (
+ DeviceHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ This->DriverBindingHandle,
+ DeviceHandle
+ );
return Status;
}
@@ -130,13 +140,13 @@ STATIC EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE DeviceHandle,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE DeviceHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_STATUS Status;
ASSERT (mUniqueIdCounter < MAX_NON_DISCOVERABLE_PCI_DEVICE_ID);
if (mUniqueIdCounter >= MAX_NON_DISCOVERABLE_PCI_DEVICE_ID) {
@@ -148,10 +158,14 @@ NonDiscoverablePciDeviceStart ( return EFI_OUT_OF_RESOURCES;
}
- Status = gBS->OpenProtocol (DeviceHandle,
+ Status = gBS->OpenProtocol (
+ DeviceHandle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
- (VOID **)&Dev->Device, This->DriverBindingHandle,
- DeviceHandle, EFI_OPEN_PROTOCOL_BY_DRIVER);
+ (VOID **)&Dev->Device,
+ This->DriverBindingHandle,
+ DeviceHandle,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
if (EFI_ERROR (Status)) {
goto FreeDev;
}
@@ -163,8 +177,12 @@ NonDiscoverablePciDeviceStart ( // EFI_PCI_IO_PROTOCOL interface.
//
Dev->Signature = NON_DISCOVERABLE_PCI_DEVICE_SIG;
- Status = gBS->InstallProtocolInterface (&DeviceHandle, &gEfiPciIoProtocolGuid,
- EFI_NATIVE_INTERFACE, &Dev->PciIo);
+ Status = gBS->InstallProtocolInterface (
+ &DeviceHandle,
+ &gEfiPciIoProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &Dev->PciIo
+ );
if (EFI_ERROR (Status)) {
goto CloseProtocol;
}
@@ -174,8 +192,12 @@ NonDiscoverablePciDeviceStart ( return EFI_SUCCESS;
CloseProtocol:
- gBS->CloseProtocol (DeviceHandle, &gEdkiiNonDiscoverableDeviceProtocolGuid,
- This->DriverBindingHandle, DeviceHandle);
+ gBS->CloseProtocol (
+ DeviceHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ This->DriverBindingHandle,
+ DeviceHandle
+ );
FreeDev:
FreePool (Dev);
@@ -199,19 +221,24 @@ STATIC EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE DeviceHandle,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE DeviceHandle,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
-
- Status = gBS->OpenProtocol (DeviceHandle, &gEfiPciIoProtocolGuid,
- (VOID **)&PciIo, This->DriverBindingHandle, DeviceHandle,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+
+ Status = gBS->OpenProtocol (
+ DeviceHandle,
+ &gEfiPciIoProtocolGuid,
+ (VOID **)&PciIo,
+ This->DriverBindingHandle,
+ DeviceHandle,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -221,27 +248,33 @@ NonDiscoverablePciDeviceStop ( //
// Handle Stop() requests for in-use driver instances gracefully.
//
- Status = gBS->UninstallProtocolInterface (DeviceHandle,
- &gEfiPciIoProtocolGuid, &Dev->PciIo);
+ Status = gBS->UninstallProtocolInterface (
+ DeviceHandle,
+ &gEfiPciIoProtocolGuid,
+ &Dev->PciIo
+ );
if (EFI_ERROR (Status)) {
return Status;
}
- gBS->CloseProtocol (DeviceHandle, &gEdkiiNonDiscoverableDeviceProtocolGuid,
- This->DriverBindingHandle, DeviceHandle);
+ gBS->CloseProtocol (
+ DeviceHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ This->DriverBindingHandle,
+ DeviceHandle
+ );
FreePool (Dev);
return EFI_SUCCESS;
}
-
//
// The static object that groups the Supported() (ie. probe), Start() and
// Stop() functions of the driver together. Refer to UEFI Spec 2.3.1 + Errata
// C, 10.1 EFI Driver Binding Protocol.
//
-STATIC EFI_DRIVER_BINDING_PROTOCOL gDriverBinding = {
+STATIC EFI_DRIVER_BINDING_PROTOCOL gDriverBinding = {
&NonDiscoverablePciDeviceSupported,
&NonDiscoverablePciDeviceStart,
&NonDiscoverablePciDeviceStop,
@@ -263,14 +296,14 @@ STATIC EFI_DRIVER_BINDING_PROTOCOL gDriverBinding = { EFI_STATUS
EFIAPI
NonDiscoverablePciDeviceDxeEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
- ASSERT_EFI_ERROR(Status);
+ ASSERT_EFI_ERROR (Status);
return EfiLibInstallDriverBindingComponentName2 (
ImageHandle,
diff --git a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c index 363c4a765b..c1c5c6267c 100644 --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c @@ -16,10 +16,10 @@ #include <Protocol/PciRootBridgeIo.h>
typedef struct {
- EFI_PHYSICAL_ADDRESS AllocAddress;
- VOID *HostAddress;
- EFI_PCI_IO_PROTOCOL_OPERATION Operation;
- UINTN NumberOfBytes;
+ EFI_PHYSICAL_ADDRESS AllocAddress;
+ VOID *HostAddress;
+ EFI_PCI_IO_PROTOCOL_OPERATION Operation;
+ UINTN NumberOfBytes;
} NON_DISCOVERABLE_PCI_DEVICE_MAP_INFO;
/**
@@ -33,12 +33,12 @@ typedef struct { STATIC
EFI_STATUS
GetBarResource (
- IN NON_DISCOVERABLE_PCI_DEVICE *Dev,
- IN UINT8 BarIndex,
- OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptor
+ IN NON_DISCOVERABLE_PCI_DEVICE *Dev,
+ IN UINT8 BarIndex,
+ OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptor
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
if (BarIndex < Dev->BarOffset) {
return EFI_NOT_FOUND;
@@ -52,8 +52,8 @@ GetBarResource ( for (Desc = Dev->Device->Resources;
Desc->Desc != ACPI_END_TAG_DESCRIPTOR;
- Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3)) {
-
+ Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3))
+ {
if (BarIndex == 0) {
*Descriptor = Desc;
return EFI_SUCCESS;
@@ -61,6 +61,7 @@ GetBarResource ( BarIndex -= 1;
}
+
return EFI_NOT_FOUND;
}
@@ -83,20 +84,20 @@ STATIC EFI_STATUS
EFIAPI
PciIoPollMem (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 BarIndex,
- IN UINT64 Offset,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- UINTN Count;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ UINTN Count;
+ EFI_STATUS Status;
if ((UINT32)Width > EfiPciIoWidthUint64) {
return EFI_INVALID_PARAMETER;
@@ -106,7 +107,7 @@ PciIoPollMem ( return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Count = 1;
Status = GetBarResource (Dev, BarIndex, &Desc);
@@ -141,20 +142,20 @@ STATIC EFI_STATUS
EFIAPI
PciIoPollIo (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 BarIndex,
- IN UINT64 Offset,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- UINTN Count;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ UINTN Count;
+ EFI_STATUS Status;
if ((UINT32)Width > EfiPciIoWidthUint64) {
return EFI_INVALID_PARAMETER;
@@ -164,7 +165,7 @@ PciIoPollIo ( return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Count = 1;
Status = GetBarResource (Dev, BarIndex, &Desc);
@@ -200,48 +201,51 @@ STATIC EFI_STATUS
EFIAPI
PciIoMemRW (
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINTN Count,
- IN UINTN DstStride,
- IN VOID *Dst,
- IN UINTN SrcStride,
- OUT CONST VOID *Src
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINTN Count,
+ IN UINTN DstStride,
+ IN VOID *Dst,
+ IN UINTN SrcStride,
+ OUT CONST VOID *Src
)
{
- volatile UINT8 *Dst8;
- volatile UINT16 *Dst16;
- volatile UINT32 *Dst32;
- volatile CONST UINT8 *Src8;
- volatile CONST UINT16 *Src16;
- volatile CONST UINT32 *Src32;
+ volatile UINT8 *Dst8;
+ volatile UINT16 *Dst16;
+ volatile UINT32 *Dst32;
+ volatile CONST UINT8 *Src8;
+ volatile CONST UINT16 *Src16;
+ volatile CONST UINT32 *Src32;
//
// Loop for each iteration and move the data
//
switch (Width & 0x3) {
- case EfiPciWidthUint8:
- Dst8 = (UINT8 *)Dst;
- Src8 = (UINT8 *)Src;
- for (;Count > 0; Count--, Dst8 += DstStride, Src8 += SrcStride) {
- *Dst8 = *Src8;
- }
- break;
- case EfiPciWidthUint16:
- Dst16 = (UINT16 *)Dst;
- Src16 = (UINT16 *)Src;
- for (;Count > 0; Count--, Dst16 += DstStride, Src16 += SrcStride) {
- *Dst16 = *Src16;
- }
- break;
- case EfiPciWidthUint32:
- Dst32 = (UINT32 *)Dst;
- Src32 = (UINT32 *)Src;
- for (;Count > 0; Count--, Dst32 += DstStride, Src32 += SrcStride) {
- *Dst32 = *Src32;
- }
- break;
- default:
- return EFI_INVALID_PARAMETER;
+ case EfiPciWidthUint8:
+ Dst8 = (UINT8 *)Dst;
+ Src8 = (UINT8 *)Src;
+ for ( ; Count > 0; Count--, Dst8 += DstStride, Src8 += SrcStride) {
+ *Dst8 = *Src8;
+ }
+
+ break;
+ case EfiPciWidthUint16:
+ Dst16 = (UINT16 *)Dst;
+ Src16 = (UINT16 *)Src;
+ for ( ; Count > 0; Count--, Dst16 += DstStride, Src16 += SrcStride) {
+ *Dst16 = *Src16;
+ }
+
+ break;
+ case EfiPciWidthUint32:
+ Dst32 = (UINT32 *)Dst;
+ Src32 = (UINT32 *)Src;
+ for ( ; Count > 0; Count--, Dst32 += DstStride, Src32 += SrcStride) {
+ *Dst32 = *Src32;
+ }
+
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
@@ -271,25 +275,25 @@ STATIC EFI_STATUS
EFIAPI
PciIoMemRead (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 BarIndex,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- UINTN AlignMask;
- VOID *Address;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ UINTN AlignMask;
+ VOID *Address;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ EFI_STATUS Status;
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
//
// Only allow accesses to the BARs we emulate
@@ -303,34 +307,35 @@ PciIoMemRead ( return EFI_UNSUPPORTED;
}
- Address = (VOID *)(UINTN)(Desc->AddrRangeMin + Offset);
+ Address = (VOID *)(UINTN)(Desc->AddrRangeMin + Offset);
AlignMask = (1 << (Width & 0x03)) - 1;
if ((UINTN)Address & AlignMask) {
return EFI_INVALID_PARAMETER;
}
switch (Width) {
- case EfiPciIoWidthUint8:
- case EfiPciIoWidthUint16:
- case EfiPciIoWidthUint32:
- case EfiPciIoWidthUint64:
- return PciIoMemRW (Width, Count, 1, Buffer, 1, Address);
-
- case EfiPciIoWidthFifoUint8:
- case EfiPciIoWidthFifoUint16:
- case EfiPciIoWidthFifoUint32:
- case EfiPciIoWidthFifoUint64:
- return PciIoMemRW (Width, Count, 1, Buffer, 0, Address);
-
- case EfiPciIoWidthFillUint8:
- case EfiPciIoWidthFillUint16:
- case EfiPciIoWidthFillUint32:
- case EfiPciIoWidthFillUint64:
- return PciIoMemRW (Width, Count, 0, Buffer, 1, Address);
-
- default:
- break;
+ case EfiPciIoWidthUint8:
+ case EfiPciIoWidthUint16:
+ case EfiPciIoWidthUint32:
+ case EfiPciIoWidthUint64:
+ return PciIoMemRW (Width, Count, 1, Buffer, 1, Address);
+
+ case EfiPciIoWidthFifoUint8:
+ case EfiPciIoWidthFifoUint16:
+ case EfiPciIoWidthFifoUint32:
+ case EfiPciIoWidthFifoUint64:
+ return PciIoMemRW (Width, Count, 1, Buffer, 0, Address);
+
+ case EfiPciIoWidthFillUint8:
+ case EfiPciIoWidthFillUint16:
+ case EfiPciIoWidthFillUint32:
+ case EfiPciIoWidthFillUint64:
+ return PciIoMemRW (Width, Count, 0, Buffer, 1, Address);
+
+ default:
+ break;
}
+
return EFI_INVALID_PARAMETER;
}
@@ -358,25 +363,25 @@ STATIC EFI_STATUS
EFIAPI
PciIoMemWrite (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 BarIndex,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- UINTN AlignMask;
- VOID *Address;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ UINTN AlignMask;
+ VOID *Address;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ EFI_STATUS Status;
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
//
// Only allow accesses to the BARs we emulate
@@ -390,34 +395,35 @@ PciIoMemWrite ( return EFI_UNSUPPORTED;
}
- Address = (VOID *)(UINTN)(Desc->AddrRangeMin + Offset);
+ Address = (VOID *)(UINTN)(Desc->AddrRangeMin + Offset);
AlignMask = (1 << (Width & 0x03)) - 1;
if ((UINTN)Address & AlignMask) {
return EFI_INVALID_PARAMETER;
}
switch (Width) {
- case EfiPciIoWidthUint8:
- case EfiPciIoWidthUint16:
- case EfiPciIoWidthUint32:
- case EfiPciIoWidthUint64:
- return PciIoMemRW (Width, Count, 1, Address, 1, Buffer);
-
- case EfiPciIoWidthFifoUint8:
- case EfiPciIoWidthFifoUint16:
- case EfiPciIoWidthFifoUint32:
- case EfiPciIoWidthFifoUint64:
- return PciIoMemRW (Width, Count, 0, Address, 1, Buffer);
-
- case EfiPciIoWidthFillUint8:
- case EfiPciIoWidthFillUint16:
- case EfiPciIoWidthFillUint32:
- case EfiPciIoWidthFillUint64:
- return PciIoMemRW (Width, Count, 1, Address, 0, Buffer);
-
- default:
- break;
+ case EfiPciIoWidthUint8:
+ case EfiPciIoWidthUint16:
+ case EfiPciIoWidthUint32:
+ case EfiPciIoWidthUint64:
+ return PciIoMemRW (Width, Count, 1, Address, 1, Buffer);
+
+ case EfiPciIoWidthFifoUint8:
+ case EfiPciIoWidthFifoUint16:
+ case EfiPciIoWidthFifoUint32:
+ case EfiPciIoWidthFifoUint64:
+ return PciIoMemRW (Width, Count, 0, Address, 1, Buffer);
+
+ case EfiPciIoWidthFillUint8:
+ case EfiPciIoWidthFillUint16:
+ case EfiPciIoWidthFillUint32:
+ case EfiPciIoWidthFillUint64:
+ return PciIoMemRW (Width, Count, 1, Address, 0, Buffer);
+
+ default:
+ break;
}
+
return EFI_INVALID_PARAMETER;
}
@@ -438,17 +444,17 @@ STATIC EFI_STATUS
EFIAPI
PciIoIoRead (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 BarIndex,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ EFI_STATUS Status;
if ((UINT32)Width >= EfiPciIoWidthMaximum) {
return EFI_INVALID_PARAMETER;
@@ -458,7 +464,7 @@ PciIoIoRead ( return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Status = GetBarResource (Dev, BarIndex, &Desc);
if (EFI_ERROR (Status)) {
@@ -490,17 +496,17 @@ STATIC EFI_STATUS
EFIAPI
PciIoIoWrite (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 BarIndex,
- IN UINT64 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ EFI_STATUS Status;
if ((UINT32)Width >= EfiPciIoWidthMaximum) {
return EFI_INVALID_PARAMETER;
@@ -510,7 +516,7 @@ PciIoIoWrite ( return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Status = GetBarResource (Dev, BarIndex, &Desc);
if (EFI_ERROR (Status)) {
@@ -547,17 +553,17 @@ PciIoPciRead ( IN OUT VOID *Buffer
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- VOID *Address;
- UINTN Length;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ VOID *Address;
+ UINTN Length;
- if (Width < 0 || Width >= EfiPciIoWidthMaximum || Buffer == NULL) {
+ if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Address = (UINT8 *)&Dev->ConfigSpace + Offset;
- Length = Count << ((UINTN)Width & 0x3);
+ Length = Count << ((UINTN)Width & 0x3);
if (Offset >= sizeof (Dev->ConfigSpace)) {
ZeroMem (Buffer, Length);
@@ -574,6 +580,7 @@ PciIoPciRead ( Count -= Length >> ((UINTN)Width & 0x3);
}
+
return PciIoMemRW (Width, Count, 1, Buffer, 1, Address);
}
@@ -597,21 +604,21 @@ STATIC EFI_STATUS
EFIAPI
PciIoPciWrite (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT32 Offset,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- VOID *Address;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ VOID *Address;
- if (Width < 0 || Width >= EfiPciIoWidthMaximum || Buffer == NULL) {
+ if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Address = (UINT8 *)&Dev->ConfigSpace + Offset;
if (Offset + (Count << ((UINTN)Width & 0x3)) > sizeof (Dev->ConfigSpace)) {
@@ -643,25 +650,25 @@ STATIC EFI_STATUS
EFIAPI
PciIoCopyMem (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 DestBarIndex,
- IN UINT64 DestOffset,
- IN UINT8 SrcBarIndex,
- IN UINT64 SrcOffset,
- IN UINTN Count
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *DestDesc;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *SrcDesc;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *DestDesc;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *SrcDesc;
+ EFI_STATUS Status;
if ((UINT32)Width > EfiPciIoWidthUint64) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Status = GetBarResource (Dev, DestBarIndex, &DestDesc);
if (EFI_ERROR (Status)) {
@@ -720,16 +727,18 @@ CoherentPciIoMap ( EFI_STATUS Status;
NON_DISCOVERABLE_PCI_DEVICE_MAP_INFO *MapInfo;
- if (Operation != EfiPciIoOperationBusMasterRead &&
- Operation != EfiPciIoOperationBusMasterWrite &&
- Operation != EfiPciIoOperationBusMasterCommonBuffer) {
+ if ((Operation != EfiPciIoOperationBusMasterRead) &&
+ (Operation != EfiPciIoOperationBusMasterWrite) &&
+ (Operation != EfiPciIoOperationBusMasterCommonBuffer))
+ {
return EFI_INVALID_PARAMETER;
}
- if (HostAddress == NULL ||
- NumberOfBytes == NULL ||
- DeviceAddress == NULL ||
- Mapping == NULL) {
+ if ((HostAddress == NULL) ||
+ (NumberOfBytes == NULL) ||
+ (DeviceAddress == NULL) ||
+ (Mapping == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -737,10 +746,10 @@ CoherentPciIoMap ( // If HostAddress exceeds 4 GB, and this device does not support 64-bit DMA
// addressing, we need to allocate a bounce buffer and copy over the data.
//
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
- if ((Dev->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0 &&
- (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress + *NumberOfBytes > SIZE_4GB) {
-
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
+ if (((Dev->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) &&
+ ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress + *NumberOfBytes > SIZE_4GB))
+ {
//
// Bounce buffering is not possible for consistent mappings
//
@@ -753,14 +762,17 @@ CoherentPciIoMap ( return EFI_OUT_OF_RESOURCES;
}
- MapInfo->AllocAddress = MAX_UINT32;
- MapInfo->HostAddress = HostAddress;
- MapInfo->Operation = Operation;
+ MapInfo->AllocAddress = MAX_UINT32;
+ MapInfo->HostAddress = HostAddress;
+ MapInfo->Operation = Operation;
MapInfo->NumberOfBytes = *NumberOfBytes;
- Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData,
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiBootServicesData,
EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes),
- &MapInfo->AllocAddress);
+ &MapInfo->AllocAddress
+ );
if (EFI_ERROR (Status)) {
//
// If we fail here, it is likely because the system has no memory below
@@ -770,16 +782,22 @@ CoherentPciIoMap ( FreePool (MapInfo);
return EFI_DEVICE_ERROR;
}
+
if (Operation == EfiPciIoOperationBusMasterRead) {
- gBS->CopyMem ((VOID *)(UINTN)MapInfo->AllocAddress, HostAddress,
- *NumberOfBytes);
+ gBS->CopyMem (
+ (VOID *)(UINTN)MapInfo->AllocAddress,
+ HostAddress,
+ *NumberOfBytes
+ );
}
+
*DeviceAddress = MapInfo->AllocAddress;
- *Mapping = MapInfo;
+ *Mapping = MapInfo;
} else {
*DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
- *Mapping = NULL;
+ *Mapping = NULL;
}
+
return EFI_SUCCESS;
}
@@ -796,8 +814,8 @@ STATIC EFI_STATUS
EFIAPI
CoherentPciIoUnmap (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN VOID *Mapping
)
{
NON_DISCOVERABLE_PCI_DEVICE_MAP_INFO *MapInfo;
@@ -805,13 +823,20 @@ CoherentPciIoUnmap ( MapInfo = Mapping;
if (MapInfo != NULL) {
if (MapInfo->Operation == EfiPciIoOperationBusMasterWrite) {
- gBS->CopyMem (MapInfo->HostAddress, (VOID *)(UINTN)MapInfo->AllocAddress,
- MapInfo->NumberOfBytes);
+ gBS->CopyMem (
+ MapInfo->HostAddress,
+ (VOID *)(UINTN)MapInfo->AllocAddress,
+ MapInfo->NumberOfBytes
+ );
}
- gBS->FreePages (MapInfo->AllocAddress,
- EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes));
+
+ gBS->FreePages (
+ MapInfo->AllocAddress,
+ EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes)
+ );
FreePool (MapInfo);
}
+
return EFI_SUCCESS;
}
@@ -838,21 +863,22 @@ STATIC EFI_STATUS
EFIAPI
CoherentPciIoAllocateBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_PHYSICAL_ADDRESS AllocAddress;
- EFI_ALLOCATE_TYPE AllocType;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_PHYSICAL_ADDRESS AllocAddress;
+ EFI_ALLOCATE_TYPE AllocType;
+ EFI_STATUS Status;
if ((Attributes & ~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE |
- EFI_PCI_ATTRIBUTE_MEMORY_CACHED)) != 0) {
+ EFI_PCI_ATTRIBUTE_MEMORY_CACHED)) != 0)
+ {
return EFI_UNSUPPORTED;
}
@@ -861,7 +887,8 @@ CoherentPciIoAllocateBuffer ( }
if ((MemoryType != EfiBootServicesData) &&
- (MemoryType != EfiRuntimeServicesData)) {
+ (MemoryType != EfiRuntimeServicesData))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -870,10 +897,10 @@ CoherentPciIoAllocateBuffer ( // been set. If the system has no memory available below 4 GB, there
// is little we can do except propagate the error.
//
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
if ((Dev->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
AllocAddress = MAX_UINT32;
- AllocType = AllocateMaxAddress;
+ AllocType = AllocateMaxAddress;
} else {
AllocType = AllocateAnyPages;
}
@@ -882,6 +909,7 @@ CoherentPciIoAllocateBuffer ( if (!EFI_ERROR (Status)) {
*HostAddress = (VOID *)(UINTN)AllocAddress;
}
+
return Status;
}
@@ -899,9 +927,9 @@ STATIC EFI_STATUS
EFIAPI
CoherentPciIoFreeBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINTN Pages,
- IN VOID *HostAddress
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
)
{
FreePages (HostAddress, Pages);
@@ -923,18 +951,18 @@ STATIC EFI_STATUS
EFIAPI
NonCoherentPciIoFreeBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINTN Pages,
- IN VOID *HostAddress
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- LIST_ENTRY *Entry;
- EFI_STATUS Status;
- NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION *Alloc;
- BOOLEAN Found;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ LIST_ENTRY *Entry;
+ EFI_STATUS Status;
+ NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION *Alloc;
+ BOOLEAN Found;
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Found = FALSE;
Alloc = NULL;
@@ -945,10 +973,10 @@ NonCoherentPciIoFreeBuffer ( //
for (Entry = Dev->UncachedAllocationList.ForwardLink;
Entry != &Dev->UncachedAllocationList;
- Entry = Entry->ForwardLink) {
-
+ Entry = Entry->ForwardLink)
+ {
Alloc = BASE_CR (Entry, NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION, List);
- if (Alloc->HostAddress == HostAddress && Alloc->NumPages == Pages) {
+ if ((Alloc->HostAddress == HostAddress) && (Alloc->NumPages == Pages)) {
//
// We are freeing the exact allocation we were given
// before by AllocateBuffer()
@@ -968,7 +996,8 @@ NonCoherentPciIoFreeBuffer ( Status = gDS->SetMemorySpaceAttributes (
(EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress,
EFI_PAGES_TO_SIZE (Pages),
- Alloc->Attributes);
+ Alloc->Attributes
+ );
if (EFI_ERROR (Status)) {
goto FreeAlloc;
}
@@ -1007,36 +1036,43 @@ STATIC EFI_STATUS
EFIAPI
NonCoherentPciIoAllocateBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
- EFI_STATUS Status;
- UINT64 MemType;
- NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION *Alloc;
- VOID *AllocAddress;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
+ EFI_STATUS Status;
+ UINT64 MemType;
+ NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION *Alloc;
+ VOID *AllocAddress;
if (HostAddress == NULL) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
- Status = CoherentPciIoAllocateBuffer (This, Type, MemoryType, Pages,
- &AllocAddress, Attributes);
+ Status = CoherentPciIoAllocateBuffer (
+ This,
+ Type,
+ MemoryType,
+ Pages,
+ &AllocAddress,
+ Attributes
+ );
if (EFI_ERROR (Status)) {
return Status;
}
Status = gDS->GetMemorySpaceDescriptor (
(EFI_PHYSICAL_ADDRESS)(UINTN)AllocAddress,
- &GcdDescriptor);
+ &GcdDescriptor
+ );
if (EFI_ERROR (Status)) {
goto FreeBuffer;
}
@@ -1049,8 +1085,9 @@ NonCoherentPciIoAllocateBuffer ( //
// Set the preferred memory attributes
//
- if ((Attributes & EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE) != 0 ||
- (GcdDescriptor.Capabilities & EFI_MEMORY_UC) == 0) {
+ if (((Attributes & EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE) != 0) ||
+ ((GcdDescriptor.Capabilities & EFI_MEMORY_UC) == 0))
+ {
//
// Use write combining if it was requested, or if it is the only
// type supported by the region.
@@ -1066,8 +1103,8 @@ NonCoherentPciIoAllocateBuffer ( }
Alloc->HostAddress = AllocAddress;
- Alloc->NumPages = Pages;
- Alloc->Attributes = GcdDescriptor.Attributes;
+ Alloc->NumPages = Pages;
+ Alloc->Attributes = GcdDescriptor.Attributes;
//
// Record this allocation in the linked list, so we
@@ -1078,7 +1115,8 @@ NonCoherentPciIoAllocateBuffer ( Status = gDS->SetMemorySpaceAttributes (
(EFI_PHYSICAL_ADDRESS)(UINTN)AllocAddress,
EFI_PAGES_TO_SIZE (Pages),
- MemType);
+ MemType
+ );
if (EFI_ERROR (Status)) {
goto RemoveList;
}
@@ -1087,7 +1125,8 @@ NonCoherentPciIoAllocateBuffer ( mCpu,
(EFI_PHYSICAL_ADDRESS)(UINTN)AllocAddress,
EFI_PAGES_TO_SIZE (Pages),
- EfiCpuFlushTypeInvalidate);
+ EfiCpuFlushTypeInvalidate
+ );
if (EFI_ERROR (Status)) {
goto RemoveList;
}
@@ -1144,16 +1183,18 @@ NonCoherentPciIoMap ( EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
BOOLEAN Bounce;
- if (HostAddress == NULL ||
- NumberOfBytes == NULL ||
- DeviceAddress == NULL ||
- Mapping == NULL) {
+ if ((HostAddress == NULL) ||
+ (NumberOfBytes == NULL) ||
+ (DeviceAddress == NULL) ||
+ (Mapping == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
- if (Operation != EfiPciIoOperationBusMasterRead &&
- Operation != EfiPciIoOperationBusMasterWrite &&
- Operation != EfiPciIoOperationBusMasterCommonBuffer) {
+ if ((Operation != EfiPciIoOperationBusMasterRead) &&
+ (Operation != EfiPciIoOperationBusMasterWrite) &&
+ (Operation != EfiPciIoOperationBusMasterCommonBuffer))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1162,11 +1203,11 @@ NonCoherentPciIoMap ( return EFI_OUT_OF_RESOURCES;
}
- MapInfo->HostAddress = HostAddress;
- MapInfo->Operation = Operation;
+ MapInfo->HostAddress = HostAddress;
+ MapInfo->Operation = Operation;
MapInfo->NumberOfBytes = *NumberOfBytes;
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
//
// If this device does not support 64-bit DMA addressing, we need to allocate
@@ -1177,33 +1218,37 @@ NonCoherentPciIoMap ( if (!Bounce) {
switch (Operation) {
- case EfiPciIoOperationBusMasterRead:
- case EfiPciIoOperationBusMasterWrite:
- //
- // For streaming DMA, it is sufficient if the buffer is aligned to
- // the CPUs DMA buffer alignment.
- //
- AlignMask = mCpu->DmaBufferAlignment - 1;
- if ((((UINTN) HostAddress | *NumberOfBytes) & AlignMask) == 0) {
- break;
- }
+ case EfiPciIoOperationBusMasterRead:
+ case EfiPciIoOperationBusMasterWrite:
+ //
+ // For streaming DMA, it is sufficient if the buffer is aligned to
+ // the CPUs DMA buffer alignment.
+ //
+ AlignMask = mCpu->DmaBufferAlignment - 1;
+ if ((((UINTN)HostAddress | *NumberOfBytes) & AlignMask) == 0) {
+ break;
+ }
+
// fall through
- case EfiPciIoOperationBusMasterCommonBuffer:
- //
- // Check whether the host address refers to an uncached mapping.
- //
- Status = gDS->GetMemorySpaceDescriptor (
- (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress,
- &GcdDescriptor);
- if (EFI_ERROR (Status) ||
- (GcdDescriptor.Attributes & (EFI_MEMORY_WB|EFI_MEMORY_WT)) != 0) {
- Bounce = TRUE;
- }
- break;
+ case EfiPciIoOperationBusMasterCommonBuffer:
+ //
+ // Check whether the host address refers to an uncached mapping.
+ //
+ Status = gDS->GetMemorySpaceDescriptor (
+ (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress,
+ &GcdDescriptor
+ );
+ if (EFI_ERROR (Status) ||
+ ((GcdDescriptor.Attributes & (EFI_MEMORY_WB|EFI_MEMORY_WT)) != 0))
+ {
+ Bounce = TRUE;
+ }
- default:
- ASSERT (FALSE);
+ break;
+
+ default:
+ ASSERT (FALSE);
}
}
@@ -1213,20 +1258,27 @@ NonCoherentPciIoMap ( goto FreeMapInfo;
}
- Status = NonCoherentPciIoAllocateBuffer (This, AllocateAnyPages,
- EfiBootServicesData, EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes),
- &AllocAddress, EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE);
+ Status = NonCoherentPciIoAllocateBuffer (
+ This,
+ AllocateAnyPages,
+ EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes),
+ &AllocAddress,
+ EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE
+ );
if (EFI_ERROR (Status)) {
goto FreeMapInfo;
}
+
MapInfo->AllocAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocAddress;
if (Operation == EfiPciIoOperationBusMasterRead) {
gBS->CopyMem (AllocAddress, HostAddress, *NumberOfBytes);
}
+
*DeviceAddress = MapInfo->AllocAddress;
} else {
MapInfo->AllocAddress = 0;
- *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
+ *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
//
// We are not using a bounce buffer: the mapping is sufficiently
@@ -1238,8 +1290,12 @@ NonCoherentPciIoMap ( // may be written back unexpectedly, and clobber the data written to
// main memory by the device.
//
- mCpu->FlushDataCache (mCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress,
- *NumberOfBytes, EfiCpuFlushTypeWriteBack);
+ mCpu->FlushDataCache (
+ mCpu,
+ (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress,
+ *NumberOfBytes,
+ EfiCpuFlushTypeWriteBack
+ );
}
*Mapping = MapInfo;
@@ -1264,8 +1320,8 @@ STATIC EFI_STATUS
EFIAPI
NonCoherentPciIoUnmap (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN VOID *Mapping
)
{
NON_DISCOVERABLE_PCI_DEVICE_MAP_INFO *MapInfo;
@@ -1281,12 +1337,18 @@ NonCoherentPciIoUnmap ( // and free the buffer.
//
if (MapInfo->Operation == EfiPciIoOperationBusMasterWrite) {
- gBS->CopyMem (MapInfo->HostAddress, (VOID *)(UINTN)MapInfo->AllocAddress,
- MapInfo->NumberOfBytes);
+ gBS->CopyMem (
+ MapInfo->HostAddress,
+ (VOID *)(UINTN)MapInfo->AllocAddress,
+ MapInfo->NumberOfBytes
+ );
}
- NonCoherentPciIoFreeBuffer (This,
+
+ NonCoherentPciIoFreeBuffer (
+ This,
EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes),
- (VOID *)(UINTN)MapInfo->AllocAddress);
+ (VOID *)(UINTN)MapInfo->AllocAddress
+ );
} else {
//
// We are *not* using a bounce buffer: if this is a bus master write,
@@ -1294,11 +1356,15 @@ NonCoherentPciIoUnmap ( // data written by the device.
//
if (MapInfo->Operation == EfiPciIoOperationBusMasterWrite) {
- mCpu->FlushDataCache (mCpu,
+ mCpu->FlushDataCache (
+ mCpu,
(EFI_PHYSICAL_ADDRESS)(UINTN)MapInfo->HostAddress,
- MapInfo->NumberOfBytes, EfiCpuFlushTypeInvalidate);
+ MapInfo->NumberOfBytes,
+ EfiCpuFlushTypeInvalidate
+ );
}
}
+
FreePool (MapInfo);
return EFI_SUCCESS;
}
@@ -1313,7 +1379,7 @@ STATIC EFI_STATUS
EFIAPI
PciIoFlush (
- IN EFI_PCI_IO_PROTOCOL *This
+ IN EFI_PCI_IO_PROTOCOL *This
)
{
return EFI_SUCCESS;
@@ -1343,16 +1409,17 @@ PciIoGetLocation ( OUT UINTN *FunctionNumber
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
- if (SegmentNumber == NULL ||
- BusNumber == NULL ||
- DeviceNumber == NULL ||
- FunctionNumber == NULL) {
+ if ((SegmentNumber == NULL) ||
+ (BusNumber == NULL) ||
+ (DeviceNumber == NULL) ||
+ (FunctionNumber == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
*SegmentNumber = 0xff;
*BusNumber = Dev->UniqueId >> 5;
@@ -1391,10 +1458,10 @@ PciIoAttributes ( OUT UINT64 *Result OPTIONAL
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- BOOLEAN Enable;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ BOOLEAN Enable;
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
if ((Attributes & (~(DEV_SUPPORTED_ATTRIBUTES))) != 0) {
return EFI_UNSUPPORTED;
@@ -1402,43 +1469,46 @@ PciIoAttributes ( Enable = FALSE;
switch (Operation) {
- case EfiPciIoAttributeOperationGet:
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
- *Result = Dev->Attributes;
- break;
+ case EfiPciIoAttributeOperationGet:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
- case EfiPciIoAttributeOperationSupported:
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
- *Result = DEV_SUPPORTED_ATTRIBUTES;
- break;
+ *Result = Dev->Attributes;
+ break;
- case EfiPciIoAttributeOperationEnable:
- Attributes |= Dev->Attributes;
- case EfiPciIoAttributeOperationSet:
- Enable = ((~Dev->Attributes & Attributes) & EFI_PCI_DEVICE_ENABLE) != 0;
- Dev->Attributes = Attributes;
- break;
+ case EfiPciIoAttributeOperationSupported:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
- case EfiPciIoAttributeOperationDisable:
- Dev->Attributes &= ~Attributes;
- break;
+ *Result = DEV_SUPPORTED_ATTRIBUTES;
+ break;
- default:
- return EFI_INVALID_PARAMETER;
- };
+ case EfiPciIoAttributeOperationEnable:
+ Attributes |= Dev->Attributes;
+ case EfiPciIoAttributeOperationSet:
+ Enable = ((~Dev->Attributes & Attributes) & EFI_PCI_DEVICE_ENABLE) != 0;
+ Dev->Attributes = Attributes;
+ break;
+
+ case EfiPciIoAttributeOperationDisable:
+ Dev->Attributes &= ~Attributes;
+ break;
+
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
//
// If we're setting any of the EFI_PCI_DEVICE_ENABLE bits, perform
// the device specific initialization now.
//
- if (Enable && !Dev->Enabled && Dev->Device->Initialize != NULL) {
+ if (Enable && !Dev->Enabled && (Dev->Device->Initialize != NULL)) {
Dev->Device->Initialize (Dev->Device);
Dev->Enabled = TRUE;
}
+
return EFI_SUCCESS;
}
@@ -1468,23 +1538,23 @@ STATIC EFI_STATUS
EFIAPI
PciIoGetBarAttributes (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINT8 BarIndex,
- OUT UINT64 *Supports OPTIONAL,
- OUT VOID **Resources OPTIONAL
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports OPTIONAL,
+ OUT VOID **Resources OPTIONAL
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ EFI_STATUS Status;
- if (Supports == NULL && Resources == NULL) {
+ if ((Supports == NULL) && (Resources == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Status = GetBarResource (Dev, BarIndex, &BarDesc);
if (EFI_ERROR (Status)) {
@@ -1499,20 +1569,23 @@ PciIoGetBarAttributes ( }
if (Resources != NULL) {
- Descriptor = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
- sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
+ Descriptor = AllocatePool (
+ sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
+ sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
+ );
if (Descriptor == NULL) {
return EFI_OUT_OF_RESOURCES;
}
CopyMem (Descriptor, BarDesc, sizeof *Descriptor);
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);
End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0;
*Resources = Descriptor;
}
+
return EFI_SUCCESS;
}
@@ -1533,32 +1606,32 @@ STATIC EFI_STATUS
EFIAPI
PciIoSetBarAttributes (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINT64 Attributes,
- IN UINT8 BarIndex,
- IN OUT UINT64 *Offset,
- IN OUT UINT64 *Length
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
)
{
- NON_DISCOVERABLE_PCI_DEVICE *Dev;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- EFI_PCI_IO_PROTOCOL_WIDTH Width;
- UINTN Count;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_PCI_DEVICE *Dev;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ EFI_PCI_IO_PROTOCOL_WIDTH Width;
+ UINTN Count;
+ EFI_STATUS Status;
if ((Attributes & (~DEV_SUPPORTED_ATTRIBUTES)) != 0) {
return EFI_UNSUPPORTED;
}
- if (Offset == NULL || Length == NULL) {
+ if ((Offset == NULL) || (Length == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(This);
+ Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
Width = EfiPciIoWidthUint8;
- Count = (UINT32) *Length;
+ Count = (UINT32)*Length;
- Status = GetBarResource(Dev, BarIndex, &Desc);
+ Status = GetBarResource (Dev, BarIndex, &Desc);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1571,13 +1644,13 @@ PciIoSetBarAttributes ( return EFI_UNSUPPORTED;
}
-STATIC CONST EFI_PCI_IO_PROTOCOL PciIoTemplate =
+STATIC CONST EFI_PCI_IO_PROTOCOL PciIoTemplate =
{
PciIoPollMem,
PciIoPollIo,
- { PciIoMemRead, PciIoMemWrite },
- { PciIoIoRead, PciIoIoWrite },
- { PciIoPciRead, PciIoPciWrite },
+ { PciIoMemRead, PciIoMemWrite },
+ { PciIoIoRead, PciIoIoWrite },
+ { PciIoPciRead, PciIoPciWrite },
PciIoCopyMem,
CoherentPciIoMap,
CoherentPciIoUnmap,
@@ -1600,11 +1673,11 @@ STATIC CONST EFI_PCI_IO_PROTOCOL PciIoTemplate = **/
VOID
InitializePciIoProtocol (
- NON_DISCOVERABLE_PCI_DEVICE *Dev
+ NON_DISCOVERABLE_PCI_DEVICE *Dev
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
- INTN Idx;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
+ INTN Idx;
InitializeListHead (&Dev->UncachedAllocationList);
@@ -1612,62 +1685,83 @@ InitializePciIoProtocol ( Dev->ConfigSpace.Hdr.DeviceId = PCI_ID_DEVICE_DONTCARE;
// Copy protocol structure
- CopyMem(&Dev->PciIo, &PciIoTemplate, sizeof PciIoTemplate);
+ CopyMem (&Dev->PciIo, &PciIoTemplate, sizeof PciIoTemplate);
if (Dev->Device->DmaType == NonDiscoverableDeviceDmaTypeNonCoherent) {
- Dev->PciIo.AllocateBuffer = NonCoherentPciIoAllocateBuffer;
- Dev->PciIo.FreeBuffer = NonCoherentPciIoFreeBuffer;
- Dev->PciIo.Map = NonCoherentPciIoMap;
- Dev->PciIo.Unmap = NonCoherentPciIoUnmap;
+ Dev->PciIo.AllocateBuffer = NonCoherentPciIoAllocateBuffer;
+ Dev->PciIo.FreeBuffer = NonCoherentPciIoFreeBuffer;
+ Dev->PciIo.Map = NonCoherentPciIoMap;
+ Dev->PciIo.Unmap = NonCoherentPciIoUnmap;
}
if (CompareGuid (Dev->Device->Type, &gEdkiiNonDiscoverableAhciDeviceGuid)) {
Dev->ConfigSpace.Hdr.ClassCode[0] = PCI_IF_MASS_STORAGE_AHCI;
Dev->ConfigSpace.Hdr.ClassCode[1] = PCI_CLASS_MASS_STORAGE_SATADPA;
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_MASS_STORAGE;
- Dev->BarOffset = 5;
- } else if (CompareGuid (Dev->Device->Type,
- &gEdkiiNonDiscoverableEhciDeviceGuid)) {
+ Dev->BarOffset = 5;
+ } else if (CompareGuid (
+ Dev->Device->Type,
+ &gEdkiiNonDiscoverableEhciDeviceGuid
+ ))
+ {
Dev->ConfigSpace.Hdr.ClassCode[0] = PCI_IF_EHCI;
Dev->ConfigSpace.Hdr.ClassCode[1] = PCI_CLASS_SERIAL_USB;
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_SERIAL;
- Dev->BarOffset = 0;
- } else if (CompareGuid (Dev->Device->Type,
- &gEdkiiNonDiscoverableNvmeDeviceGuid)) {
+ Dev->BarOffset = 0;
+ } else if (CompareGuid (
+ Dev->Device->Type,
+ &gEdkiiNonDiscoverableNvmeDeviceGuid
+ ))
+ {
Dev->ConfigSpace.Hdr.ClassCode[0] = 0x2; // PCI_IF_NVMHCI
Dev->ConfigSpace.Hdr.ClassCode[1] = 0x8; // PCI_CLASS_MASS_STORAGE_NVM
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_MASS_STORAGE;
- Dev->BarOffset = 0;
- } else if (CompareGuid (Dev->Device->Type,
- &gEdkiiNonDiscoverableOhciDeviceGuid)) {
+ Dev->BarOffset = 0;
+ } else if (CompareGuid (
+ Dev->Device->Type,
+ &gEdkiiNonDiscoverableOhciDeviceGuid
+ ))
+ {
Dev->ConfigSpace.Hdr.ClassCode[0] = PCI_IF_OHCI;
Dev->ConfigSpace.Hdr.ClassCode[1] = PCI_CLASS_SERIAL_USB;
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_SERIAL;
- Dev->BarOffset = 0;
- } else if (CompareGuid (Dev->Device->Type,
- &gEdkiiNonDiscoverableSdhciDeviceGuid)) {
+ Dev->BarOffset = 0;
+ } else if (CompareGuid (
+ Dev->Device->Type,
+ &gEdkiiNonDiscoverableSdhciDeviceGuid
+ ))
+ {
Dev->ConfigSpace.Hdr.ClassCode[0] = 0x0; // don't care
Dev->ConfigSpace.Hdr.ClassCode[1] = PCI_SUBCLASS_SD_HOST_CONTROLLER;
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_SYSTEM_PERIPHERAL;
- Dev->BarOffset = 0;
- } else if (CompareGuid (Dev->Device->Type,
- &gEdkiiNonDiscoverableXhciDeviceGuid)) {
+ Dev->BarOffset = 0;
+ } else if (CompareGuid (
+ Dev->Device->Type,
+ &gEdkiiNonDiscoverableXhciDeviceGuid
+ ))
+ {
Dev->ConfigSpace.Hdr.ClassCode[0] = PCI_IF_XHCI;
Dev->ConfigSpace.Hdr.ClassCode[1] = PCI_CLASS_SERIAL_USB;
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_SERIAL;
- Dev->BarOffset = 0;
- } else if (CompareGuid (Dev->Device->Type,
- &gEdkiiNonDiscoverableUhciDeviceGuid)) {
+ Dev->BarOffset = 0;
+ } else if (CompareGuid (
+ Dev->Device->Type,
+ &gEdkiiNonDiscoverableUhciDeviceGuid
+ ))
+ {
Dev->ConfigSpace.Hdr.ClassCode[0] = PCI_IF_UHCI;
Dev->ConfigSpace.Hdr.ClassCode[1] = PCI_CLASS_SERIAL_USB;
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_SERIAL;
- Dev->BarOffset = 0;
- } else if (CompareGuid (Dev->Device->Type,
- &gEdkiiNonDiscoverableUfsDeviceGuid)) {
+ Dev->BarOffset = 0;
+ } else if (CompareGuid (
+ Dev->Device->Type,
+ &gEdkiiNonDiscoverableUfsDeviceGuid
+ ))
+ {
Dev->ConfigSpace.Hdr.ClassCode[0] = 0x0; // don't care
Dev->ConfigSpace.Hdr.ClassCode[1] = 0x9; // UFS controller subclass;
Dev->ConfigSpace.Hdr.ClassCode[2] = PCI_CLASS_MASS_STORAGE;
- Dev->BarOffset = 0;
+ Dev->BarOffset = 0;
} else {
ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
}
@@ -1678,16 +1772,19 @@ InitializePciIoProtocol ( Idx = Dev->BarOffset;
for (Desc = Dev->Device->Resources, Dev->BarCount = 0;
Desc->Desc != ACPI_END_TAG_DESCRIPTOR;
- Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3)) {
-
+ Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3))
+ {
ASSERT (Desc->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR);
ASSERT (Desc->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM);
- if (Idx >= PCI_MAX_BAR ||
- (Idx == PCI_MAX_BAR - 1 && Desc->AddrSpaceGranularity == 64)) {
- DEBUG ((DEBUG_ERROR,
+ if ((Idx >= PCI_MAX_BAR) ||
+ ((Idx == PCI_MAX_BAR - 1) && (Desc->AddrSpaceGranularity == 64)))
+ {
+ DEBUG ((
+ DEBUG_ERROR,
"%a: resource count exceeds number of emulated BARs\n",
- __FUNCTION__));
+ __FUNCTION__
+ ));
ASSERT (FALSE);
break;
}
@@ -1696,9 +1793,11 @@ InitializePciIoProtocol ( Dev->BarCount++;
if (Desc->AddrSpaceGranularity == 64) {
- Dev->ConfigSpace.Device.Bar[Idx] |= 0x4;
+ Dev->ConfigSpace.Device.Bar[Idx] |= 0x4;
Dev->ConfigSpace.Device.Bar[++Idx] = (UINT32)RShiftU64 (
- Desc->AddrRangeMin, 32);
+ Desc->AddrRangeMin,
+ 32
+ );
}
}
}
diff --git a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.h b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.h index 3e6df3bebd..41e591e80c 100644 --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.h +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.h @@ -24,7 +24,7 @@ #include <Protocol/Cpu.h>
#include <Protocol/PciIo.h>
-#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')
+#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')
#define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \
CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \
@@ -33,74 +33,74 @@ #define DEV_SUPPORTED_ATTRIBUTES \
(EFI_PCI_DEVICE_ENABLE | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE)
-#define PCI_ID_VENDOR_UNKNOWN 0xffff
-#define PCI_ID_DEVICE_DONTCARE 0x0000
+#define PCI_ID_VENDOR_UNKNOWN 0xffff
+#define PCI_ID_DEVICE_DONTCARE 0x0000
-extern EFI_CPU_ARCH_PROTOCOL *mCpu;
+extern EFI_CPU_ARCH_PROTOCOL *mCpu;
typedef struct {
//
// The linked-list next pointer
//
- LIST_ENTRY List;
+ LIST_ENTRY List;
//
// The address of the uncached allocation
//
- VOID *HostAddress;
+ VOID *HostAddress;
//
// The number of pages in the allocation
//
- UINTN NumPages;
+ UINTN NumPages;
//
// The attributes of the allocation
//
- UINT64 Attributes;
+ UINT64 Attributes;
} NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION;
typedef struct {
- UINT32 Signature;
+ UINT32 Signature;
//
// The bound non-discoverable device protocol instance
//
- NON_DISCOVERABLE_DEVICE *Device;
+ NON_DISCOVERABLE_DEVICE *Device;
//
// The exposed PCI I/O protocol instance.
//
- EFI_PCI_IO_PROTOCOL PciIo;
+ EFI_PCI_IO_PROTOCOL PciIo;
//
// The emulated PCI config space of the device. Only the minimally required
// items are assigned.
//
- PCI_TYPE00 ConfigSpace;
+ PCI_TYPE00 ConfigSpace;
//
// The first virtual BAR to assign based on the resources described
// by the non-discoverable device.
//
- UINT32 BarOffset;
+ UINT32 BarOffset;
//
// The number of virtual BARs we expose based on the number of
// resources
//
- UINT32 BarCount;
+ UINT32 BarCount;
//
// The PCI I/O attributes for this device
//
- UINT64 Attributes;
+ UINT64 Attributes;
//
// Whether this device has been enabled
//
- BOOLEAN Enabled;
+ BOOLEAN Enabled;
//
// Linked list to keep track of uncached allocations performed
// on behalf of this device
//
- LIST_ENTRY UncachedAllocationList;
+ LIST_ENTRY UncachedAllocationList;
//
// Unique ID for this device instance: needed so that we can report unique
// segment/bus/device number for each device instance. Note that this number
// may change when disconnecting/reconnecting the driver.
//
- UINTN UniqueId;
+ UINTN UniqueId;
} NON_DISCOVERABLE_PCI_DEVICE;
/**
@@ -111,10 +111,10 @@ typedef struct { **/
VOID
InitializePciIoProtocol (
- NON_DISCOVERABLE_PCI_DEVICE *Device
+ NON_DISCOVERABLE_PCI_DEVICE *Device
);
-extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;
+extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;
#endif
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/ComponentName.c index 7ef345eec4..a58646b433 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/ComponentName.c @@ -12,7 +12,7 @@ //
// EFI Component Name Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentName = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentName = {
NvmExpressComponentNameGetDriverName,
NvmExpressComponentNameGetControllerName,
"eng"
@@ -21,20 +21,20 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentNa //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gNvmExpressComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) NvmExpressComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) NvmExpressComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gNvmExpressComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)NvmExpressComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)NvmExpressComponentNameGetControllerName,
"en"
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressDriverNameTable[] = {
{ "eng;en", L"NVM Express Driver" },
- { NULL, NULL }
+ { NULL, NULL }
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressControllerNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressControllerNameTable[] = {
{ "eng;en", L"NVM Express Controller" },
- { NULL, NULL }
+ { NULL, NULL }
};
/**
@@ -79,9 +79,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mNvmExpressControllerName EFI_STATUS
EFIAPI
NvmExpressComponentNameGetDriverName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN CHAR8 *Language,
- OUT CHAR16 **DriverName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -164,17 +164,17 @@ NvmExpressComponentNameGetDriverName ( EFI_STATUS
EFIAPI
NvmExpressComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
- EFI_BLOCK_IO_PROTOCOL *BlockIo;
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_UNICODE_STRING_TABLE *ControllerNameTable;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_PROTOCOL *BlockIo;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// Make sure this driver is currently managing ControllHandle
@@ -198,13 +198,14 @@ NvmExpressComponentNameGetControllerName ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Get the child context
//
Status = gBS->OpenProtocol (
ChildHandle,
&gEfiBlockIoProtocolGuid,
- (VOID **) &BlockIo,
+ (VOID **)&BlockIo,
gNvmExpressDriverBinding.DriverBindingHandle,
ChildHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -212,7 +213,8 @@ NvmExpressComponentNameGetControllerName ( if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
- Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
+
+ Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
ControllerNameTable = Device->ControllerNameTable;
}
@@ -223,5 +225,4 @@ NvmExpressComponentNameGetControllerName ( ControllerName,
(BOOLEAN)(This == &gNvmExpressComponentName)
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c index f60c2fcd79..9d40f67e8e 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c @@ -12,7 +12,7 @@ //
// NVM Express Driver Binding Protocol Instance
//
-EFI_DRIVER_BINDING_PROTOCOL gNvmExpressDriverBinding = {
+EFI_DRIVER_BINDING_PROTOCOL gNvmExpressDriverBinding = {
NvmExpressDriverBindingSupported,
NvmExpressDriverBindingStart,
NvmExpressDriverBindingStop,
@@ -24,7 +24,7 @@ EFI_DRIVER_BINDING_PROTOCOL gNvmExpressDriverBinding = { //
// NVM Express EFI Driver Supported EFI Version Protocol Instance
//
-EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion = {
+EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion = {
sizeof (EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL), // Size of Protocol structure.
0 // Version number to be filled at start up.
};
@@ -32,7 +32,7 @@ EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion = //
// Template for NVM Express Pass Thru Mode data structure.
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_NVM_EXPRESS_PASS_THRU_MODE gEfiNvmExpressPassThruMode = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_NVM_EXPRESS_PASS_THRU_MODE gEfiNvmExpressPassThruMode = {
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL |
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO |
@@ -56,24 +56,24 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_NVM_EXPRESS_PASS_THRU_MODE gEfiNvmExpressPassT **/
EFI_STATUS
EnumerateNvmeDevNamespace (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- UINT32 NamespaceId
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ UINT32 NamespaceId
)
{
- NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
- EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- EFI_HANDLE DeviceHandle;
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STATUS Status;
- UINT32 Lbads;
- UINT32 Flbas;
- UINT32 LbaFmtIdx;
- UINT8 Sn[21];
- UINT8 Mn[41];
- VOID *DummyInterface;
+ NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
+ EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_HANDLE DeviceHandle;
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ UINT32 Lbads;
+ UINT32 Flbas;
+ UINT32 LbaFmtIdx;
+ UINT8 Sn[21];
+ UINT8 Mn[41];
+ VOID *DummyInterface;
NewDevicePathNode = NULL;
DevicePath = NULL;
@@ -82,8 +82,8 @@ EnumerateNvmeDevNamespace ( //
// Allocate a buffer for Identify Namespace data
//
- NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
- if(NamespaceData == NULL) {
+ NamespaceData = AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
+ if (NamespaceData == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -96,9 +96,10 @@ EnumerateNvmeDevNamespace ( NamespaceId,
(VOID *)NamespaceData
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto Exit;
}
+
//
// Validate Namespace
//
@@ -108,7 +109,7 @@ EnumerateNvmeDevNamespace ( //
// allocate device private data for each discovered namespace
//
- Device = AllocateZeroPool(sizeof(NVME_DEVICE_PRIVATE_DATA));
+ Device = AllocateZeroPool (sizeof (NVME_DEVICE_PRIVATE_DATA));
if (Device == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
@@ -117,9 +118,9 @@ EnumerateNvmeDevNamespace ( //
// Initialize SSD namespace instance data
//
- Device->Signature = NVME_DEVICE_PRIVATE_DATA_SIGNATURE;
- Device->NamespaceId = NamespaceId;
- Device->NamespaceUuid = NamespaceData->Eui64;
+ Device->Signature = NVME_DEVICE_PRIVATE_DATA_SIGNATURE;
+ Device->NamespaceId = NamespaceId;
+ Device->NamespaceUuid = NamespaceData->Eui64;
Device->ControllerHandle = Private->ControllerHandle;
Device->DriverBindingHandle = Private->DriverBindingHandle;
@@ -128,17 +129,17 @@ EnumerateNvmeDevNamespace ( //
// Build BlockIo media structure
//
- Device->Media.MediaId = 0;
- Device->Media.RemovableMedia = FALSE;
- Device->Media.MediaPresent = TRUE;
+ Device->Media.MediaId = 0;
+ Device->Media.RemovableMedia = FALSE;
+ Device->Media.MediaPresent = TRUE;
Device->Media.LogicalPartition = FALSE;
- Device->Media.ReadOnly = FALSE;
- Device->Media.WriteCaching = FALSE;
- Device->Media.IoAlign = Private->PassThruMode.IoAlign;
+ Device->Media.ReadOnly = FALSE;
+ Device->Media.WriteCaching = FALSE;
+ Device->Media.IoAlign = Private->PassThruMode.IoAlign;
- Flbas = NamespaceData->Flbas;
- LbaFmtIdx = Flbas & 0xF;
- Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
+ Flbas = NamespaceData->Flbas;
+ LbaFmtIdx = Flbas & 0xF;
+ Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
Device->Media.BlockSize = (UINT32)1 << Lbads;
Device->Media.LastBlock = NamespaceData->Nsze - 1;
@@ -148,21 +149,21 @@ EnumerateNvmeDevNamespace ( //
// Create BlockIo Protocol instance
//
- Device->BlockIo.Revision = EFI_BLOCK_IO_PROTOCOL_REVISION2;
- Device->BlockIo.Media = &Device->Media;
- Device->BlockIo.Reset = NvmeBlockIoReset;
- Device->BlockIo.ReadBlocks = NvmeBlockIoReadBlocks;
- Device->BlockIo.WriteBlocks = NvmeBlockIoWriteBlocks;
- Device->BlockIo.FlushBlocks = NvmeBlockIoFlushBlocks;
+ Device->BlockIo.Revision = EFI_BLOCK_IO_PROTOCOL_REVISION2;
+ Device->BlockIo.Media = &Device->Media;
+ Device->BlockIo.Reset = NvmeBlockIoReset;
+ Device->BlockIo.ReadBlocks = NvmeBlockIoReadBlocks;
+ Device->BlockIo.WriteBlocks = NvmeBlockIoWriteBlocks;
+ Device->BlockIo.FlushBlocks = NvmeBlockIoFlushBlocks;
//
// Create BlockIo2 Protocol instance
//
- Device->BlockIo2.Media = &Device->Media;
- Device->BlockIo2.Reset = NvmeBlockIoResetEx;
- Device->BlockIo2.ReadBlocksEx = NvmeBlockIoReadBlocksEx;
- Device->BlockIo2.WriteBlocksEx = NvmeBlockIoWriteBlocksEx;
- Device->BlockIo2.FlushBlocksEx = NvmeBlockIoFlushBlocksEx;
+ Device->BlockIo2.Media = &Device->Media;
+ Device->BlockIo2.Reset = NvmeBlockIoResetEx;
+ Device->BlockIo2.ReadBlocksEx = NvmeBlockIoReadBlocksEx;
+ Device->BlockIo2.WriteBlocksEx = NvmeBlockIoWriteBlocksEx;
+ Device->BlockIo2.FlushBlocksEx = NvmeBlockIoFlushBlocksEx;
InitializeListHead (&Device->AsyncQueue);
//
@@ -186,7 +187,7 @@ EnumerateNvmeDevNamespace ( &NewDevicePathNode
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -199,10 +200,10 @@ EnumerateNvmeDevNamespace ( goto Exit;
}
- DeviceHandle = NULL;
+ DeviceHandle = NULL;
RemainingDevicePath = DevicePath;
- Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &RemainingDevicePath, &DeviceHandle);
- if (!EFI_ERROR (Status) && (DeviceHandle != NULL) && IsDevicePathEnd(RemainingDevicePath)) {
+ Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &RemainingDevicePath, &DeviceHandle);
+ if (!EFI_ERROR (Status) && (DeviceHandle != NULL) && IsDevicePathEnd (RemainingDevicePath)) {
Status = EFI_ALREADY_STARTED;
FreePool (DevicePath);
goto Exit;
@@ -228,7 +229,7 @@ EnumerateNvmeDevNamespace ( NULL
);
- if(EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -242,7 +243,7 @@ EnumerateNvmeDevNamespace ( EFI_NATIVE_INTERFACE,
&Device->StorageSecurity
);
- if(EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
gBS->UninstallMultipleProtocolInterfaces (
Device->DeviceHandle,
&gEfiDevicePathProtocolGuid,
@@ -262,7 +263,7 @@ EnumerateNvmeDevNamespace ( gBS->OpenProtocol (
Private->ControllerHandle,
&gEfiNvmExpressPassThruProtocolGuid,
- (VOID **) &DummyInterface,
+ (VOID **)&DummyInterface,
Private->DriverBindingHandle,
Device->DeviceHandle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -304,7 +305,7 @@ EnumerateNvmeDevNamespace ( }
Exit:
- if(NamespaceData != NULL) {
+ if (NamespaceData != NULL) {
FreePool (NamespaceData);
}
@@ -312,12 +313,14 @@ Exit: FreePool (NewDevicePathNode);
}
- if(EFI_ERROR(Status) && (Device != NULL) && (Device->DevicePath != NULL)) {
+ if (EFI_ERROR (Status) && (Device != NULL) && (Device->DevicePath != NULL)) {
FreePool (Device->DevicePath);
}
- if(EFI_ERROR(Status) && (Device != NULL)) {
+
+ if (EFI_ERROR (Status) && (Device != NULL)) {
FreePool (Device);
}
+
return Status;
}
@@ -333,15 +336,15 @@ Exit: **/
EFI_STATUS
DiscoverAllNamespaces (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_STATUS Status;
- UINT32 NamespaceId;
- EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *Passthru;
+ EFI_STATUS Status;
+ UINT32 NamespaceId;
+ EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *Passthru;
- NamespaceId = 0xFFFFFFFF;
- Passthru = &Private->Passthru;
+ NamespaceId = 0xFFFFFFFF;
+ Passthru = &Private->Passthru;
while (TRUE) {
Status = Passthru->GetNextNamespace (
@@ -358,7 +361,7 @@ DiscoverAllNamespaces ( NamespaceId
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
continue;
}
}
@@ -382,25 +385,25 @@ DiscoverAllNamespaces ( **/
EFI_STATUS
UnregisterNvmeNamespace (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_HANDLE Handle
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_HANDLE Handle
)
{
- EFI_STATUS Status;
- EFI_BLOCK_IO_PROTOCOL *BlockIo;
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *StorageSecurity;
- BOOLEAN IsEmpty;
- EFI_TPL OldTpl;
- VOID *DummyInterface;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_PROTOCOL *BlockIo;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *StorageSecurity;
+ BOOLEAN IsEmpty;
+ EFI_TPL OldTpl;
+ VOID *DummyInterface;
BlockIo = NULL;
Status = gBS->OpenProtocol (
Handle,
&gEfiBlockIoProtocolGuid,
- (VOID **) &BlockIo,
+ (VOID **)&BlockIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -409,7 +412,7 @@ UnregisterNvmeNamespace ( return Status;
}
- Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
+ Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (BlockIo);
//
// Wait for the device's asynchronous I/O queue to become empty.
@@ -457,7 +460,7 @@ UnregisterNvmeNamespace ( gBS->OpenProtocol (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
- (VOID **) &DummyInterface,
+ (VOID **)&DummyInterface,
This->DriverBindingHandle,
Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -471,7 +474,7 @@ UnregisterNvmeNamespace ( Status = gBS->OpenProtocol (
Handle,
&gEfiStorageSecurityCommandProtocolGuid,
- (VOID **) &StorageSecurity,
+ (VOID **)&StorageSecurity,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -485,18 +488,18 @@ UnregisterNvmeNamespace ( );
if (EFI_ERROR (Status)) {
gBS->OpenProtocol (
- Controller,
- &gEfiNvmExpressPassThruProtocolGuid,
- (VOID **) &DummyInterface,
- This->DriverBindingHandle,
- Handle,
- EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
- );
+ Controller,
+ &gEfiNvmExpressPassThruProtocolGuid,
+ (VOID **)&DummyInterface,
+ This->DriverBindingHandle,
+ Handle,
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
+ );
return Status;
}
}
- if(Device->DevicePath != NULL) {
+ if (Device->DevicePath != NULL) {
FreePool (Device->DevicePath);
}
@@ -520,25 +523,25 @@ UnregisterNvmeNamespace ( VOID
EFIAPI
ProcessAsyncTaskList (
- IN EFI_EVENT Event,
- IN VOID* Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_PCI_IO_PROTOCOL *PciIo;
- NVME_CQ *Cq;
- UINT16 QueueId;
- UINT32 Data;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
- NVME_BLKIO2_SUBTASK *Subtask;
- NVME_BLKIO2_REQUEST *BlkIo2Request;
- EFI_BLOCK_IO2_TOKEN *Token;
- BOOLEAN HasNewItem;
- EFI_STATUS Status;
-
- Private = (NVME_CONTROLLER_PRIVATE_DATA*)Context;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ NVME_CQ *Cq;
+ UINT16 QueueId;
+ UINT32 Data;
+ LIST_ENTRY *Link;
+ LIST_ENTRY *NextLink;
+ NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
+ NVME_BLKIO2_SUBTASK *Subtask;
+ NVME_BLKIO2_REQUEST *BlkIo2Request;
+ EFI_BLOCK_IO2_TOKEN *Token;
+ BOOLEAN HasNewItem;
+ EFI_STATUS Status;
+
+ Private = (NVME_CONTROLLER_PRIVATE_DATA *)Context;
QueueId = 2;
Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
HasNewItem = FALSE;
@@ -549,7 +552,8 @@ ProcessAsyncTaskList ( //
for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);
!IsNull (&Private->UnsubmittedSubtasks, Link);
- Link = NextLink) {
+ Link = NextLink)
+ {
NextLink = GetNextNode (&Private->UnsubmittedSubtasks, Link);
Subtask = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);
BlkIo2Request = Subtask->BlockIo2Request;
@@ -563,7 +567,8 @@ ProcessAsyncTaskList ( if (Token->TransactionStatus != EFI_SUCCESS) {
if (IsListEmpty (&BlkIo2Request->SubtasksQueue) &&
BlkIo2Request->LastSubtaskSubmitted &&
- (BlkIo2Request->UnsubmittedSubtaskNum == 0)) {
+ (BlkIo2Request->UnsubmittedSubtaskNum == 0))
+ {
//
// Remove the BlockIo2 request from the device asynchronous queue.
//
@@ -594,7 +599,8 @@ ProcessAsyncTaskList ( Token->TransactionStatus = EFI_DEVICE_ERROR;
if (IsListEmpty (&BlkIo2Request->SubtasksQueue) &&
- Subtask->IsLast) {
+ Subtask->IsLast)
+ {
//
// Remove the BlockIo2 request from the device asynchronous queue.
//
@@ -625,8 +631,9 @@ ProcessAsyncTaskList ( //
for (Link = GetFirstNode (&Private->AsyncPassThruQueue);
!IsNull (&Private->AsyncPassThruQueue, Link);
- Link = NextLink) {
- NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
+ Link = NextLink)
+ {
+ NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);
if (AsyncRequest->CommandId == Cq->Cid) {
//
@@ -636,7 +643,7 @@ ProcessAsyncTaskList ( CopyMem (
AsyncRequest->Packet->NvmeCompletion,
Cq,
- sizeof(EFI_NVM_EXPRESS_COMPLETION)
+ sizeof (EFI_NVM_EXPRESS_COMPLETION)
);
//
@@ -645,12 +652,15 @@ ProcessAsyncTaskList ( if (AsyncRequest->MapData != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapData);
}
+
if (AsyncRequest->MapMeta != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapMeta);
}
+
if (AsyncRequest->MapPrpList != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);
}
+
if (AsyncRequest->PrpListHost != NULL) {
PciIo->FreeBuffer (
PciIo,
@@ -674,19 +684,19 @@ ProcessAsyncTaskList ( Private->CqHdbl[QueueId].Cqh++;
if (Private->CqHdbl[QueueId].Cqh > MIN (NVME_ASYNC_CCQ_SIZE, Private->Cap.Mqes)) {
Private->CqHdbl[QueueId].Cqh = 0;
- Private->Pt[QueueId] ^= 1;
+ Private->Pt[QueueId] ^= 1;
}
Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
}
if (HasNewItem) {
- Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
+ Data = ReadUnaligned32 ((UINT32 *)&Private->CqHdbl[QueueId]);
PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,
- NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
+ NVME_CQHDBL_OFFSET (QueueId, Private->Cap.Dstrd),
1,
&Data
);
@@ -766,8 +776,9 @@ NvmExpressDriverBindingSupported ( if ((DevicePathNode.DevPath->Type != MESSAGING_DEVICE_PATH) ||
(DevicePathNode.DevPath->SubType != MSG_NVME_NAMESPACE_DP) ||
- (DevicePathNodeLength(DevicePathNode.DevPath) != sizeof(NVME_NAMESPACE_DEVICE_PATH))) {
- return EFI_UNSUPPORTED;
+ (DevicePathNodeLength (DevicePathNode.DevPath) != sizeof (NVME_NAMESPACE_DEVICE_PATH)))
+ {
+ return EFI_UNSUPPORTED;
}
}
}
@@ -778,7 +789,7 @@ NvmExpressDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID **) &ParentDevicePath,
+ (VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -807,7 +818,7 @@ NvmExpressDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -853,7 +864,6 @@ Done: return Status;
}
-
/**
Starts a device controller or a bus controller.
@@ -915,7 +925,7 @@ NvmExpressDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID **) &ParentDevicePath,
+ (VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -927,7 +937,7 @@ NvmExpressDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -965,14 +975,14 @@ NvmExpressDriverBindingStart ( AllocateAnyPages,
EfiBootServicesData,
6,
- (VOID**)&Private->Buffer,
+ (VOID **)&Private->Buffer,
0
);
if (EFI_ERROR (Status)) {
goto Exit;
}
- Bytes = EFI_PAGES_TO_SIZE (6);
+ Bytes = EFI_PAGES_TO_SIZE (6);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -988,7 +998,7 @@ NvmExpressDriverBindingStart ( Private->BufferPciAddr = (UINT8 *)(UINTN)MappedAddr;
- Private->Signature = NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE;
+ Private->Signature = NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE;
Private->ControllerHandle = Controller;
Private->ImageHandle = This->DriverBindingHandle;
Private->DriverBindingHandle = This->DriverBindingHandle;
@@ -1004,7 +1014,7 @@ NvmExpressDriverBindingStart ( InitializeListHead (&Private->UnsubmittedSubtasks);
Status = NvmeControllerInit (Private);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -1046,7 +1056,7 @@ NvmExpressDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
- (VOID **) &Passthru,
+ (VOID **)&Passthru,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1065,7 +1075,6 @@ NvmExpressDriverBindingStart ( Status = DiscoverAllNamespaces (
Private
);
-
} else if (!IsDevicePathEnd (RemainingDevicePath)) {
//
// Enumerate the specified NVME namespace
@@ -1127,7 +1136,6 @@ Exit: return Status;
}
-
/**
Stops a device controller or a bus controller.
@@ -1157,10 +1165,10 @@ Exit: EFI_STATUS
EFIAPI
NvmExpressDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -1175,7 +1183,7 @@ NvmExpressDriverBindingStop ( Status = gBS->OpenProtocol (
Controller,
&gEfiNvmExpressPassThruProtocolGuid,
- (VOID **) &PassThru,
+ (VOID **)&PassThru,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1201,11 +1209,11 @@ NvmExpressDriverBindingStop ( }
gBS->UninstallMultipleProtocolInterfaces (
- Controller,
- &gEfiNvmExpressPassThruProtocolGuid,
- PassThru,
- NULL
- );
+ Controller,
+ &gEfiNvmExpressPassThruProtocolGuid,
+ PassThru,
+ NULL
+ );
if (Private->TimerEvent != NULL) {
gBS->CloseEvent (Private->TimerEvent);
@@ -1224,17 +1232,17 @@ NvmExpressDriverBindingStop ( }
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
gBS->CloseProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
NvmeUnregisterShutdownNotification ();
@@ -1272,15 +1280,15 @@ NvmExpressDriverBindingStop ( EFI_STATUS
EFIAPI
NvmExpressUnload (
- IN EFI_HANDLE ImageHandle
+ IN EFI_HANDLE ImageHandle
)
{
- EFI_STATUS Status;
- EFI_HANDLE *DeviceHandleBuffer;
- UINTN DeviceHandleCount;
- UINTN Index;
- EFI_COMPONENT_NAME_PROTOCOL *ComponentName;
- EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2;
+ EFI_STATUS Status;
+ EFI_HANDLE *DeviceHandleBuffer;
+ UINTN DeviceHandleCount;
+ UINTN Index;
+ EFI_COMPONENT_NAME_PROTOCOL *ComponentName;
+ EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2;
//
// Get the list of the device handles managed by this driver.
@@ -1289,13 +1297,13 @@ NvmExpressUnload ( // those protocols installed at image handle.
//
DeviceHandleBuffer = NULL;
- Status = gBS->LocateHandleBuffer (
- ByProtocol,
- &gEfiNvmExpressPassThruProtocolGuid,
- NULL,
- &DeviceHandleCount,
- &DeviceHandleBuffer
- );
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiNvmExpressPassThruProtocolGuid,
+ NULL,
+ &DeviceHandleCount,
+ &DeviceHandleBuffer
+ );
if (!EFI_ERROR (Status)) {
//
@@ -1342,7 +1350,7 @@ NvmExpressUnload ( Status = gBS->HandleProtocol (
ImageHandle,
&gEfiComponentNameProtocolGuid,
- (VOID **) &ComponentName
+ (VOID **)&ComponentName
);
if (!EFI_ERROR (Status)) {
gBS->UninstallProtocolInterface (
@@ -1355,7 +1363,7 @@ NvmExpressUnload ( Status = gBS->HandleProtocol (
ImageHandle,
&gEfiComponentName2ProtocolGuid,
- (VOID **) &ComponentName2
+ (VOID **)&ComponentName2
);
if (!EFI_ERROR (Status)) {
gBS->UninstallProtocolInterface (
@@ -1374,6 +1382,7 @@ EXIT: if (DeviceHandleBuffer != NULL) {
gBS->FreePool (DeviceHandleBuffer);
}
+
return Status;
}
@@ -1394,7 +1403,7 @@ NvmExpressDriverEntry ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EfiLibInstallDriverBindingComponentName2 (
ImageHandle,
@@ -1411,12 +1420,12 @@ NvmExpressDriverEntry ( // EFI drivers that are on PCI and other plug in cards.
//
gNvmExpressDriverSupportedEfiVersion.FirmwareVersion = 0x00020028;
- Status = gBS->InstallMultipleProtocolInterfaces (
- &ImageHandle,
- &gEfiDriverSupportedEfiVersionProtocolGuid,
- &gNvmExpressDriverSupportedEfiVersion,
- NULL
- );
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gEfiDriverSupportedEfiVersionProtocolGuid,
+ &gNvmExpressDriverSupportedEfiVersion,
+ NULL
+ );
ASSERT_EFI_ERROR (Status);
return Status;
}
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h index 45a1447500..4c26b2e1b4 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h @@ -41,8 +41,8 @@ #include <Library/UefiDriverEntryPoint.h>
#include <Library/ReportStatusCodeLib.h>
-typedef struct _NVME_CONTROLLER_PRIVATE_DATA NVME_CONTROLLER_PRIVATE_DATA;
-typedef struct _NVME_DEVICE_PRIVATE_DATA NVME_DEVICE_PRIVATE_DATA;
+typedef struct _NVME_CONTROLLER_PRIVATE_DATA NVME_CONTROLLER_PRIVATE_DATA;
+typedef struct _NVME_DEVICE_PRIVATE_DATA NVME_DEVICE_PRIVATE_DATA;
#include "NvmExpressBlockIo.h"
#include "NvmExpressDiskInfo.h"
@@ -53,67 +53,67 @@ extern EFI_COMPONENT_NAME_PROTOCOL gNvmExpressComponentName; extern EFI_COMPONENT_NAME2_PROTOCOL gNvmExpressComponentName2;
extern EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiVersion;
-#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
-#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
+#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
+#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
-#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
-#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
+#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
+#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
-#define NVME_CSQ_SIZE 1 // Number of I/O submission queue entries, which is 0-based
-#define NVME_CCQ_SIZE 1 // Number of I/O completion queue entries, which is 0-based
+#define NVME_CSQ_SIZE 1 // Number of I/O submission queue entries, which is 0-based
+#define NVME_CCQ_SIZE 1 // Number of I/O completion queue entries, which is 0-based
//
// Number of asynchronous I/O submission queue entries, which is 0-based.
// The asynchronous I/O submission queue size is 4kB in total.
//
-#define NVME_ASYNC_CSQ_SIZE 63
+#define NVME_ASYNC_CSQ_SIZE 63
//
// Number of asynchronous I/O completion queue entries, which is 0-based.
// The asynchronous I/O completion queue size is 4kB in total.
//
-#define NVME_ASYNC_CCQ_SIZE 255
+#define NVME_ASYNC_CCQ_SIZE 255
-#define NVME_MAX_QUEUES 3 // Number of queues supported by the driver
+#define NVME_MAX_QUEUES 3 // Number of queues supported by the driver
-#define NVME_CONTROLLER_ID 0
+#define NVME_CONTROLLER_ID 0
//
// Time out value for Nvme transaction execution
//
-#define NVME_GENERIC_TIMEOUT EFI_TIMER_PERIOD_SECONDS (5)
+#define NVME_GENERIC_TIMEOUT EFI_TIMER_PERIOD_SECONDS (5)
//
// Nvme async transfer timer interval, set by experience.
//
-#define NVME_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS (1)
+#define NVME_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS (1)
//
// Unique signature for private data structure.
//
-#define NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','M','E')
+#define NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','M','E')
//
// Nvme private data structure.
//
struct _NVME_CONTROLLER_PRIVATE_DATA {
- UINT32 Signature;
+ UINT32 Signature;
- EFI_HANDLE ControllerHandle;
- EFI_HANDLE ImageHandle;
- EFI_HANDLE DriverBindingHandle;
+ EFI_HANDLE ControllerHandle;
+ EFI_HANDLE ImageHandle;
+ EFI_HANDLE DriverBindingHandle;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 PciAttributes;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 PciAttributes;
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
- EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL Passthru;
+ EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
+ EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL Passthru;
//
// pointer to identify controller data
//
- NVME_ADMIN_CONTROLLER_DATA *ControllerData;
+ NVME_ADMIN_CONTROLLER_DATA *ControllerData;
//
// 6 x 4kB aligned buffers will be carved out of this buffer.
@@ -124,45 +124,45 @@ struct _NVME_CONTROLLER_PRIVATE_DATA { // 5th 4kB boundary is the start of I/O submission queue #2.
// 6th 4kB boundary is the start of I/O completion queue #2.
//
- UINT8 *Buffer;
- UINT8 *BufferPciAddr;
+ UINT8 *Buffer;
+ UINT8 *BufferPciAddr;
//
// Pointers to 4kB aligned submission & completion queues.
//
- NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
- NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
- NVME_SQ *SqBufferPciAddr[NVME_MAX_QUEUES];
- NVME_CQ *CqBufferPciAddr[NVME_MAX_QUEUES];
+ NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
+ NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
+ NVME_SQ *SqBufferPciAddr[NVME_MAX_QUEUES];
+ NVME_CQ *CqBufferPciAddr[NVME_MAX_QUEUES];
//
// Submission and completion queue indices.
//
- NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
- NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
- UINT16 AsyncSqHead;
+ NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
+ NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
+ UINT16 AsyncSqHead;
//
// Flag to indicate internal IO queue creation.
//
- BOOLEAN CreateIoQueue;
+ BOOLEAN CreateIoQueue;
- UINT8 Pt[NVME_MAX_QUEUES];
- UINT16 Cid[NVME_MAX_QUEUES];
+ UINT8 Pt[NVME_MAX_QUEUES];
+ UINT16 Cid[NVME_MAX_QUEUES];
//
// Nvme controller capabilities
//
- NVME_CAP Cap;
+ NVME_CAP Cap;
- VOID *Mapping;
+ VOID *Mapping;
//
// For Non-blocking operations.
//
- EFI_EVENT TimerEvent;
- LIST_ENTRY AsyncPassThruQueue;
- LIST_ENTRY UnsubmittedSubtasks;
+ EFI_EVENT TimerEvent;
+ LIST_ENTRY AsyncPassThruQueue;
+ LIST_ENTRY UnsubmittedSubtasks;
};
#define NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU(a) \
@@ -175,7 +175,7 @@ struct _NVME_CONTROLLER_PRIVATE_DATA { //
// Unique signature for private data structure.
//
-#define NVME_DEVICE_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('X','S','S','D')
+#define NVME_DEVICE_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('X','S','S','D')
//
// Nvme device private data structure
@@ -208,7 +208,6 @@ struct _NVME_DEVICE_PRIVATE_DATA { NVME_ADMIN_NAMESPACE_DATA NamespaceData;
NVME_CONTROLLER_PRIVATE_DATA *Controller;
-
};
//
@@ -235,7 +234,7 @@ struct _NVME_DEVICE_PRIVATE_DATA { NVME_DEVICE_PRIVATE_DATA_SIGNATURE \
)
-#define NVME_DEVICE_PRIVATE_DATA_FROM_STORAGE_SECURITY(a)\
+#define NVME_DEVICE_PRIVATE_DATA_FROM_STORAGE_SECURITY(a) \
CR (a, \
NVME_DEVICE_PRIVATE_DATA, \
StorageSecurity, \
@@ -245,38 +244,38 @@ struct _NVME_DEVICE_PRIVATE_DATA { //
// Nvme block I/O 2 request.
//
-#define NVME_BLKIO2_REQUEST_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'R')
+#define NVME_BLKIO2_REQUEST_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'R')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
+ UINT32 Signature;
+ LIST_ENTRY Link;
- EFI_BLOCK_IO2_TOKEN *Token;
- UINTN UnsubmittedSubtaskNum;
- BOOLEAN LastSubtaskSubmitted;
+ EFI_BLOCK_IO2_TOKEN *Token;
+ UINTN UnsubmittedSubtaskNum;
+ BOOLEAN LastSubtaskSubmitted;
//
// The queue for Nvme read/write sub-tasks of a BlockIo2 request.
//
- LIST_ENTRY SubtasksQueue;
+ LIST_ENTRY SubtasksQueue;
} NVME_BLKIO2_REQUEST;
#define NVME_BLKIO2_REQUEST_FROM_LINK(a) \
CR (a, NVME_BLKIO2_REQUEST, Link, NVME_BLKIO2_REQUEST_SIGNATURE)
-#define NVME_BLKIO2_SUBTASK_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'S')
+#define NVME_BLKIO2_SUBTASK_SIGNATURE SIGNATURE_32 ('N', 'B', '2', 'S')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
+ UINT32 Signature;
+ LIST_ENTRY Link;
- BOOLEAN IsLast;
- UINT32 NamespaceId;
- EFI_EVENT Event;
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
+ BOOLEAN IsLast;
+ UINT32 NamespaceId;
+ EFI_EVENT Event;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
//
// The BlockIo2 request this subtask belongs to
//
- NVME_BLKIO2_REQUEST *BlockIo2Request;
+ NVME_BLKIO2_REQUEST *BlockIo2Request;
} NVME_BLKIO2_SUBTASK;
#define NVME_BLKIO2_SUBTASK_FROM_LINK(a) \
@@ -285,20 +284,20 @@ typedef struct { //
// Nvme asynchronous passthru request.
//
-#define NVME_PASS_THRU_ASYNC_REQ_SIG SIGNATURE_32 ('N', 'P', 'A', 'R')
+#define NVME_PASS_THRU_ASYNC_REQ_SIG SIGNATURE_32 ('N', 'P', 'A', 'R')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
-
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet;
- UINT16 CommandId;
- VOID *MapPrpList;
- UINTN PrpListNo;
- VOID *PrpListHost;
- VOID *MapData;
- VOID *MapMeta;
- EFI_EVENT CallerEvent;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet;
+ UINT16 CommandId;
+ VOID *MapPrpList;
+ UINTN PrpListNo;
+ VOID *PrpListHost;
+ VOID *MapData;
+ VOID *MapMeta;
+ EFI_EVENT CallerEvent;
} NVME_PASS_THRU_ASYNC_REQ;
#define NVME_PASS_THRU_ASYNC_REQ_FROM_THIS(a) \
@@ -426,11 +425,11 @@ NvmExpressComponentNameGetDriverName ( EFI_STATUS
EFIAPI
NvmExpressComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
/**
@@ -555,10 +554,10 @@ NvmExpressDriverBindingStart ( EFI_STATUS
EFIAPI
NvmExpressDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -594,10 +593,10 @@ NvmExpressDriverBindingStop ( EFI_STATUS
EFIAPI
NvmExpressPassThru (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN UINT32 NamespaceId,
- IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
- IN EFI_EVENT Event OPTIONAL
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
);
/**
@@ -636,8 +635,8 @@ NvmExpressPassThru ( EFI_STATUS
EFIAPI
NvmExpressGetNextNamespace (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN OUT UINT32 *NamespaceId
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT32 *NamespaceId
);
/**
@@ -667,9 +666,9 @@ NvmExpressGetNextNamespace ( EFI_STATUS
EFIAPI
NvmExpressGetNamespace (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINT32 *NamespaceId
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT32 *NamespaceId
);
/**
@@ -706,9 +705,9 @@ NvmExpressGetNamespace ( EFI_STATUS
EFIAPI
NvmExpressBuildDevicePath (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN UINT32 NamespaceId,
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -719,7 +718,7 @@ NvmExpressBuildDevicePath ( **/
VOID
NvmeDumpStatus (
- IN NVME_CQ *Cq
+ IN NVME_CQ *Cq
);
/**
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.c index c63a6537ac..b33c903412 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.c @@ -23,27 +23,27 @@ **/
EFI_STATUS
ReadSectors (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- IN UINT64 Buffer,
- IN UINT64 Lba,
- IN UINT32 Blocks
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ IN UINT64 Buffer,
+ IN UINT64 Lba,
+ IN UINT32 Blocks
)
{
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 Bytes;
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- UINT32 BlockSize;
-
- Private = Device->Controller;
- BlockSize = Device->Media.BlockSize;
- Bytes = Blocks * BlockSize;
-
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 Bytes;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+
+ Private = Device->Controller;
+ BlockSize = Device->Media.BlockSize;
+ Bytes = Blocks * BlockSize;
+
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -57,7 +57,7 @@ ReadSectors ( CommandPacket.QueueType = NVME_IO_QUEUE;
CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;
- CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);
+ CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64 (Lba, 32);
CommandPacket.NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;
CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID | CDW12_VALID;
@@ -86,41 +86,41 @@ ReadSectors ( **/
EFI_STATUS
WriteSectors (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- IN UINT64 Buffer,
- IN UINT64 Lba,
- IN UINT32 Blocks
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ IN UINT64 Buffer,
+ IN UINT64 Lba,
+ IN UINT32 Blocks
)
{
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- UINT32 Bytes;
- UINT32 BlockSize;
-
- Private = Device->Controller;
- BlockSize = Device->Media.BlockSize;
- Bytes = Blocks * BlockSize;
-
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ UINT32 Bytes;
+ UINT32 BlockSize;
+
+ Private = Device->Controller;
+ BlockSize = Device->Media.BlockSize;
+ Bytes = Blocks * BlockSize;
+
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
CommandPacket.NvmeCmd->Cdw0.Opcode = NVME_IO_WRITE_OPC;
- CommandPacket.NvmeCmd->Nsid = Device->NamespaceId;
- CommandPacket.TransferBuffer = (VOID *)(UINTN)Buffer;
+ CommandPacket.NvmeCmd->Nsid = Device->NamespaceId;
+ CommandPacket.TransferBuffer = (VOID *)(UINTN)Buffer;
CommandPacket.TransferLength = Bytes;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
CommandPacket.QueueType = NVME_IO_QUEUE;
CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;
- CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);
+ CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64 (Lba, 32);
//
// Set Force Unit Access bit (bit 30) to use write-through behaviour
//
@@ -155,19 +155,19 @@ WriteSectors ( **/
EFI_STATUS
NvmeRead (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- OUT VOID *Buffer,
- IN UINT64 Lba,
- IN UINTN Blocks
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ OUT VOID *Buffer,
+ IN UINT64 Lba,
+ IN UINTN Blocks
)
{
- EFI_STATUS Status;
- UINT32 BlockSize;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 MaxTransferBlocks;
- UINTN OrginalBlocks;
- BOOLEAN IsEmpty;
- EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 MaxTransferBlocks;
+ UINTN OrginalBlocks;
+ BOOLEAN IsEmpty;
+ EFI_TPL OldTpl;
//
// Wait for the device's asynchronous I/O queue to become empty.
@@ -207,14 +207,22 @@ NvmeRead ( Blocks = 0;
}
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
break;
}
}
- DEBUG ((DEBUG_BLKIO, "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
- "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n", __FUNCTION__, Lba,
- (UINT64)OrginalBlocks, (UINT64)Blocks, BlockSize, Status));
+ DEBUG ((
+ DEBUG_BLKIO,
+ "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
+ "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n",
+ __FUNCTION__,
+ Lba,
+ (UINT64)OrginalBlocks,
+ (UINT64)Blocks,
+ BlockSize,
+ Status
+ ));
return Status;
}
@@ -233,19 +241,19 @@ NvmeRead ( **/
EFI_STATUS
NvmeWrite (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- IN VOID *Buffer,
- IN UINT64 Lba,
- IN UINTN Blocks
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ IN VOID *Buffer,
+ IN UINT64 Lba,
+ IN UINTN Blocks
)
{
- EFI_STATUS Status;
- UINT32 BlockSize;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 MaxTransferBlocks;
- UINTN OrginalBlocks;
- BOOLEAN IsEmpty;
- EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 MaxTransferBlocks;
+ UINTN OrginalBlocks;
+ BOOLEAN IsEmpty;
+ EFI_TPL OldTpl;
//
// Wait for the device's asynchronous I/O queue to become empty.
@@ -285,14 +293,22 @@ NvmeWrite ( Blocks = 0;
}
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
break;
}
}
- DEBUG ((DEBUG_BLKIO, "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
- "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n", __FUNCTION__, Lba,
- (UINT64)OrginalBlocks, (UINT64)Blocks, BlockSize, Status));
+ DEBUG ((
+ DEBUG_BLKIO,
+ "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
+ "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n",
+ __FUNCTION__,
+ Lba,
+ (UINT64)OrginalBlocks,
+ (UINT64)Blocks,
+ BlockSize,
+ Status
+ ));
return Status;
}
@@ -308,28 +324,28 @@ NvmeWrite ( **/
EFI_STATUS
NvmeFlush (
- IN NVME_DEVICE_PRIVATE_DATA *Device
+ IN NVME_DEVICE_PRIVATE_DATA *Device
)
{
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
Private = Device->Controller;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
CommandPacket.NvmeCmd->Cdw0.Opcode = NVME_IO_FLUSH_OPC;
- CommandPacket.NvmeCmd->Nsid = Device->NamespaceId;
- CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
- CommandPacket.QueueType = NVME_IO_QUEUE;
+ CommandPacket.NvmeCmd->Nsid = Device->NamespaceId;
+ CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
+ CommandPacket.QueueType = NVME_IO_QUEUE;
Status = Private->Passthru.PassThru (
&Private->Passthru,
@@ -352,19 +368,19 @@ NvmeFlush ( VOID
EFIAPI
AsyncIoCallback (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- NVME_BLKIO2_SUBTASK *Subtask;
- NVME_BLKIO2_REQUEST *Request;
- NVME_CQ *Completion;
- EFI_BLOCK_IO2_TOKEN *Token;
+ NVME_BLKIO2_SUBTASK *Subtask;
+ NVME_BLKIO2_REQUEST *Request;
+ NVME_CQ *Completion;
+ EFI_BLOCK_IO2_TOKEN *Token;
gBS->CloseEvent (Event);
- Subtask = (NVME_BLKIO2_SUBTASK *) Context;
- Completion = (NVME_CQ *) Subtask->CommandPacket->NvmeCompletion;
+ Subtask = (NVME_BLKIO2_SUBTASK *)Context;
+ Completion = (NVME_CQ *)Subtask->CommandPacket->NvmeCompletion;
Request = Subtask->BlockIo2Request;
Token = Request->Token;
@@ -379,9 +395,9 @@ AsyncIoCallback ( //
// Dump completion entry status for debugging.
//
- DEBUG_CODE_BEGIN();
- NvmeDumpStatus (Completion);
- DEBUG_CODE_END();
+ DEBUG_CODE_BEGIN ();
+ NvmeDumpStatus (Completion);
+ DEBUG_CODE_END ();
}
}
@@ -422,23 +438,23 @@ AsyncIoCallback ( **/
EFI_STATUS
AsyncReadSectors (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- IN NVME_BLKIO2_REQUEST *Request,
- IN UINT64 Buffer,
- IN UINT64 Lba,
- IN UINT32 Blocks,
- IN BOOLEAN IsLast
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ IN NVME_BLKIO2_REQUEST *Request,
+ IN UINT64 Buffer,
+ IN UINT64 Lba,
+ IN UINT32 Blocks,
+ IN BOOLEAN IsLast
)
{
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 Bytes;
- NVME_BLKIO2_SUBTASK *Subtask;
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
- EFI_NVM_EXPRESS_COMMAND *Command;
- EFI_NVM_EXPRESS_COMPLETION *Completion;
- EFI_STATUS Status;
- UINT32 BlockSize;
- EFI_TPL OldTpl;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 Bytes;
+ NVME_BLKIO2_SUBTASK *Subtask;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND *Command;
+ EFI_NVM_EXPRESS_COMPLETION *Completion;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ EFI_TPL OldTpl;
Private = Device->Controller;
BlockSize = Device->Media.BlockSize;
@@ -488,7 +504,7 @@ AsyncReadSectors ( Subtask,
&Subtask->Event
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto ErrorExit;
}
@@ -504,7 +520,7 @@ AsyncReadSectors ( CommandPacket->QueueType = NVME_IO_QUEUE;
CommandPacket->NvmeCmd->Cdw10 = (UINT32)Lba;
- CommandPacket->NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);
+ CommandPacket->NvmeCmd->Cdw11 = (UINT32)RShiftU64 (Lba, 32);
CommandPacket->NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;
CommandPacket->NvmeCmd->Flags = CDW10_VALID | CDW11_VALID | CDW12_VALID;
@@ -561,23 +577,23 @@ ErrorExit: **/
EFI_STATUS
AsyncWriteSectors (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- IN NVME_BLKIO2_REQUEST *Request,
- IN UINT64 Buffer,
- IN UINT64 Lba,
- IN UINT32 Blocks,
- IN BOOLEAN IsLast
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ IN NVME_BLKIO2_REQUEST *Request,
+ IN UINT64 Buffer,
+ IN UINT64 Lba,
+ IN UINT32 Blocks,
+ IN BOOLEAN IsLast
)
{
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 Bytes;
- NVME_BLKIO2_SUBTASK *Subtask;
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
- EFI_NVM_EXPRESS_COMMAND *Command;
- EFI_NVM_EXPRESS_COMPLETION *Completion;
- EFI_STATUS Status;
- UINT32 BlockSize;
- EFI_TPL OldTpl;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 Bytes;
+ NVME_BLKIO2_SUBTASK *Subtask;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND *Command;
+ EFI_NVM_EXPRESS_COMPLETION *Completion;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ EFI_TPL OldTpl;
Private = Device->Controller;
BlockSize = Device->Media.BlockSize;
@@ -627,7 +643,7 @@ AsyncWriteSectors ( Subtask,
&Subtask->Event
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto ErrorExit;
}
@@ -643,7 +659,7 @@ AsyncWriteSectors ( CommandPacket->QueueType = NVME_IO_QUEUE;
CommandPacket->NvmeCmd->Cdw10 = (UINT32)Lba;
- CommandPacket->NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);
+ CommandPacket->NvmeCmd->Cdw11 = (UINT32)RShiftU64 (Lba, 32);
//
// Set Force Unit Access bit (bit 30) to use write-through behaviour
//
@@ -701,21 +717,21 @@ ErrorExit: **/
EFI_STATUS
NvmeAsyncRead (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- OUT VOID *Buffer,
- IN UINT64 Lba,
- IN UINTN Blocks,
- IN EFI_BLOCK_IO2_TOKEN *Token
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ OUT VOID *Buffer,
+ IN UINT64 Lba,
+ IN UINTN Blocks,
+ IN EFI_BLOCK_IO2_TOKEN *Token
)
{
- EFI_STATUS Status;
- UINT32 BlockSize;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- NVME_BLKIO2_REQUEST *BlkIo2Req;
- UINT32 MaxTransferBlocks;
- UINTN OrginalBlocks;
- BOOLEAN IsEmpty;
- EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ NVME_BLKIO2_REQUEST *BlkIo2Req;
+ UINT32 MaxTransferBlocks;
+ UINTN OrginalBlocks;
+ BOOLEAN IsEmpty;
+ EFI_TPL OldTpl;
Status = EFI_SUCCESS;
Private = Device->Controller;
@@ -745,7 +761,8 @@ NvmeAsyncRead ( if (Blocks > MaxTransferBlocks) {
Status = AsyncReadSectors (
Device,
- BlkIo2Req, (UINT64)(UINTN)Buffer,
+ BlkIo2Req,
+ (UINT64)(UINTN)Buffer,
Lba,
MaxTransferBlocks,
FALSE
@@ -767,7 +784,7 @@ NvmeAsyncRead ( Blocks = 0;
}
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
IsEmpty = IsListEmpty (&BlkIo2Req->SubtasksQueue) &&
(BlkIo2Req->UnsubmittedSubtaskNum == 0);
@@ -785,8 +802,8 @@ NvmeAsyncRead ( // should be returned to make sure that the caller does not free
// resources still using by these requests.
//
- Status = EFI_SUCCESS;
- Token->TransactionStatus = EFI_DEVICE_ERROR;
+ Status = EFI_SUCCESS;
+ Token->TransactionStatus = EFI_DEVICE_ERROR;
BlkIo2Req->LastSubtaskSubmitted = TRUE;
}
@@ -796,9 +813,17 @@ NvmeAsyncRead ( }
}
- DEBUG ((DEBUG_BLKIO, "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
- "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n", __FUNCTION__, Lba,
- (UINT64)OrginalBlocks, (UINT64)Blocks, BlockSize, Status));
+ DEBUG ((
+ DEBUG_BLKIO,
+ "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
+ "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n",
+ __FUNCTION__,
+ Lba,
+ (UINT64)OrginalBlocks,
+ (UINT64)Blocks,
+ BlockSize,
+ Status
+ ));
return Status;
}
@@ -820,21 +845,21 @@ NvmeAsyncRead ( **/
EFI_STATUS
NvmeAsyncWrite (
- IN NVME_DEVICE_PRIVATE_DATA *Device,
- IN VOID *Buffer,
- IN UINT64 Lba,
- IN UINTN Blocks,
- IN EFI_BLOCK_IO2_TOKEN *Token
+ IN NVME_DEVICE_PRIVATE_DATA *Device,
+ IN VOID *Buffer,
+ IN UINT64 Lba,
+ IN UINTN Blocks,
+ IN EFI_BLOCK_IO2_TOKEN *Token
)
{
- EFI_STATUS Status;
- UINT32 BlockSize;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- NVME_BLKIO2_REQUEST *BlkIo2Req;
- UINT32 MaxTransferBlocks;
- UINTN OrginalBlocks;
- BOOLEAN IsEmpty;
- EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ NVME_BLKIO2_REQUEST *BlkIo2Req;
+ UINT32 MaxTransferBlocks;
+ UINTN OrginalBlocks;
+ BOOLEAN IsEmpty;
+ EFI_TPL OldTpl;
Status = EFI_SUCCESS;
Private = Device->Controller;
@@ -862,14 +887,14 @@ NvmeAsyncWrite ( while (Blocks > 0) {
if (Blocks > MaxTransferBlocks) {
- Status = AsyncWriteSectors (
- Device,
- BlkIo2Req,
- (UINT64)(UINTN)Buffer,
- Lba,
- MaxTransferBlocks,
- FALSE
- );
+ Status = AsyncWriteSectors (
+ Device,
+ BlkIo2Req,
+ (UINT64)(UINTN)Buffer,
+ Lba,
+ MaxTransferBlocks,
+ FALSE
+ );
Blocks -= MaxTransferBlocks;
Buffer = (VOID *)(UINTN)((UINT64)(UINTN)Buffer + MaxTransferBlocks * BlockSize);
@@ -887,7 +912,7 @@ NvmeAsyncWrite ( Blocks = 0;
}
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
IsEmpty = IsListEmpty (&BlkIo2Req->SubtasksQueue) &&
(BlkIo2Req->UnsubmittedSubtaskNum == 0);
@@ -905,8 +930,8 @@ NvmeAsyncWrite ( // should be returned to make sure that the caller does not free
// resources still using by these requests.
//
- Status = EFI_SUCCESS;
- Token->TransactionStatus = EFI_DEVICE_ERROR;
+ Status = EFI_SUCCESS;
+ Token->TransactionStatus = EFI_DEVICE_ERROR;
BlkIo2Req->LastSubtaskSubmitted = TRUE;
}
@@ -916,9 +941,17 @@ NvmeAsyncWrite ( }
}
- DEBUG ((DEBUG_BLKIO, "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
- "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n", __FUNCTION__, Lba,
- (UINT64)OrginalBlocks, (UINT64)Blocks, BlockSize, Status));
+ DEBUG ((
+ DEBUG_BLKIO,
+ "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
+ "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n",
+ __FUNCTION__,
+ Lba,
+ (UINT64)OrginalBlocks,
+ (UINT64)Blocks,
+ BlockSize,
+ Status
+ ));
return Status;
}
@@ -937,14 +970,14 @@ NvmeAsyncWrite ( EFI_STATUS
EFIAPI
NvmeBlockIoReset (
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN BOOLEAN ExtendedVerification
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
)
{
- EFI_TPL OldTpl;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STATUS Status;
+ EFI_TPL OldTpl;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
if (This == NULL) {
return EFI_INVALID_PARAMETER;
@@ -953,13 +986,13 @@ NvmeBlockIoReset ( //
// For Nvm Express subsystem, reset block device means reset controller.
//
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
- Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (This);
+ Device = NVME_DEVICE_PRIVATE_DATA_FROM_BLOCK_IO (This);
Private = Device->Controller;
- Status = NvmeControllerInit (Private);
+ Status = NvmeControllerInit (Private);
if (EFI_ERROR (Status)) {
Status = EFI_DEVICE_ERROR;
@@ -992,20 +1025,20 @@ NvmeBlockIoReset ( EFI_STATUS
EFIAPI
NvmeBlockIoReadBlocks (
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
)
{
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STATUS Status;
- EFI_BLOCK_IO_MEDIA *Media;
- UINTN BlockSize;
- UINTN NumberOfBlocks;
- UINTN IoAlign;
- EFI_TPL OldTpl;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN BlockSize;
+ UINTN NumberOfBlocks;
+ UINTN IoAlign;
+ EFI_TPL OldTpl;
//
// Check parameters.
@@ -1033,13 +1066,13 @@ NvmeBlockIoReadBlocks ( return EFI_BAD_BUFFER_SIZE;
}
- NumberOfBlocks = BufferSize / BlockSize;
+ NumberOfBlocks = BufferSize / BlockSize;
if ((Lba + NumberOfBlocks - 1) > Media->LastBlock) {
return EFI_INVALID_PARAMETER;
}
IoAlign = Media->IoAlign;
- if (IoAlign > 0 && (((UINTN) Buffer & (IoAlign - 1)) != 0)) {
+ if ((IoAlign > 0) && (((UINTN)Buffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
@@ -1076,20 +1109,20 @@ NvmeBlockIoReadBlocks ( EFI_STATUS
EFIAPI
NvmeBlockIoWriteBlocks (
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN UINTN BufferSize,
- IN VOID *Buffer
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
)
{
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STATUS Status;
- EFI_BLOCK_IO_MEDIA *Media;
- UINTN BlockSize;
- UINTN NumberOfBlocks;
- UINTN IoAlign;
- EFI_TPL OldTpl;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN BlockSize;
+ UINTN NumberOfBlocks;
+ UINTN IoAlign;
+ EFI_TPL OldTpl;
//
// Check parameters.
@@ -1117,13 +1150,13 @@ NvmeBlockIoWriteBlocks ( return EFI_BAD_BUFFER_SIZE;
}
- NumberOfBlocks = BufferSize / BlockSize;
+ NumberOfBlocks = BufferSize / BlockSize;
if ((Lba + NumberOfBlocks - 1) > Media->LastBlock) {
return EFI_INVALID_PARAMETER;
}
IoAlign = Media->IoAlign;
- if (IoAlign > 0 && (((UINTN) Buffer & (IoAlign - 1)) != 0)) {
+ if ((IoAlign > 0) && (((UINTN)Buffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
@@ -1151,12 +1184,12 @@ NvmeBlockIoWriteBlocks ( EFI_STATUS
EFIAPI
NvmeBlockIoFlushBlocks (
- IN EFI_BLOCK_IO_PROTOCOL *This
+ IN EFI_BLOCK_IO_PROTOCOL *This
)
{
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
//
// Check parameters.
@@ -1196,11 +1229,11 @@ NvmeBlockIoResetEx ( IN BOOLEAN ExtendedVerification
)
{
- EFI_STATUS Status;
- NVME_DEVICE_PRIVATE_DATA *Device;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- BOOLEAN IsEmpty;
- EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ BOOLEAN IsEmpty;
+ EFI_TPL OldTpl;
if (This == NULL) {
return EFI_INVALID_PARAMETER;
@@ -1227,7 +1260,7 @@ NvmeBlockIoResetEx ( OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
- Status = NvmeControllerInit (Private);
+ Status = NvmeControllerInit (Private);
if (EFI_ERROR (Status)) {
Status = EFI_DEVICE_ERROR;
@@ -1278,21 +1311,21 @@ NvmeBlockIoResetEx ( EFI_STATUS
EFIAPI
NvmeBlockIoReadBlocksEx (
- IN EFI_BLOCK_IO2_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN OUT EFI_BLOCK_IO2_TOKEN *Token,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
)
{
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STATUS Status;
- EFI_BLOCK_IO_MEDIA *Media;
- UINTN BlockSize;
- UINTN NumberOfBlocks;
- UINTN IoAlign;
- EFI_TPL OldTpl;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN BlockSize;
+ UINTN NumberOfBlocks;
+ UINTN IoAlign;
+ EFI_TPL OldTpl;
//
// Check parameters.
@@ -1316,6 +1349,7 @@ NvmeBlockIoReadBlocksEx ( Token->TransactionStatus = EFI_SUCCESS;
gBS->SignalEvent (Token->Event);
}
+
return EFI_SUCCESS;
}
@@ -1324,13 +1358,13 @@ NvmeBlockIoReadBlocksEx ( return EFI_BAD_BUFFER_SIZE;
}
- NumberOfBlocks = BufferSize / BlockSize;
+ NumberOfBlocks = BufferSize / BlockSize;
if ((Lba + NumberOfBlocks - 1) > Media->LastBlock) {
return EFI_INVALID_PARAMETER;
}
IoAlign = Media->IoAlign;
- if (IoAlign > 0 && (((UINTN) Buffer & (IoAlign - 1)) != 0)) {
+ if ((IoAlign > 0) && (((UINTN)Buffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
@@ -1340,7 +1374,7 @@ NvmeBlockIoReadBlocksEx ( if ((Token != NULL) && (Token->Event != NULL)) {
Token->TransactionStatus = EFI_SUCCESS;
- Status = NvmeAsyncRead (Device, Buffer, Lba, NumberOfBlocks, Token);
+ Status = NvmeAsyncRead (Device, Buffer, Lba, NumberOfBlocks, Token);
} else {
Status = NvmeRead (Device, Buffer, Lba, NumberOfBlocks);
}
@@ -1391,20 +1425,20 @@ EFI_STATUS EFIAPI
NvmeBlockIoWriteBlocksEx (
IN EFI_BLOCK_IO2_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN OUT EFI_BLOCK_IO2_TOKEN *Token,
- IN UINTN BufferSize,
- IN VOID *Buffer
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
)
{
- NVME_DEVICE_PRIVATE_DATA *Device;
- EFI_STATUS Status;
- EFI_BLOCK_IO_MEDIA *Media;
- UINTN BlockSize;
- UINTN NumberOfBlocks;
- UINTN IoAlign;
- EFI_TPL OldTpl;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN BlockSize;
+ UINTN NumberOfBlocks;
+ UINTN IoAlign;
+ EFI_TPL OldTpl;
//
// Check parameters.
@@ -1428,6 +1462,7 @@ NvmeBlockIoWriteBlocksEx ( Token->TransactionStatus = EFI_SUCCESS;
gBS->SignalEvent (Token->Event);
}
+
return EFI_SUCCESS;
}
@@ -1436,13 +1471,13 @@ NvmeBlockIoWriteBlocksEx ( return EFI_BAD_BUFFER_SIZE;
}
- NumberOfBlocks = BufferSize / BlockSize;
+ NumberOfBlocks = BufferSize / BlockSize;
if ((Lba + NumberOfBlocks - 1) > Media->LastBlock) {
return EFI_INVALID_PARAMETER;
}
IoAlign = Media->IoAlign;
- if (IoAlign > 0 && (((UINTN) Buffer & (IoAlign - 1)) != 0)) {
+ if ((IoAlign > 0) && (((UINTN)Buffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
@@ -1452,7 +1487,7 @@ NvmeBlockIoWriteBlocksEx ( if ((Token != NULL) && (Token->Event != NULL)) {
Token->TransactionStatus = EFI_SUCCESS;
- Status = NvmeAsyncWrite (Device, Buffer, Lba, NumberOfBlocks, Token);
+ Status = NvmeAsyncWrite (Device, Buffer, Lba, NumberOfBlocks, Token);
} else {
Status = NvmeWrite (Device, Buffer, Lba, NumberOfBlocks);
}
@@ -1488,13 +1523,13 @@ NvmeBlockIoWriteBlocksEx ( EFI_STATUS
EFIAPI
NvmeBlockIoFlushBlocksEx (
- IN EFI_BLOCK_IO2_PROTOCOL *This,
- IN OUT EFI_BLOCK_IO2_TOKEN *Token
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token
)
{
- NVME_DEVICE_PRIVATE_DATA *Device;
- BOOLEAN IsEmpty;
- EFI_TPL OldTpl;
+ NVME_DEVICE_PRIVATE_DATA *Device;
+ BOOLEAN IsEmpty;
+ EFI_TPL OldTpl;
//
// Check parameters.
@@ -1560,21 +1595,21 @@ NvmeBlockIoFlushBlocksEx ( **/
EFI_STATUS
TrustTransferNvmeDevice (
- IN OUT NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN OUT VOID *Buffer,
- IN UINT8 SecurityProtocolId,
- IN UINT16 SecurityProtocolSpecificData,
- IN UINTN TransferLength,
- IN BOOLEAN IsTrustSend,
- IN UINT64 Timeout,
- OUT UINTN *TransferLengthOut
+ IN OUT NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN OUT VOID *Buffer,
+ IN UINT8 SecurityProtocolId,
+ IN UINT16 SecurityProtocolSpecificData,
+ IN UINTN TransferLength,
+ IN BOOLEAN IsTrustSend,
+ IN UINT64 Timeout,
+ OUT UINTN *TransferLengthOut
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- UINT16 SpecificData;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ UINT16 SpecificData;
ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
@@ -1615,10 +1650,10 @@ TrustTransferNvmeDevice ( );
if (!IsTrustSend) {
- if (EFI_ERROR (Status)) {
+ if (EFI_ERROR (Status)) {
*TransferLengthOut = 0;
} else {
- *TransferLengthOut = (UINTN) TransferLength;
+ *TransferLengthOut = (UINTN)TransferLength;
}
}
@@ -1700,20 +1735,20 @@ TrustTransferNvmeDevice ( EFI_STATUS
EFIAPI
NvmeStorageSecurityReceiveData (
- IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
- IN UINT32 MediaId,
- IN UINT64 Timeout,
- IN UINT8 SecurityProtocolId,
- IN UINT16 SecurityProtocolSpecificData,
- IN UINTN PayloadBufferSize,
- OUT VOID *PayloadBuffer,
- OUT UINTN *PayloadTransferSize
+ IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Timeout,
+ IN UINT8 SecurityProtocolId,
+ IN UINT16 SecurityProtocolSpecificData,
+ IN UINTN PayloadBufferSize,
+ OUT VOID *PayloadBuffer,
+ OUT UINTN *PayloadTransferSize
)
{
- EFI_STATUS Status;
- NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ NVME_DEVICE_PRIVATE_DATA *Device;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
if ((PayloadBuffer == NULL) || (PayloadTransferSize == NULL) || (PayloadBufferSize == 0)) {
return EFI_INVALID_PARAMETER;
@@ -1807,19 +1842,19 @@ NvmeStorageSecurityReceiveData ( EFI_STATUS
EFIAPI
NvmeStorageSecuritySendData (
- IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
- IN UINT32 MediaId,
- IN UINT64 Timeout,
- IN UINT8 SecurityProtocolId,
- IN UINT16 SecurityProtocolSpecificData,
- IN UINTN PayloadBufferSize,
- IN VOID *PayloadBuffer
+ IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Timeout,
+ IN UINT8 SecurityProtocolId,
+ IN UINT16 SecurityProtocolSpecificData,
+ IN UINTN PayloadBufferSize,
+ IN VOID *PayloadBuffer
)
{
- EFI_STATUS Status;
- NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ NVME_DEVICE_PRIVATE_DATA *Device;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
if ((PayloadBuffer == NULL) && (PayloadBufferSize != 0)) {
return EFI_INVALID_PARAMETER;
@@ -1848,7 +1883,3 @@ NvmeStorageSecuritySendData ( return Status;
}
-
-
-
-
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.h index ba00dde440..8cad15efd3 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressBlockIo.h @@ -23,8 +23,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_STATUS
EFIAPI
NvmeBlockIoReset (
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN BOOLEAN ExtendedVerification
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
);
/**
@@ -49,11 +49,11 @@ NvmeBlockIoReset ( EFI_STATUS
EFIAPI
NvmeBlockIoReadBlocks (
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
);
/**
@@ -79,11 +79,11 @@ NvmeBlockIoReadBlocks ( EFI_STATUS
EFIAPI
NvmeBlockIoWriteBlocks (
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN UINTN BufferSize,
- IN VOID *Buffer
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
);
/**
@@ -99,7 +99,7 @@ NvmeBlockIoWriteBlocks ( EFI_STATUS
EFIAPI
NvmeBlockIoFlushBlocks (
- IN EFI_BLOCK_IO_PROTOCOL *This
+ IN EFI_BLOCK_IO_PROTOCOL *This
);
/**
@@ -162,12 +162,12 @@ NvmeBlockIoResetEx ( EFI_STATUS
EFIAPI
NvmeBlockIoReadBlocksEx (
- IN EFI_BLOCK_IO2_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN OUT EFI_BLOCK_IO2_TOKEN *Token,
- IN UINTN BufferSize,
- OUT VOID *Buffer
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
);
/**
@@ -212,11 +212,11 @@ EFI_STATUS EFIAPI
NvmeBlockIoWriteBlocksEx (
IN EFI_BLOCK_IO2_PROTOCOL *This,
- IN UINT32 MediaId,
- IN EFI_LBA Lba,
- IN OUT EFI_BLOCK_IO2_TOKEN *Token,
- IN UINTN BufferSize,
- IN VOID *Buffer
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
);
/**
@@ -246,8 +246,8 @@ NvmeBlockIoWriteBlocksEx ( EFI_STATUS
EFIAPI
NvmeBlockIoFlushBlocksEx (
- IN EFI_BLOCK_IO2_PROTOCOL *This,
- IN OUT EFI_BLOCK_IO2_TOKEN *Token
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token
);
/**
@@ -325,14 +325,14 @@ NvmeBlockIoFlushBlocksEx ( EFI_STATUS
EFIAPI
NvmeStorageSecurityReceiveData (
- IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
- IN UINT32 MediaId,
- IN UINT64 Timeout,
- IN UINT8 SecurityProtocolId,
- IN UINT16 SecurityProtocolSpecificData,
- IN UINTN PayloadBufferSize,
- OUT VOID *PayloadBuffer,
- OUT UINTN *PayloadTransferSize
+ IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Timeout,
+ IN UINT8 SecurityProtocolId,
+ IN UINT16 SecurityProtocolSpecificData,
+ IN UINTN PayloadBufferSize,
+ OUT VOID *PayloadBuffer,
+ OUT UINTN *PayloadTransferSize
);
/**
@@ -399,13 +399,13 @@ NvmeStorageSecurityReceiveData ( EFI_STATUS
EFIAPI
NvmeStorageSecuritySendData (
- IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
- IN UINT32 MediaId,
- IN UINT64 Timeout,
- IN UINT8 SecurityProtocolId,
- IN UINT16 SecurityProtocolSpecificData,
- IN UINTN PayloadBufferSize,
- IN VOID *PayloadBuffer
+ IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Timeout,
+ IN UINT8 SecurityProtocolId,
+ IN UINT16 SecurityProtocolSpecificData,
+ IN UINTN PayloadBufferSize,
+ IN VOID *PayloadBuffer
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.c index 10b79d4ad7..9a5ca67300 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.c @@ -8,7 +8,7 @@ #include "NvmExpress.h"
-EFI_DISK_INFO_PROTOCOL gNvmExpressDiskInfoProtocolTemplate = {
+EFI_DISK_INFO_PROTOCOL gNvmExpressDiskInfoProtocolTemplate = {
EFI_DISK_INFO_NVME_INTERFACE_GUID,
NvmExpressDiskInfoInquiry,
NvmExpressDiskInfoIdentify,
@@ -27,13 +27,12 @@ EFI_DISK_INFO_PROTOCOL gNvmExpressDiskInfoProtocolTemplate = { **/
VOID
InitializeDiskInfo (
- IN NVME_DEVICE_PRIVATE_DATA *Device
+ IN NVME_DEVICE_PRIVATE_DATA *Device
)
{
CopyMem (&Device->DiskInfo, &gNvmExpressDiskInfoProtocolTemplate, sizeof (EFI_DISK_INFO_PROTOCOL));
}
-
/**
Provides inquiry information for the controller type.
@@ -53,15 +52,14 @@ InitializeDiskInfo ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoInquiry (
- IN EFI_DISK_INFO_PROTOCOL *This,
- IN OUT VOID *InquiryData,
- IN OUT UINT32 *InquiryDataSize
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *InquiryData,
+ IN OUT UINT32 *InquiryDataSize
)
{
return EFI_NOT_FOUND;
}
-
/**
Provides identify information for the controller type.
@@ -83,13 +81,13 @@ NvmExpressDiskInfoInquiry ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoIdentify (
- IN EFI_DISK_INFO_PROTOCOL *This,
- IN OUT VOID *IdentifyData,
- IN OUT UINT32 *IdentifyDataSize
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *IdentifyData,
+ IN OUT UINT32 *IdentifyDataSize
)
{
- EFI_STATUS Status;
- NVME_DEVICE_PRIVATE_DATA *Device;
+ EFI_STATUS Status;
+ NVME_DEVICE_PRIVATE_DATA *Device;
Device = NVME_DEVICE_PRIVATE_DATA_FROM_DISK_INFO (This);
@@ -98,6 +96,7 @@ NvmExpressDiskInfoIdentify ( Status = EFI_SUCCESS;
CopyMem (IdentifyData, &Device->NamespaceData, sizeof (Device->NamespaceData));
}
+
*IdentifyDataSize = sizeof (Device->NamespaceData);
return Status;
}
@@ -122,16 +121,15 @@ NvmExpressDiskInfoIdentify ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoSenseData (
- IN EFI_DISK_INFO_PROTOCOL *This,
- IN OUT VOID *SenseData,
- IN OUT UINT32 *SenseDataSize,
- OUT UINT8 *SenseDataNumber
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *SenseData,
+ IN OUT UINT32 *SenseDataSize,
+ OUT UINT8 *SenseDataNumber
)
{
return EFI_NOT_FOUND;
}
-
/**
This function is used to get controller information.
@@ -146,11 +144,10 @@ NvmExpressDiskInfoSenseData ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoWhichIde (
- IN EFI_DISK_INFO_PROTOCOL *This,
- OUT UINT32 *IdeChannel,
- OUT UINT32 *IdeDevice
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ OUT UINT32 *IdeChannel,
+ OUT UINT32 *IdeDevice
)
{
return EFI_UNSUPPORTED;
}
-
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.h index b19e6f0a3b..22135ca262 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDiskInfo.h @@ -20,10 +20,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
InitializeDiskInfo (
- IN NVME_DEVICE_PRIVATE_DATA *Device
+ IN NVME_DEVICE_PRIVATE_DATA *Device
);
-
/**
Provides inquiry information for the controller type.
@@ -43,9 +42,9 @@ InitializeDiskInfo ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoInquiry (
- IN EFI_DISK_INFO_PROTOCOL *This,
- IN OUT VOID *InquiryData,
- IN OUT UINT32 *InquiryDataSize
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *InquiryData,
+ IN OUT UINT32 *InquiryDataSize
);
/**
@@ -69,9 +68,9 @@ NvmExpressDiskInfoInquiry ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoIdentify (
- IN EFI_DISK_INFO_PROTOCOL *This,
- IN OUT VOID *IdentifyData,
- IN OUT UINT32 *IdentifyDataSize
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *IdentifyData,
+ IN OUT UINT32 *IdentifyDataSize
);
/**
@@ -94,13 +93,12 @@ NvmExpressDiskInfoIdentify ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoSenseData (
- IN EFI_DISK_INFO_PROTOCOL *This,
- IN OUT VOID *SenseData,
- IN OUT UINT32 *SenseDataSize,
- OUT UINT8 *SenseDataNumber
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *SenseData,
+ IN OUT UINT32 *SenseDataSize,
+ OUT UINT8 *SenseDataNumber
);
-
/**
This function is used to get controller information.
@@ -115,9 +113,9 @@ NvmExpressDiskInfoSenseData ( EFI_STATUS
EFIAPI
NvmExpressDiskInfoWhichIde (
- IN EFI_DISK_INFO_PROTOCOL *This,
- OUT UINT32 *IdeChannel,
- OUT UINT32 *IdeDevice
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ OUT UINT32 *IdeChannel,
+ OUT UINT32 *IdeDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c index 08f9d50ff5..ac77afe113 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c @@ -9,13 +9,13 @@ #include "NvmExpress.h"
-#define NVME_SHUTDOWN_PROCESS_TIMEOUT 45
+#define NVME_SHUTDOWN_PROCESS_TIMEOUT 45
//
// The number of NVME controllers managed by this driver, used by
// NvmeRegisterShutdownNotification() and NvmeUnregisterShutdownNotification().
//
-UINTN mNvmeControllerNumber = 0;
+UINTN mNvmeControllerNumber = 0;
/**
Read Nvm Express controller capability register.
@@ -29,13 +29,13 @@ UINTN mNvmeControllerNumber = 0; **/
EFI_STATUS
ReadNvmeControllerCapabilities (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN NVME_CAP *Cap
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN NVME_CAP *Cap
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT64 Data;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT64 Data;
PciIo = Private->PciIo;
Status = PciIo->Mem.Read (
@@ -47,11 +47,11 @@ ReadNvmeControllerCapabilities ( &Data
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
- WriteUnaligned64 ((UINT64*)Cap, Data);
+ WriteUnaligned64 ((UINT64 *)Cap, Data);
return EFI_SUCCESS;
}
@@ -67,13 +67,13 @@ ReadNvmeControllerCapabilities ( **/
EFI_STATUS
ReadNvmeControllerConfiguration (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN NVME_CC *Cc
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN NVME_CC *Cc
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT32 Data;
PciIo = Private->PciIo;
Status = PciIo->Mem.Read (
@@ -85,11 +85,11 @@ ReadNvmeControllerConfiguration ( &Data
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
- WriteUnaligned32 ((UINT32*)Cc, Data);
+ WriteUnaligned32 ((UINT32 *)Cc, Data);
return EFI_SUCCESS;
}
@@ -105,16 +105,16 @@ ReadNvmeControllerConfiguration ( **/
EFI_STATUS
WriteNvmeControllerConfiguration (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN NVME_CC *Cc
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN NVME_CC *Cc
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT32 Data;
PciIo = Private->PciIo;
- Data = ReadUnaligned32 ((UINT32*)Cc);
+ Data = ReadUnaligned32 ((UINT32 *)Cc);
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
@@ -124,7 +124,7 @@ WriteNvmeControllerConfiguration ( &Data
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -151,13 +151,13 @@ WriteNvmeControllerConfiguration ( **/
EFI_STATUS
ReadNvmeControllerStatus (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN NVME_CSTS *Csts
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN NVME_CSTS *Csts
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT32 Data;
PciIo = Private->PciIo;
Status = PciIo->Mem.Read (
@@ -169,16 +169,14 @@ ReadNvmeControllerStatus ( &Data
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
- WriteUnaligned32 ((UINT32*)Csts, Data);
+ WriteUnaligned32 ((UINT32 *)Csts, Data);
return EFI_SUCCESS;
}
-
-
/**
Write Nvm Express admin queue attributes register.
@@ -191,16 +189,16 @@ ReadNvmeControllerStatus ( **/
EFI_STATUS
WriteNvmeAdminQueueAttributes (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN NVME_AQA *Aqa
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN NVME_AQA *Aqa
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT32 Data;
PciIo = Private->PciIo;
- Data = ReadUnaligned32 ((UINT32*)Aqa);
+ Data = ReadUnaligned32 ((UINT32 *)Aqa);
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
@@ -210,7 +208,7 @@ WriteNvmeAdminQueueAttributes ( &Data
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -220,7 +218,6 @@ WriteNvmeAdminQueueAttributes ( return EFI_SUCCESS;
}
-
/**
Write Nvm Express admin submission queue base address register.
@@ -233,16 +230,16 @@ WriteNvmeAdminQueueAttributes ( **/
EFI_STATUS
WriteNvmeAdminSubmissionQueueBaseAddress (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN NVME_ASQ *Asq
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN NVME_ASQ *Asq
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT64 Data;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT64 Data;
- PciIo = Private->PciIo;
- Data = ReadUnaligned64 ((UINT64*)Asq);
+ PciIo = Private->PciIo;
+ Data = ReadUnaligned64 ((UINT64 *)Asq);
Status = PciIo->Mem.Write (
PciIo,
@@ -253,7 +250,7 @@ WriteNvmeAdminSubmissionQueueBaseAddress ( &Data
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -262,8 +259,6 @@ WriteNvmeAdminSubmissionQueueBaseAddress ( return EFI_SUCCESS;
}
-
-
/**
Write Nvm Express admin completion queue base address register.
@@ -276,16 +271,16 @@ WriteNvmeAdminSubmissionQueueBaseAddress ( **/
EFI_STATUS
WriteNvmeAdminCompletionQueueBaseAddress (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN NVME_ACQ *Acq
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN NVME_ACQ *Acq
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT64 Data;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT64 Data;
- PciIo = Private->PciIo;
- Data = ReadUnaligned64 ((UINT64*)Acq);
+ PciIo = Private->PciIo;
+ Data = ReadUnaligned64 ((UINT64 *)Acq);
Status = PciIo->Mem.Write (
PciIo,
@@ -296,7 +291,7 @@ WriteNvmeAdminCompletionQueueBaseAddress ( &Data
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -316,20 +311,20 @@ WriteNvmeAdminCompletionQueueBaseAddress ( **/
EFI_STATUS
NvmeDisableController (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- NVME_CC Cc;
- NVME_CSTS Csts;
- EFI_STATUS Status;
- UINT32 Index;
- UINT8 Timeout;
+ NVME_CC Cc;
+ NVME_CSTS Csts;
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINT8 Timeout;
//
// Read Controller Configuration Register.
//
Status = ReadNvmeControllerConfiguration (Private, &Cc);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -340,7 +335,7 @@ NvmeDisableController ( //
Status = WriteNvmeControllerConfiguration (Private, &Cc);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -354,15 +349,15 @@ NvmeDisableController ( Timeout = Private->Cap.To;
}
- for(Index = (Timeout * 500); Index != 0; --Index) {
- gBS->Stall(1000);
+ for (Index = (Timeout * 500); Index != 0; --Index) {
+ gBS->Stall (1000);
//
// Check if the controller is initialized
//
Status = ReadNvmeControllerStatus (Private, &Csts);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -395,14 +390,14 @@ NvmeDisableController ( **/
EFI_STATUS
NvmeEnableController (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- NVME_CC Cc;
- NVME_CSTS Csts;
- EFI_STATUS Status;
- UINT32 Index;
- UINT8 Timeout;
+ NVME_CC Cc;
+ NVME_CSTS Csts;
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINT8 Timeout;
//
// Enable the controller.
@@ -414,7 +409,7 @@ NvmeEnableController ( Cc.Iocqes = 4;
Status = WriteNvmeControllerConfiguration (Private, &Cc);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -428,15 +423,15 @@ NvmeEnableController ( Timeout = Private->Cap.To;
}
- for(Index = (Timeout * 500); Index != 0; --Index) {
- gBS->Stall(1000);
+ for (Index = (Timeout * 500); Index != 0; --Index) {
+ gBS->Stall (1000);
//
// Check if the controller is initialized
//
Status = ReadNvmeControllerStatus (Private, &Csts);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -469,25 +464,25 @@ NvmeEnableController ( **/
EFI_STATUS
NvmeIdentifyController (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN VOID *Buffer
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN VOID *Buffer
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
//
// According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
// For the Identify command, the Namespace Identifier is only used for the Namespace data structure.
//
- Command.Nsid = 0;
+ Command.Nsid = 0;
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -498,8 +493,8 @@ NvmeIdentifyController ( //
// Set bit 0 (Cns bit) to 1 to identify a controller
//
- Command.Cdw10 = 1;
- Command.Flags = CDW10_VALID;
+ Command.Cdw10 = 1;
+ Command.Flags = CDW10_VALID;
Status = Private->Passthru.PassThru (
&Private->Passthru,
@@ -524,25 +519,25 @@ NvmeIdentifyController ( **/
EFI_STATUS
NvmeIdentifyNamespace (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN VOID *Buffer
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN VOID *Buffer
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
- Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
- Command.Nsid = NamespaceId;
+ Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
+ Command.Nsid = NamespaceId;
CommandPacket.TransferBuffer = Buffer;
CommandPacket.TransferLength = sizeof (NVME_ADMIN_NAMESPACE_DATA);
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -574,30 +569,30 @@ NvmeIdentifyNamespace ( **/
EFI_STATUS
NvmeCreateIoCompletionQueue (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- NVME_ADMIN_CRIOCQ CrIoCq;
- UINT32 Index;
- UINT16 QueueSize;
-
- Status = EFI_SUCCESS;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ NVME_ADMIN_CRIOCQ CrIoCq;
+ UINT32 Index;
+ UINT16 QueueSize;
+
+ Status = EFI_SUCCESS;
Private->CreateIoQueue = TRUE;
for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
- ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
CommandPacket.TransferBuffer = Private->CqBufferPciAddr[Index];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -646,30 +641,30 @@ NvmeCreateIoCompletionQueue ( **/
EFI_STATUS
NvmeCreateIoSubmissionQueue (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- NVME_ADMIN_CRIOSQ CrIoSq;
- UINT32 Index;
- UINT16 QueueSize;
-
- Status = EFI_SUCCESS;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ NVME_ADMIN_CRIOSQ CrIoSq;
+ UINT32 Index;
+ UINT16 QueueSize;
+
+ Status = EFI_SUCCESS;
Private->CreateIoQueue = TRUE;
for (Index = 1; Index < NVME_MAX_QUEUES; Index++) {
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
- ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
CommandPacket.TransferBuffer = Private->SqBufferPciAddr[Index];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -720,17 +715,18 @@ NvmeCreateIoSubmissionQueue ( **/
EFI_STATUS
NvmeControllerInit (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Supports;
- NVME_AQA Aqa;
- NVME_ASQ Asq;
- NVME_ACQ Acq;
- UINT8 Sn[21];
- UINT8 Mn[41];
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Supports;
+ NVME_AQA Aqa;
+ NVME_ASQ Asq;
+ NVME_ACQ Acq;
+ UINT8 Sn[21];
+ UINT8 Mn[41];
+
//
// Save original PCI attributes and enable this controller.
//
@@ -799,12 +795,12 @@ NvmeControllerInit ( //
ASSERT ((Private->Cap.Mpsmin + 12) <= EFI_PAGE_SHIFT);
- Private->Cid[0] = 0;
- Private->Cid[1] = 0;
- Private->Cid[2] = 0;
- Private->Pt[0] = 0;
- Private->Pt[1] = 0;
- Private->Pt[2] = 0;
+ Private->Cid[0] = 0;
+ Private->Cid[1] = 0;
+ Private->Cid[2] = 0;
+ Private->Pt[0] = 0;
+ Private->Pt[1] = 0;
+ Private->Pt[2] = 0;
Private->SqTdbl[0].Sqt = 0;
Private->SqTdbl[1].Sqt = 0;
Private->SqTdbl[2].Sqt = 0;
@@ -815,7 +811,7 @@ NvmeControllerInit ( Status = NvmeDisableController (Private);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -869,7 +865,7 @@ NvmeControllerInit ( //
Status = WriteNvmeAdminQueueAttributes (Private, &Aqa);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -878,7 +874,7 @@ NvmeControllerInit ( //
Status = WriteNvmeAdminSubmissionQueueBaseAddress (Private, &Asq);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -887,12 +883,12 @@ NvmeControllerInit ( //
Status = WriteNvmeAdminCompletionQueueBaseAddress (Private, &Acq);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
Status = NvmeEnableController (Private);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -900,7 +896,7 @@ NvmeControllerInit ( // Allocate buffer for Identify Controller data
//
if (Private->ControllerData == NULL) {
- Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA));
+ Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_CONTROLLER_DATA));
if (Private->ControllerData == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -912,8 +908,8 @@ NvmeControllerInit ( //
Status = NvmeIdentifyController (Private, Private->ControllerData);
- if (EFI_ERROR(Status)) {
- FreePool(Private->ControllerData);
+ if (EFI_ERROR (Status)) {
+ FreePool (Private->ControllerData);
Private->ControllerData = NULL;
return EFI_NOT_FOUND;
}
@@ -928,13 +924,13 @@ NvmeControllerInit ( DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
- DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
- DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
- DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
- DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64*)(Private->ControllerData->Tnvmcap + 8))));
- DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64*)Private->ControllerData->Tnvmcap)));
+ DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
+ DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
+ DEBUG ((DEBUG_INFO, " FR : 0x%x\n", *((UINT64 *)Private->ControllerData->Fr)));
+ DEBUG ((DEBUG_INFO, " TNVMCAP (high 8-byte) : 0x%lx\n", *((UINT64 *)(Private->ControllerData->Tnvmcap + 8))));
+ DEBUG ((DEBUG_INFO, " TNVMCAP (low 8-byte) : 0x%lx\n", *((UINT64 *)Private->ControllerData->Tnvmcap)));
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
- DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
+ DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32 *)Private->ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
@@ -945,8 +941,8 @@ NvmeControllerInit ( // One for blocking I/O, one for non-blocking I/O.
//
Status = NvmeCreateIoCompletionQueue (Private);
- if (EFI_ERROR(Status)) {
- return Status;
+ if (EFI_ERROR (Status)) {
+ return Status;
}
//
@@ -976,24 +972,24 @@ NvmeControllerInit ( VOID
EFIAPI
NvmeShutdownAllControllers (
- IN EFI_RESET_TYPE ResetType,
- IN EFI_STATUS ResetStatus,
- IN UINTN DataSize,
- IN VOID *ResetData OPTIONAL
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
)
{
- EFI_STATUS Status;
- EFI_HANDLE *Handles;
- UINTN HandleCount;
- UINTN HandleIndex;
- EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfos;
- UINTN OpenInfoCount;
- UINTN OpenInfoIndex;
- EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *NvmePassThru;
- NVME_CC Cc;
- NVME_CSTS Csts;
- UINTN Index;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN HandleCount;
+ UINTN HandleIndex;
+ EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfos;
+ UINTN OpenInfoCount;
+ UINTN OpenInfoIndex;
+ EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *NvmePassThru;
+ NVME_CC Cc;
+ NVME_CSTS Csts;
+ UINTN Index;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
Status = gBS->LocateHandleBuffer (
ByProtocol,
@@ -1023,11 +1019,12 @@ NvmeShutdownAllControllers ( // gImageHandle equals to DriverBinding handle for this driver.
//
if (((OpenInfos[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) != 0) &&
- (OpenInfos[OpenInfoIndex].AgentHandle == gImageHandle)) {
+ (OpenInfos[OpenInfoIndex].AgentHandle == gImageHandle))
+ {
Status = gBS->OpenProtocol (
OpenInfos[OpenInfoIndex].ControllerHandle,
&gEfiNvmExpressPassThruProtocolGuid,
- (VOID **) &NvmePassThru,
+ (VOID **)&NvmePassThru,
NULL,
NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1035,22 +1032,24 @@ NvmeShutdownAllControllers ( if (EFI_ERROR (Status)) {
continue;
}
+
Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (NvmePassThru);
//
// Read Controller Configuration Register.
//
Status = ReadNvmeControllerConfiguration (Private, &Cc);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
continue;
}
+
//
// The host should set the Shutdown Notification (CC.SHN) field to 01b
// to indicate a normal shutdown operation.
//
Cc.Shn = NVME_CC_SHN_NORMAL_SHUTDOWN;
Status = WriteNvmeControllerConfiguration (Private, &Cc);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
continue;
}
@@ -1061,10 +1060,11 @@ NvmeShutdownAllControllers ( //
for (Index = 0; Index < NVME_SHUTDOWN_PROCESS_TIMEOUT * 100; Index++) {
Status = ReadNvmeControllerStatus (Private, &Csts);
- if (!EFI_ERROR(Status) && (Csts.Shst == NVME_CSTS_SHST_SHUTDOWN_COMPLETED)) {
- DEBUG((DEBUG_INFO, "NvmeShutdownController: shutdown processing is completed after %dms.\n", Index * 10));
+ if (!EFI_ERROR (Status) && (Csts.Shst == NVME_CSTS_SHST_SHUTDOWN_COMPLETED)) {
+ DEBUG ((DEBUG_INFO, "NvmeShutdownController: shutdown processing is completed after %dms.\n", Index * 10));
break;
}
+
//
// Stall for 10ms
//
@@ -1072,7 +1072,7 @@ NvmeShutdownAllControllers ( }
if (Index == NVME_SHUTDOWN_PROCESS_TIMEOUT * 100) {
- DEBUG((DEBUG_ERROR, "NvmeShutdownController: shutdown processing is timed out\n"));
+ DEBUG ((DEBUG_ERROR, "NvmeShutdownController: shutdown processing is timed out\n"));
}
}
}
@@ -1089,12 +1089,12 @@ NvmeRegisterShutdownNotification ( VOID
)
{
- EFI_STATUS Status;
- EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
+ EFI_STATUS Status;
+ EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
mNvmeControllerNumber++;
if (mNvmeControllerNumber == 1) {
- Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **) &ResetNotify);
+ Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **)&ResetNotify);
if (!EFI_ERROR (Status)) {
Status = ResetNotify->RegisterResetNotify (ResetNotify, NvmeShutdownAllControllers);
ASSERT_EFI_ERROR (Status);
@@ -1114,12 +1114,12 @@ NvmeUnregisterShutdownNotification ( VOID
)
{
- EFI_STATUS Status;
- EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
+ EFI_STATUS Status;
+ EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
mNvmeControllerNumber--;
if (mNvmeControllerNumber == 0) {
- Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **) &ResetNotify);
+ Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **)&ResetNotify);
if (!EFI_ERROR (Status)) {
Status = ResetNotify->UnregisterResetNotify (ResetNotify, NvmeShutdownAllControllers);
ASSERT_EFI_ERROR (Status);
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h index 60b3770580..a08c4e974e 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h @@ -11,12 +11,12 @@ #ifndef _NVME_HCI_H_
#define _NVME_HCI_H_
-#define NVME_BAR 0
+#define NVME_BAR 0
//
// Offset from the beginning of private data queue buffer
//
-#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
+#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
/**
Initialize the Nvm Express controller.
@@ -29,7 +29,7 @@ **/
EFI_STATUS
NvmeControllerInit (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
);
/**
@@ -44,8 +44,8 @@ NvmeControllerInit ( **/
EFI_STATUS
NvmeIdentifyController (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN VOID *Buffer
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN VOID *Buffer
);
/**
@@ -61,10 +61,9 @@ NvmeIdentifyController ( **/
EFI_STATUS
NvmeIdentifyNamespace (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN VOID *Buffer
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN VOID *Buffer
);
#endif
-
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c index a46a098258..f37baa626a 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c @@ -18,7 +18,7 @@ **/
VOID
NvmeDumpStatus (
- IN NVME_CQ *Cq
+ IN NVME_CQ *Cq
)
{
DEBUG ((DEBUG_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
@@ -97,6 +97,7 @@ NvmeDumpStatus ( DEBUG ((DEBUG_VERBOSE, "Reservation Conflict\n"));
break;
}
+
break;
case 0x1:
@@ -159,6 +160,7 @@ NvmeDumpStatus ( DEBUG ((DEBUG_VERBOSE, "Attempted Write to Read Only Range\n"));
break;
}
+
break;
case 0x2:
@@ -185,6 +187,7 @@ NvmeDumpStatus ( DEBUG ((DEBUG_VERBOSE, "Access Denied\n"));
break;
}
+
break;
default:
@@ -206,24 +209,24 @@ NvmeDumpStatus ( @retval The pointer to the first PRP List of the PRP lists.
**/
-VOID*
+VOID *
NvmeCreatePrpList (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
- IN UINTN Pages,
- OUT VOID **PrpListHost,
- IN OUT UINTN *PrpListNo,
- OUT VOID **Mapping
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
+ IN UINTN Pages,
+ OUT VOID **PrpListHost,
+ IN OUT UINTN *PrpListNo,
+ OUT VOID **Mapping
)
{
- UINTN PrpEntryNo;
- UINT64 PrpListBase;
- UINTN PrpListIndex;
- UINTN PrpEntryIndex;
- UINT64 Remainder;
- EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
- UINTN Bytes;
- EFI_STATUS Status;
+ UINTN PrpEntryNo;
+ UINT64 PrpListBase;
+ UINTN PrpListIndex;
+ UINTN PrpEntryIndex;
+ UINT64 Remainder;
+ EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
+ UINTN Bytes;
+ EFI_STATUS Status;
//
// The number of Prp Entry in a memory page.
@@ -257,7 +260,7 @@ NvmeCreatePrpList ( return NULL;
}
- Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
+ Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -271,45 +274,46 @@ NvmeCreatePrpList ( DEBUG ((DEBUG_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
goto EXIT;
}
+
//
// Fill all PRP lists except of last one.
//
ZeroMem (*PrpListHost, Bytes);
for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
- PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
+ PrpListBase = *(UINT64 *)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
if (PrpEntryIndex != PrpEntryNo - 1) {
//
// Fill all PRP entries except of last one.
//
- *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
- PhysicalAddr += EFI_PAGE_SIZE;
+ *((UINT64 *)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
+ PhysicalAddr += EFI_PAGE_SIZE;
} else {
//
// Fill last PRP entries with next PRP List pointer.
//
- *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
+ *((UINT64 *)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
}
}
}
+
//
// Fill last PRP list.
//
- PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
+ PrpListBase = *(UINT64 *)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {
- *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
- PhysicalAddr += EFI_PAGE_SIZE;
+ *((UINT64 *)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
+ PhysicalAddr += EFI_PAGE_SIZE;
}
- return (VOID*)(UINTN)PrpListPhyAddr;
+ return (VOID *)(UINTN)PrpListPhyAddr;
EXIT:
PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
return NULL;
}
-
/**
Aborts the asynchronous PassThru requests.
@@ -322,18 +326,18 @@ EXIT: **/
EFI_STATUS
AbortAsyncPassThruTasks (
- IN NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- NVME_BLKIO2_SUBTASK *Subtask;
- NVME_BLKIO2_REQUEST *BlkIo2Request;
- NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
- EFI_BLOCK_IO2_TOKEN *Token;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ LIST_ENTRY *Link;
+ LIST_ENTRY *NextLink;
+ NVME_BLKIO2_SUBTASK *Subtask;
+ NVME_BLKIO2_REQUEST *BlkIo2Request;
+ NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
+ EFI_BLOCK_IO2_TOKEN *Token;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
PciIo = Private->PciIo;
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
@@ -343,7 +347,8 @@ AbortAsyncPassThruTasks ( //
for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);
!IsNull (&Private->UnsubmittedSubtasks, Link);
- Link = NextLink) {
+ Link = NextLink)
+ {
NextLink = GetNextNode (&Private->UnsubmittedSubtasks, Link);
Subtask = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);
BlkIo2Request = Subtask->BlockIo2Request;
@@ -353,6 +358,7 @@ AbortAsyncPassThruTasks ( if (Subtask->IsLast) {
BlkIo2Request->LastSubtaskSubmitted = TRUE;
}
+
Token->TransactionStatus = EFI_ABORTED;
RemoveEntryList (Link);
@@ -365,19 +371,23 @@ AbortAsyncPassThruTasks ( //
for (Link = GetFirstNode (&Private->AsyncPassThruQueue);
!IsNull (&Private->AsyncPassThruQueue, Link);
- Link = NextLink) {
- NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
+ Link = NextLink)
+ {
+ NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);
if (AsyncRequest->MapData != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapData);
}
+
if (AsyncRequest->MapMeta != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapMeta);
}
+
if (AsyncRequest->MapPrpList != NULL) {
PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);
}
+
if (AsyncRequest->PrpListHost != NULL) {
PciIo->FreeBuffer (
PciIo,
@@ -392,7 +402,8 @@ AbortAsyncPassThruTasks ( }
if (IsListEmpty (&Private->AsyncPassThruQueue) &&
- IsListEmpty (&Private->UnsubmittedSubtasks)) {
+ IsListEmpty (&Private->UnsubmittedSubtasks))
+ {
Status = EFI_SUCCESS;
} else {
Status = EFI_DEVICE_ERROR;
@@ -403,7 +414,6 @@ AbortAsyncPassThruTasks ( return Status;
}
-
/**
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
@@ -439,10 +449,10 @@ AbortAsyncPassThruTasks ( EFI_STATUS
EFIAPI
NvmExpressPassThru (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN UINT32 NamespaceId,
- IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
- IN EFI_EVENT Event OPTIONAL
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
)
{
NVME_CONTROLLER_PRIVATE_DATA *Private;
@@ -483,7 +493,7 @@ NvmExpressPassThru ( return EFI_INVALID_PARAMETER;
}
- if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
+ if ((Packet->QueueType != NVME_ADMIN_QUEUE) && (Packet->QueueType != NVME_IO_QUEUE)) {
return EFI_INVALID_PARAMETER;
}
@@ -492,31 +502,33 @@ NvmExpressPassThru ( // EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal
// configuration.
//
- Attributes = This->Mode->Attributes;
+ Attributes = This->Mode->Attributes;
if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
- EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {
+ EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0)
+ {
return EFI_INVALID_PARAMETER;
}
//
// Buffer alignment check for TransferBuffer & MetadataBuffer.
//
- IoAlign = This->Mode->IoAlign;
- if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
+ IoAlign = This->Mode->IoAlign;
+ if ((IoAlign > 0) && (((UINTN)Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
- if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
+ if ((IoAlign > 0) && (((UINTN)Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
return EFI_INVALID_PARAMETER;
}
- Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
+ Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
//
// Check NamespaceId is valid or not.
//
if ((NamespaceId > Private->ControllerData->Nn) &&
- (NamespaceId != (UINT32) -1)) {
+ (NamespaceId != (UINT32)-1))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -555,13 +567,15 @@ NvmExpressPassThru ( // Submission queue full check.
//
if ((Private->SqTdbl[QueueId].Sqt + 1) % QueueSize ==
- Private->AsyncSqHead) {
+ Private->AsyncSqHead)
+ {
return EFI_NOT_READY;
}
}
}
- Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
- Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
+
+ Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
+ Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
if (Packet->NvmeCmd->Nsid != NamespaceId) {
return EFI_INVALID_PARAMETER;
@@ -584,7 +598,8 @@ NvmExpressPassThru ( Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
if ((Packet->QueueType == NVME_ADMIN_QUEUE) &&
- ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD))) {
+ ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))
+ {
//
// Currently, we only use the IO Completion/Submission queues created internally
// by this driver during controller initialization. Any other IO queues created
@@ -601,7 +616,8 @@ NvmExpressPassThru ( // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
//
if (((Packet->TransferLength != 0) && (Packet->TransferBuffer == NULL)) ||
- ((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL))) {
+ ((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL)))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -613,14 +629,14 @@ NvmExpressPassThru ( if ((Packet->TransferLength != 0) && (Packet->TransferBuffer != NULL)) {
MapLength = Packet->TransferLength;
- Status = PciIo->Map (
- PciIo,
- Flag,
- Packet->TransferBuffer,
- &MapLength,
- &PhyAddr,
- &MapData
- );
+ Status = PciIo->Map (
+ PciIo,
+ Flag,
+ Packet->TransferBuffer,
+ &MapLength,
+ &PhyAddr,
+ &MapData
+ );
if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
return EFI_OUT_OF_RESOURCES;
}
@@ -629,16 +645,16 @@ NvmExpressPassThru ( Sq->Prp[1] = 0;
}
- if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
+ if ((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
MapLength = Packet->MetadataLength;
- Status = PciIo->Map (
- PciIo,
- Flag,
- Packet->MetadataBuffer,
- &MapLength,
- &PhyAddr,
- &MapMeta
- );
+ Status = PciIo->Map (
+ PciIo,
+ Flag,
+ Packet->MetadataBuffer,
+ &MapLength,
+ &PhyAddr,
+ &MapMeta
+ );
if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
PciIo->Unmap (
PciIo,
@@ -647,9 +663,11 @@ NvmExpressPassThru ( return EFI_OUT_OF_RESOURCES;
}
+
Sq->Mptr = PhyAddr;
}
}
+
//
// If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
// then build a PRP list in the second PRP submission queue entry.
@@ -662,7 +680,7 @@ NvmExpressPassThru ( // Create PrpList for remaining data buffer.
//
PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
- Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
+ Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES (Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
if (Prp == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto EXIT;
@@ -673,28 +691,35 @@ NvmExpressPassThru ( Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
}
- if(Packet->NvmeCmd->Flags & CDW2_VALID) {
+ if (Packet->NvmeCmd->Flags & CDW2_VALID) {
Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;
}
- if(Packet->NvmeCmd->Flags & CDW3_VALID) {
+
+ if (Packet->NvmeCmd->Flags & CDW3_VALID) {
Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);
}
- if(Packet->NvmeCmd->Flags & CDW10_VALID) {
+
+ if (Packet->NvmeCmd->Flags & CDW10_VALID) {
Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
}
- if(Packet->NvmeCmd->Flags & CDW11_VALID) {
+
+ if (Packet->NvmeCmd->Flags & CDW11_VALID) {
Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
}
- if(Packet->NvmeCmd->Flags & CDW12_VALID) {
+
+ if (Packet->NvmeCmd->Flags & CDW12_VALID) {
Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
}
- if(Packet->NvmeCmd->Flags & CDW13_VALID) {
+
+ if (Packet->NvmeCmd->Flags & CDW13_VALID) {
Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
}
- if(Packet->NvmeCmd->Flags & CDW14_VALID) {
+
+ if (Packet->NvmeCmd->Flags & CDW14_VALID) {
Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
}
- if(Packet->NvmeCmd->Flags & CDW15_VALID) {
+
+ if (Packet->NvmeCmd->Flags & CDW15_VALID) {
Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
}
@@ -707,15 +732,16 @@ NvmExpressPassThru ( } else {
Private->SqTdbl[QueueId].Sqt ^= 1;
}
- Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
+
+ Data = ReadUnaligned32 ((UINT32 *)&Private->SqTdbl[QueueId]);
Status = PciIo->Mem.Write (
- PciIo,
- EfiPciIoWidthUint32,
- NVME_BAR,
- NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),
- 1,
- &Data
- );
+ PciIo,
+ EfiPciIoWidthUint32,
+ NVME_BAR,
+ NVME_SQTDBL_OFFSET (QueueId, Private->Cap.Dstrd),
+ 1,
+ &Data
+ );
if (EFI_ERROR (Status)) {
goto EXIT;
@@ -732,15 +758,15 @@ NvmExpressPassThru ( goto EXIT;
}
- AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;
- AsyncRequest->Packet = Packet;
- AsyncRequest->CommandId = Sq->Cid;
- AsyncRequest->CallerEvent = Event;
- AsyncRequest->MapData = MapData;
- AsyncRequest->MapMeta = MapMeta;
- AsyncRequest->MapPrpList = MapPrpList;
- AsyncRequest->PrpListNo = PrpListNo;
- AsyncRequest->PrpListHost = PrpListHost;
+ AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;
+ AsyncRequest->Packet = Packet;
+ AsyncRequest->CommandId = Sq->Cid;
+ AsyncRequest->CallerEvent = Event;
+ AsyncRequest->MapData = MapData;
+ AsyncRequest->MapMeta = MapMeta;
+ AsyncRequest->MapPrpList = MapPrpList;
+ AsyncRequest->PrpListNo = PrpListNo;
+ AsyncRequest->PrpListHost = PrpListHost;
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);
@@ -760,9 +786,9 @@ NvmExpressPassThru ( goto EXIT;
}
- Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
+ Status = gBS->SetTimer (TimerEvent, TimerRelative, Packet->CommandTimeout);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto EXIT;
}
@@ -788,14 +814,15 @@ NvmExpressPassThru ( //
// Dump every completion entry status for debugging.
//
- DEBUG_CODE_BEGIN();
- NvmeDumpStatus(Cq);
- DEBUG_CODE_END();
+ DEBUG_CODE_BEGIN ();
+ NvmeDumpStatus (Cq);
+ DEBUG_CODE_END ();
}
+
//
// Copy the Respose Queue entry for this command to the callers response buffer
//
- CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ CopyMem (Packet->NvmeCompletion, Cq, sizeof (EFI_NVM_EXPRESS_COMPLETION));
} else {
//
// Timeout occurs for an NVMe command. Reset the controller to abort the
@@ -840,16 +867,16 @@ NvmExpressPassThru ( Private->Pt[QueueId] ^= 1;
}
- Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
+ Data = ReadUnaligned32 ((UINT32 *)&Private->CqHdbl[QueueId]);
PreviousStatus = Status;
- Status = PciIo->Mem.Write (
- PciIo,
- EfiPciIoWidthUint32,
- NVME_BAR,
- NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
- 1,
- &Data
- );
+ Status = PciIo->Mem.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ NVME_BAR,
+ NVME_CQHDBL_OFFSET (QueueId, Private->Cap.Dstrd),
+ 1,
+ &Data
+ );
// The return status of PciIo->Mem.Write should not override
// previous status if previous status contains error.
Status = EFI_ERROR (PreviousStatus) ? PreviousStatus : Status;
@@ -892,6 +919,7 @@ EXIT: if (TimerEvent != NULL) {
gBS->CloseEvent (TimerEvent);
}
+
return Status;
}
@@ -931,14 +959,14 @@ EXIT: EFI_STATUS
EFIAPI
NvmExpressGetNextNamespace (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN OUT UINT32 *NamespaceId
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT32 *NamespaceId
)
{
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
- UINT32 NextNamespaceId;
- EFI_STATUS Status;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
+ UINT32 NextNamespaceId;
+ EFI_STATUS Status;
if ((This == NULL) || (NamespaceId == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -966,7 +994,7 @@ NvmExpressGetNextNamespace ( }
Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto Done;
}
@@ -990,7 +1018,7 @@ NvmExpressGetNextNamespace ( }
Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto Done;
}
@@ -999,7 +1027,7 @@ NvmExpressGetNextNamespace ( Done:
if (NamespaceData != NULL) {
- FreePool(NamespaceData);
+ FreePool (NamespaceData);
}
return Status;
@@ -1032,13 +1060,13 @@ Done: EFI_STATUS
EFIAPI
NvmExpressGetNamespace (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINT32 *NamespaceId
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT32 *NamespaceId
)
{
- NVME_NAMESPACE_DEVICE_PATH *Node;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
+ NVME_NAMESPACE_DEVICE_PATH *Node;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1052,7 +1080,7 @@ NvmExpressGetNamespace ( Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
- if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
+ if (DevicePathNodeLength (DevicePath) != sizeof (NVME_NAMESPACE_DEVICE_PATH)) {
return EFI_NOT_FOUND;
}
@@ -1060,7 +1088,8 @@ NvmExpressGetNamespace ( // Check NamespaceId in the device path node is valid or not.
//
if ((Node->NamespaceId == 0) ||
- (Node->NamespaceId > Private->ControllerData->Nn)) {
+ (Node->NamespaceId > Private->ControllerData->Nn))
+ {
return EFI_NOT_FOUND;
}
@@ -1106,15 +1135,15 @@ NvmExpressGetNamespace ( EFI_STATUS
EFIAPI
NvmExpressBuildDevicePath (
- IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
- IN UINT32 NamespaceId,
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
- NVME_NAMESPACE_DEVICE_PATH *Node;
- NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_STATUS Status;
- NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
+ NVME_NAMESPACE_DEVICE_PATH *Node;
+ NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
+ NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
//
// Validate parameters
@@ -1130,7 +1159,8 @@ NvmExpressBuildDevicePath ( // Check NamespaceId is valid or not.
//
if ((NamespaceId == 0) ||
- (NamespaceId > Private->ControllerData->Nn)) {
+ (NamespaceId > Private->ControllerData->Nn))
+ {
return EFI_NOT_FOUND;
}
@@ -1142,14 +1172,14 @@ NvmExpressBuildDevicePath ( Node->Header.Type = MESSAGING_DEVICE_PATH;
Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
- Node->NamespaceId = NamespaceId;
+ Node->NamespaceId = NamespaceId;
//
// Allocate a buffer for Identify Namespace data.
//
NamespaceData = NULL;
- NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
- if(NamespaceData == NULL) {
+ NamespaceData = AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
+ if (NamespaceData == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
}
@@ -1163,7 +1193,7 @@ NvmExpressBuildDevicePath ( (VOID *)NamespaceData
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto Exit;
}
@@ -1172,7 +1202,7 @@ NvmExpressBuildDevicePath ( *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
Exit:
- if(NamespaceData != NULL) {
+ if (NamespaceData != NULL) {
FreePool (NamespaceData);
}
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/DevicePath.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/DevicePath.c index 6f9ff4b7dd..9b454a7dd8 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/DevicePath.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/DevicePath.c @@ -17,8 +17,8 @@ NVME_NAMESPACE_DEVICE_PATH mNvmeDevicePathNodeTemplate = { MESSAGING_DEVICE_PATH,
MSG_NVME_NAMESPACE_DP,
{
- (UINT8) (sizeof (NVME_NAMESPACE_DEVICE_PATH)),
- (UINT8) ((sizeof (NVME_NAMESPACE_DEVICE_PATH)) >> 8)
+ (UINT8)(sizeof (NVME_NAMESPACE_DEVICE_PATH)),
+ (UINT8)((sizeof (NVME_NAMESPACE_DEVICE_PATH)) >> 8)
}
},
0x0, // NamespaceId
@@ -32,8 +32,8 @@ EFI_DEVICE_PATH_PROTOCOL mNvmeEndDevicePathNodeTemplate = { END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{
- (UINT8) (sizeof (EFI_DEVICE_PATH_PROTOCOL)),
- (UINT8) ((sizeof (EFI_DEVICE_PATH_PROTOCOL)) >> 8)
+ (UINT8)(sizeof (EFI_DEVICE_PATH_PROTOCOL)),
+ (UINT8)((sizeof (EFI_DEVICE_PATH_PROTOCOL)) >> 8)
}
};
@@ -78,7 +78,7 @@ NextDevicePathNode ( )
{
ASSERT (Node != NULL);
- return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength(Node));
+ return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength (Node));
}
/**
@@ -96,14 +96,14 @@ NextDevicePathNode ( **/
EFI_STATUS
GetDevicePathInstanceSize (
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINTN *InstanceSize,
- OUT BOOLEAN *EntireDevicePathEnd
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINTN *InstanceSize,
+ OUT BOOLEAN *EntireDevicePathEnd
)
{
- EFI_DEVICE_PATH_PROTOCOL *Walker;
+ EFI_DEVICE_PATH_PROTOCOL *Walker;
- if (DevicePath == NULL || InstanceSize == NULL || EntireDevicePathEnd == NULL) {
+ if ((DevicePath == NULL) || (InstanceSize == NULL) || (EntireDevicePathEnd == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -129,7 +129,7 @@ GetDevicePathInstanceSize ( //
// Compute the size of the device path instance
//
- *InstanceSize = ((UINTN) Walker - (UINTN) (DevicePath)) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
+ *InstanceSize = ((UINTN)Walker - (UINTN)(DevicePath)) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
return EFI_SUCCESS;
}
@@ -147,12 +147,12 @@ GetDevicePathInstanceSize ( **/
EFI_STATUS
NvmeIsHcDevicePathValid (
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- IN UINTN DevicePathLength
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN UINTN DevicePathLength
)
{
- EFI_DEVICE_PATH_PROTOCOL *Start;
- UINTN Size;
+ EFI_DEVICE_PATH_PROTOCOL *Start;
+ UINTN Size;
if (DevicePath == NULL) {
return EFI_INVALID_PARAMETER;
@@ -167,22 +167,24 @@ NvmeIsHcDevicePathValid ( Start = DevicePath;
while (!(DevicePath->Type == END_DEVICE_PATH_TYPE &&
- DevicePath->SubType == END_ENTIRE_DEVICE_PATH_SUBTYPE)) {
+ DevicePath->SubType == END_ENTIRE_DEVICE_PATH_SUBTYPE))
+ {
DevicePath = NextDevicePathNode (DevicePath);
//
// Prevent overflow and invalid zero in the 'Length' field of a device path
// node.
//
- if ((UINTN) DevicePath <= (UINTN) Start) {
+ if ((UINTN)DevicePath <= (UINTN)Start) {
return EFI_INVALID_PARAMETER;
}
//
// Prevent touching memory beyond given DevicePathLength.
//
- if ((UINTN) DevicePath - (UINTN) Start >
- DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)) {
+ if ((UINTN)DevicePath - (UINTN)Start >
+ DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL))
+ {
return EFI_INVALID_PARAMETER;
}
}
@@ -190,7 +192,7 @@ NvmeIsHcDevicePathValid ( //
// Check if the device path and its size match exactly with each other.
//
- Size = ((UINTN) DevicePath - (UINTN) Start) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
+ Size = ((UINTN)DevicePath - (UINTN)Start) + sizeof (EFI_DEVICE_PATH_PROTOCOL);
if (Size != DevicePathLength) {
return EFI_INVALID_PARAMETER;
}
@@ -217,17 +219,17 @@ NvmeIsHcDevicePathValid ( **/
EFI_STATUS
NvmeBuildDevicePath (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN UINT64 NamespaceUuid,
- OUT UINTN *DevicePathLength,
- OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN UINT64 NamespaceUuid,
+ OUT UINTN *DevicePathLength,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
- EFI_DEVICE_PATH_PROTOCOL *DevicePathWalker;
- NVME_NAMESPACE_DEVICE_PATH *NvmeDeviceNode;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathWalker;
+ NVME_NAMESPACE_DEVICE_PATH *NvmeDeviceNode;
- if (DevicePathLength == NULL || DevicePath == NULL) {
+ if ((DevicePathLength == NULL) || (DevicePath == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -251,8 +253,8 @@ NvmeBuildDevicePath ( //
// Construct the Nvm Express device node
//
- DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *) ((UINT8 *)DevicePathWalker +
- (Private->DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)));
+ DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)DevicePathWalker +
+ (Private->DevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)));
CopyMem (
DevicePathWalker,
&mNvmeDevicePathNodeTemplate,
@@ -265,8 +267,8 @@ NvmeBuildDevicePath ( //
// Construct the end device node
//
- DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *) ((UINT8 *)DevicePathWalker +
- sizeof (NVME_NAMESPACE_DEVICE_PATH));
+ DevicePathWalker = (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)DevicePathWalker +
+ sizeof (NVME_NAMESPACE_DEVICE_PATH));
CopyMem (
DevicePathWalker,
&mNvmeEndDevicePathNodeTemplate,
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/DmaMem.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/DmaMem.c index 7b049b9e4a..36bebc5bc1 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/DmaMem.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/DmaMem.c @@ -20,15 +20,15 @@ GetIoMmu ( VOID
)
{
- EFI_STATUS Status;
- EDKII_IOMMU_PPI *IoMmu;
+ EFI_STATUS Status;
+ EDKII_IOMMU_PPI *IoMmu;
IoMmu = NULL;
Status = PeiServicesLocatePpi (
&gEdkiiIoMmuPpiGuid,
0,
NULL,
- (VOID **) &IoMmu
+ (VOID **)&IoMmu
);
if (!EFI_ERROR (Status) && (IoMmu != NULL)) {
return IoMmu;
@@ -58,48 +58,50 @@ GetIoMmu ( **/
EFI_STATUS
IoMmuMap (
- IN EDKII_IOMMU_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ IN EDKII_IOMMU_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- UINT64 Attribute;
- EDKII_IOMMU_PPI *IoMmu;
+ EFI_STATUS Status;
+ UINT64 Attribute;
+ EDKII_IOMMU_PPI *IoMmu;
IoMmu = GetIoMmu ();
if (IoMmu != NULL) {
Status = IoMmu->Map (
- IoMmu,
- Operation,
- HostAddress,
- NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+ IoMmu,
+ Operation,
+ HostAddress,
+ NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
switch (Operation) {
- case EdkiiIoMmuOperationBusMasterRead:
- case EdkiiIoMmuOperationBusMasterRead64:
- Attribute = EDKII_IOMMU_ACCESS_READ;
- break;
- case EdkiiIoMmuOperationBusMasterWrite:
- case EdkiiIoMmuOperationBusMasterWrite64:
- Attribute = EDKII_IOMMU_ACCESS_WRITE;
- break;
- case EdkiiIoMmuOperationBusMasterCommonBuffer:
- case EdkiiIoMmuOperationBusMasterCommonBuffer64:
- Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
- break;
- default:
- ASSERT(FALSE);
- return EFI_INVALID_PARAMETER;
+ case EdkiiIoMmuOperationBusMasterRead:
+ case EdkiiIoMmuOperationBusMasterRead64:
+ Attribute = EDKII_IOMMU_ACCESS_READ;
+ break;
+ case EdkiiIoMmuOperationBusMasterWrite:
+ case EdkiiIoMmuOperationBusMasterWrite64:
+ Attribute = EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ case EdkiiIoMmuOperationBusMasterCommonBuffer:
+ case EdkiiIoMmuOperationBusMasterCommonBuffer64:
+ Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -110,9 +112,10 @@ IoMmuMap ( }
} else {
*DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
- *Mapping = NULL;
- Status = EFI_SUCCESS;
+ *Mapping = NULL;
+ Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -127,11 +130,11 @@ IoMmuMap ( **/
EFI_STATUS
IoMmuUnmap (
- IN VOID *Mapping
+ IN VOID *Mapping
)
{
- EFI_STATUS Status;
- EDKII_IOMMU_PPI *IoMmu;
+ EFI_STATUS Status;
+ EDKII_IOMMU_PPI *IoMmu;
IoMmu = GetIoMmu ();
@@ -141,6 +144,7 @@ IoMmuUnmap ( } else {
Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -175,7 +179,7 @@ IoMmuAllocateBuffer ( EFI_PHYSICAL_ADDRESS HostPhyAddress;
EDKII_IOMMU_PPI *IoMmu;
- *HostAddress = NULL;
+ *HostAddress = NULL;
*DeviceAddress = 0;
IoMmu = GetIoMmu ();
@@ -192,18 +196,19 @@ IoMmuAllocateBuffer ( return EFI_OUT_OF_RESOURCES;
}
- NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);
- Status = IoMmu->Map (
- IoMmu,
- EdkiiIoMmuOperationBusMasterCommonBuffer,
- *HostAddress,
- &NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+ NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
+ Status = IoMmu->Map (
+ IoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ *HostAddress,
+ &NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -221,10 +226,12 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *)(UINTN)HostPhyAddress;
+
+ *HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
- *Mapping = NULL;
+ *Mapping = NULL;
}
+
return Status;
}
@@ -242,13 +249,13 @@ IoMmuAllocateBuffer ( **/
EFI_STATUS
IoMmuFreeBuffer (
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
)
{
- EFI_STATUS Status;
- EDKII_IOMMU_PPI *IoMmu;
+ EFI_STATUS Status;
+ EDKII_IOMMU_PPI *IoMmu;
IoMmu = GetIoMmu ();
@@ -259,5 +266,6 @@ IoMmuFreeBuffer ( } else {
Status = EFI_SUCCESS;
}
+
return Status;
}
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c index a8cb7f3a67..f73053fc3f 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c @@ -53,19 +53,19 @@ EFI_PEI_NOTIFY_DESCRIPTOR mNvmeEndOfPeiNotifyListTemplate = { **/
EFI_STATUS
EnumerateNvmeDevNamespace (
- IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId
+ IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId
)
{
- EFI_STATUS Status;
- NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
- PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
- UINT32 DeviceIndex;
- UINT32 Lbads;
- UINT32 Flbas;
- UINT32 LbaFmtIdx;
-
- NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *) AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
+ EFI_STATUS Status;
+ NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
+ PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
+ UINT32 DeviceIndex;
+ UINT32 Lbads;
+ UINT32 Flbas;
+ UINT32 LbaFmtIdx;
+
+ NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
if (NamespaceData == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -92,8 +92,8 @@ EnumerateNvmeDevNamespace ( goto Exit;
}
- DeviceIndex = Private->ActiveNamespaceNum;
- NamespaceInfo = &Private->NamespaceInfo[DeviceIndex];
+ DeviceIndex = Private->ActiveNamespaceNum;
+ NamespaceInfo = &Private->NamespaceInfo[DeviceIndex];
NamespaceInfo->NamespaceId = NamespaceId;
NamespaceInfo->NamespaceUuid = NamespaceData->Eui64;
NamespaceInfo->Controller = Private;
@@ -110,8 +110,8 @@ EnumerateNvmeDevNamespace ( NamespaceInfo->Media.RemovableMedia = FALSE;
NamespaceInfo->Media.MediaPresent = TRUE;
NamespaceInfo->Media.ReadOnly = FALSE;
- NamespaceInfo->Media.BlockSize = (UINT32) 1 << Lbads;
- NamespaceInfo->Media.LastBlock = (EFI_PEI_LBA) NamespaceData->Nsze - 1;
+ NamespaceInfo->Media.BlockSize = (UINT32)1 << Lbads;
+ NamespaceInfo->Media.LastBlock = (EFI_PEI_LBA)NamespaceData->Nsze - 1;
DEBUG ((
DEBUG_INFO,
"%a: Namespace ID %d - BlockSize = 0x%x, LastBlock = 0x%lx\n",
@@ -140,10 +140,10 @@ Exit: **/
EFI_STATUS
NvmeDiscoverNamespaces (
- IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- UINT32 NamespaceId;
+ UINT32 NamespaceId;
Private->ActiveNamespaceNum = 0;
Private->NamespaceInfo = AllocateZeroPool (Private->ControllerData->Nn * sizeof (PEI_NVME_NAMESPACE_INFO));
@@ -161,6 +161,7 @@ NvmeDiscoverNamespaces ( //
EnumerateNvmeDevNamespace (Private, NamespaceId);
}
+
if (Private->ActiveNamespaceNum == 0) {
return EFI_NOT_FOUND;
}
@@ -187,7 +188,7 @@ NvmePeimEndOfPei ( IN VOID *Ppi
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY (NotifyDescriptor);
NvmeFreeDmaResource (Private);
@@ -207,19 +208,19 @@ NvmePeimEndOfPei ( EFI_STATUS
EFIAPI
NvmExpressPeimEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
- EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI *NvmeHcPpi;
- UINT8 Controller;
- UINTN MmioBase;
- UINTN DevicePathLength;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_PHYSICAL_ADDRESS DeviceAddress;
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI *NvmeHcPpi;
+ UINT8 Controller;
+ UINTN MmioBase;
+ UINTN DevicePathLength;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_PHYSICAL_ADDRESS DeviceAddress;
DEBUG ((DEBUG_INFO, "%a: Enters.\n", __FUNCTION__));
@@ -239,7 +240,7 @@ NvmExpressPeimEntry ( &gEdkiiPeiNvmExpressHostControllerPpiGuid,
0,
NULL,
- (VOID **) &NvmeHcPpi
+ (VOID **)&NvmeHcPpi
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Fail to locate NvmeHostControllerPpi.\n", __FUNCTION__));
@@ -269,8 +270,10 @@ NvmExpressPeimEntry ( );
if (EFI_ERROR (Status)) {
DEBUG ((
- DEBUG_ERROR, "%a: Fail to allocate get the device path for Controller %d.\n",
- __FUNCTION__, Controller
+ DEBUG_ERROR,
+ "%a: Fail to allocate get the device path for Controller %d.\n",
+ __FUNCTION__,
+ Controller
));
return Status;
}
@@ -281,8 +284,10 @@ NvmExpressPeimEntry ( Status = NvmeIsHcDevicePathValid (DevicePath, DevicePathLength);
if (EFI_ERROR (Status)) {
DEBUG ((
- DEBUG_ERROR, "%a: The device path is invalid for Controller %d.\n",
- __FUNCTION__, Controller
+ DEBUG_ERROR,
+ "%a: The device path is invalid for Controller %d.\n",
+ __FUNCTION__,
+ Controller
));
Controller++;
continue;
@@ -295,10 +300,13 @@ NvmExpressPeimEntry ( // during S3 resume.
//
if ((BootMode == BOOT_ON_S3_RESUME) &&
- (NvmeS3SkipThisController (DevicePath, DevicePathLength))) {
+ (NvmeS3SkipThisController (DevicePath, DevicePathLength)))
+ {
DEBUG ((
- DEBUG_ERROR, "%a: Controller %d is skipped during S3.\n",
- __FUNCTION__, Controller
+ DEBUG_ERROR,
+ "%a: Controller %d is skipped during S3.\n",
+ __FUNCTION__,
+ Controller
));
Controller++;
continue;
@@ -310,8 +318,10 @@ NvmExpressPeimEntry ( Private = AllocateZeroPool (sizeof (PEI_NVME_CONTROLLER_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((
- DEBUG_ERROR, "%a: Fail to allocate private data for Controller %d.\n",
- __FUNCTION__, Controller
+ DEBUG_ERROR,
+ "%a: Fail to allocate private data for Controller %d.\n",
+ __FUNCTION__,
+ Controller
));
return EFI_OUT_OF_RESOURCES;
}
@@ -327,12 +337,15 @@ NvmExpressPeimEntry ( );
if (EFI_ERROR (Status)) {
DEBUG ((
- DEBUG_ERROR, "%a: Fail to allocate DMA buffers for Controller %d.\n",
- __FUNCTION__, Controller
+ DEBUG_ERROR,
+ "%a: Fail to allocate DMA buffers for Controller %d.\n",
+ __FUNCTION__,
+ Controller
));
return Status;
}
- ASSERT (DeviceAddress == ((EFI_PHYSICAL_ADDRESS) (UINTN) Private->Buffer));
+
+ ASSERT (DeviceAddress == ((EFI_PHYSICAL_ADDRESS)(UINTN)Private->Buffer));
DEBUG ((DEBUG_INFO, "%a: DMA buffer base at 0x%x\n", __FUNCTION__, Private->Buffer));
//
@@ -351,7 +364,9 @@ NvmExpressPeimEntry ( DEBUG ((
DEBUG_ERROR,
"%a: Controller initialization fail for Controller %d with Status - %r.\n",
- __FUNCTION__, Controller, Status
+ __FUNCTION__,
+ Controller,
+ Status
));
NvmeFreeDmaResource (Private);
Controller++;
@@ -369,7 +384,9 @@ NvmExpressPeimEntry ( DEBUG ((
DEBUG_ERROR,
"%a: Namespaces discovery fail for Controller %d with Status - %r.\n",
- __FUNCTION__, Controller, Status
+ __FUNCTION__,
+ Controller,
+ Status
));
NvmeFreeDmaResource (Private);
Controller++;
@@ -379,35 +396,35 @@ NvmExpressPeimEntry ( //
// Nvm Express Pass Thru PPI
//
- Private->PassThruMode.Attributes = EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
- EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL |
- EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM;
- Private->PassThruMode.IoAlign = sizeof (UINTN);
- Private->PassThruMode.NvmeVersion = EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI_REVISION;
- Private->NvmePassThruPpi.Mode = &Private->PassThruMode;
- Private->NvmePassThruPpi.GetDevicePath = NvmePassThruGetDevicePath;
- Private->NvmePassThruPpi.GetNextNameSpace = NvmePassThruGetNextNameSpace;
- Private->NvmePassThruPpi.PassThru = NvmePassThru;
+ Private->PassThruMode.Attributes = EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
+ EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL |
+ EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM;
+ Private->PassThruMode.IoAlign = sizeof (UINTN);
+ Private->PassThruMode.NvmeVersion = EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI_REVISION;
+ Private->NvmePassThruPpi.Mode = &Private->PassThruMode;
+ Private->NvmePassThruPpi.GetDevicePath = NvmePassThruGetDevicePath;
+ Private->NvmePassThruPpi.GetNextNameSpace = NvmePassThruGetNextNameSpace;
+ Private->NvmePassThruPpi.PassThru = NvmePassThru;
CopyMem (
&Private->NvmePassThruPpiList,
&mNvmePassThruPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
- Private->NvmePassThruPpiList.Ppi = &Private->NvmePassThruPpi;
+ Private->NvmePassThruPpiList.Ppi = &Private->NvmePassThruPpi;
PeiServicesInstallPpi (&Private->NvmePassThruPpiList);
//
// Block Io PPI
//
- Private->BlkIoPpi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo;
- Private->BlkIoPpi.GetBlockDeviceMediaInfo = NvmeBlockIoPeimGetMediaInfo;
- Private->BlkIoPpi.ReadBlocks = NvmeBlockIoPeimReadBlocks;
+ Private->BlkIoPpi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo;
+ Private->BlkIoPpi.GetBlockDeviceMediaInfo = NvmeBlockIoPeimGetMediaInfo;
+ Private->BlkIoPpi.ReadBlocks = NvmeBlockIoPeimReadBlocks;
CopyMem (
&Private->BlkIoPpiList,
&mNvmeBlkIoPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
- Private->BlkIoPpiList.Ppi = &Private->BlkIoPpi;
+ Private->BlkIoPpiList.Ppi = &Private->BlkIoPpi;
Private->BlkIo2Ppi.Revision = EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION;
Private->BlkIo2Ppi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo2;
@@ -418,7 +435,7 @@ NvmExpressPeimEntry ( &mNvmeBlkIo2PpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
- Private->BlkIo2PpiList.Ppi = &Private->BlkIo2Ppi;
+ Private->BlkIo2PpiList.Ppi = &Private->BlkIo2Ppi;
PeiServicesInstallPpi (&Private->BlkIoPpiList);
//
@@ -428,7 +445,8 @@ NvmExpressPeimEntry ( DEBUG ((
DEBUG_INFO,
"%a: Security Security Command PPI will be produced for Controller %d.\n",
- __FUNCTION__, Controller
+ __FUNCTION__,
+ Controller
));
Private->StorageSecurityPpi.Revision = EDKII_STORAGE_SECURITY_PPI_REVISION;
Private->StorageSecurityPpi.GetNumberofDevices = NvmeStorageSecurityGetDeviceNo;
@@ -440,7 +458,7 @@ NvmExpressPeimEntry ( &mNvmeStorageSecurityPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
- Private->StorageSecurityPpiList.Ppi = &Private->StorageSecurityPpi;
+ Private->StorageSecurityPpiList.Ppi = &Private->StorageSecurityPpi;
PeiServicesInstallPpi (&Private->StorageSecurityPpiList);
}
@@ -449,11 +467,13 @@ NvmExpressPeimEntry ( &mNvmeEndOfPeiNotifyListTemplate,
sizeof (EFI_PEI_NOTIFY_DESCRIPTOR)
);
- PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
+ PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
DEBUG ((
- DEBUG_INFO, "%a: Controller %d has been successfully initialized.\n",
- __FUNCTION__, Controller
+ DEBUG_INFO,
+ "%a: Controller %d has been successfully initialized.\n",
+ __FUNCTION__,
+ Controller
));
Controller++;
}
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.h b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.h index 8cd905191b..78a6b70165 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.h @@ -44,68 +44,68 @@ typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DA //
// NVME PEI driver implementation related definitions
//
-#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
-#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
-#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
-#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
-#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
-#define NVME_PRP_SIZE (8) // Pages of PRP list
+#define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
+#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
+#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
+#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
+#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
+#define NVME_PRP_SIZE (8) // Pages of PRP list
#define NVME_MEM_MAX_PAGES \
( \
- 1 /* ASQ */ + \
- 1 /* ACQ */ + \
- 1 /* SQs */ + \
- 1 /* CQs */ + \
+ 1 /* ASQ */ + \
+ 1 /* ACQ */ + \
+ 1 /* SQs */ + \
+ 1 /* CQs */ + \
NVME_PRP_SIZE) /* PRPs */
-#define NVME_ADMIN_QUEUE 0x00
-#define NVME_IO_QUEUE 0x01
-#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
-#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
+#define NVME_ADMIN_QUEUE 0x00
+#define NVME_IO_QUEUE 0x01
+#define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
+#define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
//
// Nvme namespace data structure.
//
struct _PEI_NVME_NAMESPACE_INFO {
- UINT32 NamespaceId;
- UINT64 NamespaceUuid;
- EFI_PEI_BLOCK_IO2_MEDIA Media;
+ UINT32 NamespaceId;
+ UINT64 NamespaceUuid;
+ EFI_PEI_BLOCK_IO2_MEDIA Media;
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
};
-#define NVME_CONTROLLER_NSID 0
+#define NVME_CONTROLLER_NSID 0
//
// Unique signature for private data structure.
//
-#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
+#define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
//
// Nvme controller private data structure.
//
struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
- UINT32 Signature;
- UINTN MmioBase;
- EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
- UINTN DevicePathLength;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
-
- EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
- EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
- EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;
- EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI NvmePassThruPpi;
- EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
- EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
- EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;
- EFI_PEI_PPI_DESCRIPTOR NvmePassThruPpiList;
- EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
+ UINT32 Signature;
+ UINTN MmioBase;
+ EFI_NVM_EXPRESS_PASS_THRU_MODE PassThruMode;
+ UINTN DevicePathLength;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
+ EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
+ EDKII_PEI_STORAGE_SECURITY_CMD_PPI StorageSecurityPpi;
+ EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI NvmePassThruPpi;
+ EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
+ EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
+ EFI_PEI_PPI_DESCRIPTOR StorageSecurityPpiList;
+ EFI_PEI_PPI_DESCRIPTOR NvmePassThruPpiList;
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
//
// Pointer to identify controller data
//
- NVME_ADMIN_CONTROLLER_DATA *ControllerData;
+ NVME_ADMIN_CONTROLLER_DATA *ControllerData;
//
// (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
@@ -115,34 +115,34 @@ struct _PEI_NVME_CONTROLLER_PRIVATE_DATA { // 4th 4kB boundary is the start of I/O completion queue
// 5th 4kB boundary is the start of PRP list buffers
//
- VOID *Buffer;
- VOID *BufferMapping;
+ VOID *Buffer;
+ VOID *BufferMapping;
//
// Pointers to 4kB aligned submission & completion queues
//
- NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
- NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
+ NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
+ NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
//
// Submission and completion queue indices
//
- NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
- NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
+ NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
+ NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
- UINT8 Pt[NVME_MAX_QUEUES];
- UINT16 Cid[NVME_MAX_QUEUES];
+ UINT8 Pt[NVME_MAX_QUEUES];
+ UINT16 Cid[NVME_MAX_QUEUES];
//
// Nvme controller capabilities
//
- NVME_CAP Cap;
+ NVME_CAP Cap;
//
// Namespaces information on the controller
//
- UINT32 ActiveNamespaceNum;
- PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
+ UINT32 ActiveNamespaceNum;
+ PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
};
#define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \
@@ -156,7 +156,6 @@ struct _PEI_NVME_CONTROLLER_PRIVATE_DATA { #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \
CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
-
//
// Internal functions
//
@@ -201,9 +200,9 @@ IoMmuAllocateBuffer ( **/
EFI_STATUS
IoMmuFreeBuffer (
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
);
/**
@@ -227,11 +226,11 @@ IoMmuFreeBuffer ( **/
EFI_STATUS
IoMmuMap (
- IN EDKII_IOMMU_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ IN EDKII_IOMMU_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
);
/**
@@ -245,7 +244,7 @@ IoMmuMap ( **/
EFI_STATUS
IoMmuUnmap (
- IN VOID *Mapping
+ IN VOID *Mapping
);
/**
@@ -282,9 +281,9 @@ NvmePeimEndOfPei ( **/
EFI_STATUS
GetDevicePathInstanceSize (
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINTN *InstanceSize,
- OUT BOOLEAN *EntireDevicePathEnd
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINTN *InstanceSize,
+ OUT BOOLEAN *EntireDevicePathEnd
);
/**
@@ -300,8 +299,8 @@ GetDevicePathInstanceSize ( **/
EFI_STATUS
NvmeIsHcDevicePathValid (
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- IN UINTN DevicePathLength
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN UINTN DevicePathLength
);
/**
@@ -323,11 +322,11 @@ NvmeIsHcDevicePathValid ( **/
EFI_STATUS
NvmeBuildDevicePath (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN UINT64 NamespaceUuid,
- OUT UINTN *DevicePathLength,
- OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN UINT64 NamespaceUuid,
+ OUT UINTN *DevicePathLength,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -342,8 +341,8 @@ NvmeBuildDevicePath ( **/
BOOLEAN
NvmeS3SkipThisController (
- IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
- IN UINTN HcDevicePathLength
+ IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
+ IN UINTN HcDevicePathLength
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.c index a9bf4f8190..576481dcee 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.c @@ -24,29 +24,29 @@ **/
EFI_STATUS
ReadSectors (
- IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
- OUT UINTN Buffer,
- IN UINT64 Lba,
- IN UINT32 Blocks
+ IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
+ OUT UINTN Buffer,
+ IN UINT64 Lba,
+ IN UINT32 Blocks
)
{
- EFI_STATUS Status;
- UINT32 BlockSize;
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 Bytes;
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
-
- Private = NamespaceInfo->Controller;
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 Bytes;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
+
+ Private = NamespaceInfo->Controller;
NvmePassThru = &Private->NvmePassThruPpi;
- BlockSize = NamespaceInfo->Media.BlockSize;
- Bytes = Blocks * BlockSize;
+ BlockSize = NamespaceInfo->Media.BlockSize;
+ Bytes = Blocks * BlockSize;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -60,7 +60,7 @@ ReadSectors ( CommandPacket.QueueType = NVME_IO_QUEUE;
CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;
- CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64(Lba, 32);
+ CommandPacket.NvmeCmd->Cdw11 = (UINT32)RShiftU64 (Lba, 32);
CommandPacket.NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;
CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID | CDW12_VALID;
@@ -88,18 +88,18 @@ ReadSectors ( **/
EFI_STATUS
NvmeRead (
- IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
- OUT UINTN Buffer,
- IN UINT64 Lba,
- IN UINTN Blocks
+ IN PEI_NVME_NAMESPACE_INFO *NamespaceInfo,
+ OUT UINTN Buffer,
+ IN UINT64 Lba,
+ IN UINTN Blocks
)
{
- EFI_STATUS Status;
- UINT32 Retries;
- UINT32 BlockSize;
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 MaxTransferBlocks;
- UINTN OrginalBlocks;
+ EFI_STATUS Status;
+ UINT32 Retries;
+ UINT32 BlockSize;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 MaxTransferBlocks;
+ UINTN OrginalBlocks;
Status = EFI_SUCCESS;
Retries = 0;
@@ -120,14 +120,15 @@ NvmeRead ( Lba,
Blocks > MaxTransferBlocks ? MaxTransferBlocks : (UINT32)Blocks
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
Retries++;
MaxTransferBlocks = MaxTransferBlocks >> 1;
- if (Retries > NVME_READ_MAX_RETRY || MaxTransferBlocks < 1) {
+ if ((Retries > NVME_READ_MAX_RETRY) || (MaxTransferBlocks < 1)) {
DEBUG ((DEBUG_ERROR, "%a: ReadSectors fail, Status - %r\n", __FUNCTION__, Status));
break;
}
+
DEBUG ((
DEBUG_BLKIO,
"%a: ReadSectors fail, retry with smaller transfer block number - 0x%x\n",
@@ -142,13 +143,21 @@ NvmeRead ( Buffer += (MaxTransferBlocks * BlockSize);
Lba += MaxTransferBlocks;
} else {
- Blocks = 0;
+ Blocks = 0;
}
}
- DEBUG ((DEBUG_BLKIO, "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
- "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n", __FUNCTION__, Lba,
- (UINT64)OrginalBlocks, (UINT64)Blocks, BlockSize, Status));
+ DEBUG ((
+ DEBUG_BLKIO,
+ "%a: Lba = 0x%08Lx, Original = 0x%08Lx, "
+ "Remaining = 0x%08Lx, BlockSize = 0x%x, Status = %r\n",
+ __FUNCTION__,
+ Lba,
+ (UINT64)OrginalBlocks,
+ (UINT64)Blocks,
+ BlockSize,
+ Status
+ ));
return Status;
}
@@ -176,13 +185,13 @@ NvmeBlockIoPeimGetDeviceNo ( OUT UINTN *NumberBlockDevices
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- if (This == NULL || NumberBlockDevices == NULL) {
+ if ((This == NULL) || (NumberBlockDevices == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO (This);
+ Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO (This);
*NumberBlockDevices = Private->ActiveNamespaceNum;
return EFI_SUCCESS;
@@ -238,9 +247,9 @@ NvmeBlockIoPeimGetMediaInfo ( OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- if (This == NULL || MediaInfo == NULL) {
+ if ((This == NULL) || (MediaInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -250,7 +259,7 @@ NvmeBlockIoPeimGetMediaInfo ( return EFI_INVALID_PARAMETER;
}
- MediaInfo->DeviceType = (EFI_PEI_BLOCK_DEVICE_TYPE) EDKII_PEI_BLOCK_DEVICE_TYPE_NVME;
+ MediaInfo->DeviceType = (EFI_PEI_BLOCK_DEVICE_TYPE)EDKII_PEI_BLOCK_DEVICE_TYPE_NVME;
MediaInfo->MediaPresent = TRUE;
MediaInfo->LastBlock = (UINTN)Private->NamespaceInfo[DeviceIndex-1].Media.LastBlock;
MediaInfo->BlockSize = Private->NamespaceInfo[DeviceIndex-1].Media.BlockSize;
@@ -303,17 +312,17 @@ NvmeBlockIoPeimReadBlocks ( OUT VOID *Buffer
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
- UINT32 BlockSize;
- UINTN NumberOfBlocks;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
+ UINT32 BlockSize;
+ UINTN NumberOfBlocks;
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO (This);
//
// Check parameters
//
- if (This == NULL || Buffer == NULL) {
+ if ((This == NULL) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -329,7 +338,7 @@ NvmeBlockIoPeimReadBlocks ( // Check BufferSize and StartLBA
//
NamespaceInfo = &(Private->NamespaceInfo[DeviceIndex - 1]);
- BlockSize = NamespaceInfo->Media.BlockSize;
+ BlockSize = NamespaceInfo->Media.BlockSize;
if (BufferSize % BlockSize != 0) {
return EFI_BAD_BUFFER_SIZE;
}
@@ -337,6 +346,7 @@ NvmeBlockIoPeimReadBlocks ( if (StartLBA > NamespaceInfo->Media.LastBlock) {
return EFI_INVALID_PARAMETER;
}
+
NumberOfBlocks = BufferSize / BlockSize;
if (NumberOfBlocks - 1 > NamespaceInfo->Media.LastBlock - StartLBA) {
return EFI_INVALID_PARAMETER;
@@ -369,13 +379,13 @@ NvmeBlockIoPeimGetDeviceNo2 ( OUT UINTN *NumberBlockDevices
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- if (This == NULL || NumberBlockDevices == NULL) {
+ if ((This == NULL) || (NumberBlockDevices == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2 (This);
+ Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2 (This);
*NumberBlockDevices = Private->ActiveNamespaceNum;
return EFI_SUCCESS;
@@ -431,22 +441,22 @@ NvmeBlockIoPeimGetMediaInfo2 ( OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
)
{
- EFI_STATUS Status;
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_PEI_BLOCK_IO_MEDIA Media;
+ EFI_STATUS Status;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_PEI_BLOCK_IO_MEDIA Media;
- if (This == NULL || MediaInfo == NULL) {
+ if ((This == NULL) || (MediaInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2 (This);
- Status = NvmeBlockIoPeimGetMediaInfo (
- PeiServices,
- &Private->BlkIoPpi,
- DeviceIndex,
- &Media
- );
+ Status = NvmeBlockIoPeimGetMediaInfo (
+ PeiServices,
+ &Private->BlkIoPpi,
+ DeviceIndex,
+ &Media
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -505,7 +515,7 @@ NvmeBlockIoPeimReadBlocks2 ( OUT VOID *Buffer
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
if (This == NULL) {
return EFI_INVALID_PARAMETER;
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.h b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.h index 2c7065cb79..9c0a1eadf8 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiBlockIo.h @@ -14,9 +14,9 @@ //
// Nvme device for EFI_PEI_BLOCK_DEVICE_TYPE
//
-#define EDKII_PEI_BLOCK_DEVICE_TYPE_NVME 7
+#define EDKII_PEI_BLOCK_DEVICE_TYPE_NVME 7
-#define NVME_READ_MAX_RETRY 3
+#define NVME_READ_MAX_RETRY 3
/**
Gets the count of block I/O devices that one specific block driver detects.
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c index 1d7e3d26e0..ac956bdce4 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c @@ -22,14 +22,14 @@ **/
EFI_STATUS
NvmeMmioRead (
- IN OUT VOID *MemBuffer,
- IN UINTN MmioAddr,
- IN UINTN Size
+ IN OUT VOID *MemBuffer,
+ IN UINTN MmioAddr,
+ IN UINTN Size
)
{
- UINTN Offset;
- UINT8 Data;
- UINT8 *Ptr;
+ UINTN Offset;
+ UINT8 Data;
+ UINT8 *Ptr;
// priority has adjusted
switch (Size) {
@@ -52,9 +52,10 @@ NvmeMmioRead ( default:
Ptr = (UINT8 *)MemBuffer;
for (Offset = 0; Offset < Size; Offset += 1) {
- Data = MmioRead8 (MmioAddr + Offset);
+ Data = MmioRead8 (MmioAddr + Offset);
Ptr[Offset] = Data;
}
+
break;
}
@@ -73,14 +74,14 @@ NvmeMmioRead ( **/
EFI_STATUS
NvmeMmioWrite (
- IN OUT UINTN MmioAddr,
- IN VOID *MemBuffer,
- IN UINTN Size
+ IN OUT UINTN MmioAddr,
+ IN VOID *MemBuffer,
+ IN UINTN Size
)
{
- UINTN Offset;
- UINT8 Data;
- UINT8 *Ptr;
+ UINTN Offset;
+ UINT8 Data;
+ UINT8 *Ptr;
// priority has adjusted
switch (Size) {
@@ -106,6 +107,7 @@ NvmeMmioWrite ( Data = Ptr[Offset];
MmioWrite8 (MmioAddr + Offset, Data);
}
+
break;
}
@@ -122,18 +124,18 @@ NvmeMmioWrite ( **/
UINT32
NvmeBaseMemPageOffset (
- IN UINTN BaseMemIndex
+ IN UINTN BaseMemIndex
)
{
- UINT32 Pages;
- UINTN Index;
- UINT32 PageSizeList[5];
+ UINT32 Pages;
+ UINTN Index;
+ UINT32 PageSizeList[5];
- PageSizeList[0] = 1; /* ASQ */
- PageSizeList[1] = 1; /* ACQ */
- PageSizeList[2] = 1; /* SQs */
- PageSizeList[3] = 1; /* CQs */
- PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */
+ PageSizeList[0] = 1; /* ASQ */
+ PageSizeList[1] = 1; /* ACQ */
+ PageSizeList[2] = 1; /* SQs */
+ PageSizeList[3] = 1; /* CQs */
+ PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */
if (BaseMemIndex > MAX_BASEMEM_COUNT) {
DEBUG ((DEBUG_ERROR, "%a: The input BaseMem index is invalid.\n", __FUNCTION__));
@@ -161,14 +163,14 @@ NvmeBaseMemPageOffset ( **/
EFI_STATUS
NvmeWaitController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN BOOLEAN WaitReady
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN BOOLEAN WaitReady
)
{
- NVME_CSTS Csts;
- EFI_STATUS Status;
- UINT32 Index;
- UINT8 Timeout;
+ NVME_CSTS Csts;
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINT8 Timeout;
//
// Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after
@@ -181,19 +183,19 @@ NvmeWaitController ( }
Status = EFI_SUCCESS;
- for(Index = (Timeout * 500); Index != 0; --Index) {
+ for (Index = (Timeout * 500); Index != 0; --Index) {
MicroSecondDelay (1000);
//
// Check if the controller is initialized
//
Status = NVME_GET_CSTS (Private, &Csts);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: NVME_GET_CSTS fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
- if ((BOOLEAN) Csts.Rdy == WaitReady) {
+ if ((BOOLEAN)Csts.Rdy == WaitReady) {
break;
}
}
@@ -216,12 +218,12 @@ NvmeWaitController ( **/
EFI_STATUS
NvmeDisableController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- NVME_CC Cc;
- NVME_CSTS Csts;
- EFI_STATUS Status;
+ NVME_CC Cc;
+ NVME_CSTS Csts;
+ EFI_STATUS Status;
Status = NVME_GET_CSTS (Private, &Csts);
@@ -271,11 +273,11 @@ ErrorExit: **/
EFI_STATUS
NvmeEnableController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- NVME_CC Cc;
- EFI_STATUS Status;
+ NVME_CC Cc;
+ EFI_STATUS Status;
//
// Enable the controller
@@ -316,25 +318,25 @@ ErrorExit: **/
EFI_STATUS
NvmeIdentifyController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN VOID *Buffer
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN VOID *Buffer
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
//
// According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
// For the Identify command, the Namespace Identifier is only used for the Namespace Data structure.
//
- Command.Nsid = 0;
+ Command.Nsid = 0;
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -369,19 +371,19 @@ NvmeIdentifyController ( **/
EFI_STATUS
NvmeIdentifyNamespace (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN VOID *Buffer
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN VOID *Buffer
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
Command.Nsid = NamespaceId;
@@ -414,11 +416,11 @@ NvmeIdentifyNamespace ( **/
VOID
NvmeDumpControllerData (
- IN NVME_ADMIN_CONTROLLER_DATA *ControllerData
+ IN NVME_ADMIN_CONTROLLER_DATA *ControllerData
)
{
- UINT8 Sn[21];
- UINT8 Mn[41];
+ UINT8 Sn[21];
+ UINT8 Mn[41];
CopyMem (Sn, ControllerData->Sn, sizeof (ControllerData->Sn));
Sn[20] = 0;
@@ -428,11 +430,11 @@ NvmeDumpControllerData ( DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", ControllerData->Vid));
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", ControllerData->Ssvid));
- DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
- DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
- DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64*)ControllerData->Fr)));
+ DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
+ DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
+ DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64 *)ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", ControllerData->Rab));
- DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)ControllerData->Ieee_oui));
+ DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32 *)ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", ControllerData->Aerl));
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", ControllerData->Sqes));
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", ControllerData->Cqes));
@@ -451,24 +453,24 @@ NvmeDumpControllerData ( **/
EFI_STATUS
NvmeCreateIoCompletionQueue (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- NVME_ADMIN_CRIOCQ CrIoCq;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ NVME_ADMIN_CRIOCQ CrIoCq;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
- ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
CommandPacket.TransferBuffer = Private->CqBuffer[NVME_IO_QUEUE];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -499,24 +501,24 @@ NvmeCreateIoCompletionQueue ( **/
EFI_STATUS
NvmeCreateIoSubmissionQueue (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- NVME_ADMIN_CRIOSQ CrIoSq;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ NVME_ADMIN_CRIOSQ CrIoSq;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
- ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
CommandPacket.TransferBuffer = Private->SqBuffer[NVME_IO_QUEUE];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -549,15 +551,15 @@ NvmeCreateIoSubmissionQueue ( **/
EFI_STATUS
NvmeControllerInit (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_STATUS Status;
- UINTN Index;
- NVME_AQA Aqa;
- NVME_ASQ Asq;
- NVME_ACQ Acq;
- NVME_VER Ver;
+ EFI_STATUS Status;
+ UINTN Index;
+ NVME_AQA Aqa;
+ NVME_ASQ Asq;
+ NVME_ACQ Acq;
+ NVME_VER Ver;
//
// Dump the NVME controller implementation version
@@ -589,6 +591,7 @@ NvmeControllerInit ( ZeroMem ((VOID *)(UINTN)(&Private->SqTdbl[Index]), sizeof (NVME_SQTDBL));
ZeroMem ((VOID *)(UINTN)(&Private->CqHdbl[Index]), sizeof (NVME_CQHDBL));
}
+
ZeroMem (Private->Buffer, EFI_PAGE_SIZE * NVME_MEM_MAX_PAGES);
//
@@ -657,11 +660,13 @@ NvmeControllerInit ( return EFI_OUT_OF_RESOURCES;
}
}
+
Status = NvmeIdentifyController (Private, Private->ControllerData);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: NvmeIdentifyController fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
+
NvmeDumpControllerData (Private->ControllerData);
//
@@ -684,6 +689,7 @@ NvmeControllerInit ( DEBUG ((DEBUG_ERROR, "%a: Create IO completion queue fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
+
Status = NvmeCreateIoSubmissionQueue (Private);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Create IO submission queue fail, Status - %r\n", __FUNCTION__, Status));
@@ -700,17 +706,17 @@ NvmeControllerInit ( **/
VOID
NvmeFreeDmaResource (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
ASSERT (Private != NULL);
if (Private->BufferMapping != NULL) {
IoMmuFreeBuffer (
- NVME_MEM_MAX_PAGES,
- Private->Buffer,
- Private->BufferMapping
- );
+ NVME_MEM_MAX_PAGES,
+ Private->Buffer,
+ Private->BufferMapping
+ );
}
return;
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h index 89fee735fe..a6bec510f0 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h @@ -43,14 +43,13 @@ enum { //
// All of base memories are 4K(0x1000) alignment
//
-#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
-#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
-#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-
+#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
+#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
+#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
/**
Transfer MMIO Data to memory.
@@ -64,9 +63,9 @@ enum { **/
EFI_STATUS
NvmeMmioRead (
- IN OUT VOID *MemBuffer,
- IN UINTN MmioAddr,
- IN UINTN Size
+ IN OUT VOID *MemBuffer,
+ IN UINTN MmioAddr,
+ IN UINTN Size
);
/**
@@ -81,9 +80,9 @@ NvmeMmioRead ( **/
EFI_STATUS
NvmeMmioWrite (
- IN OUT UINTN MmioAddr,
- IN VOID *MemBuffer,
- IN UINTN Size
+ IN OUT UINTN MmioAddr,
+ IN VOID *MemBuffer,
+ IN UINTN Size
);
/**
@@ -96,7 +95,7 @@ NvmeMmioWrite ( **/
UINT32
NvmeBaseMemPageOffset (
- IN UINTN BaseMemIndex
+ IN UINTN BaseMemIndex
);
/**
@@ -110,7 +109,7 @@ NvmeBaseMemPageOffset ( **/
EFI_STATUS
NvmeControllerInit (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
);
/**
@@ -126,9 +125,9 @@ NvmeControllerInit ( **/
EFI_STATUS
NvmeIdentifyNamespace (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN VOID *Buffer
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN VOID *Buffer
);
/**
@@ -139,7 +138,7 @@ NvmeIdentifyNamespace ( **/
VOID
NvmeFreeDmaResource (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.c index 370a54e5a2..dc280ec4e3 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.c @@ -22,22 +22,22 @@ **/
UINT64
NvmeCreatePrpList (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
- IN UINTN Pages
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
+ IN UINTN Pages
)
{
- UINTN PrpEntryNo;
- UINTN PrpListNo;
- UINT64 PrpListBase;
- VOID *PrpListHost;
- UINTN PrpListIndex;
- UINTN PrpEntryIndex;
- UINT64 Remainder;
- EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
- UINTN Bytes;
- UINT8 *PrpEntry;
- EFI_PHYSICAL_ADDRESS NewPhyAddr;
+ UINTN PrpEntryNo;
+ UINTN PrpListNo;
+ UINT64 PrpListBase;
+ VOID *PrpListHost;
+ UINTN PrpListIndex;
+ UINTN PrpEntryIndex;
+ UINT64 Remainder;
+ EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
+ UINTN Bytes;
+ UINT8 *PrpEntry;
+ EFI_PHYSICAL_ADDRESS NewPhyAddr;
//
// The number of Prp Entry in a memory page.
@@ -47,7 +47,7 @@ NvmeCreatePrpList ( //
// Calculate total PrpList number.
//
- PrpListNo = (UINTN) DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);
+ PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);
if (Remainder != 0) {
PrpListNo += 1;
}
@@ -62,9 +62,10 @@ NvmeCreatePrpList ( ));
return 0;
}
- PrpListHost = (VOID *)(UINTN) NVME_PRP_BASE (Private);
- Bytes = EFI_PAGES_TO_SIZE (PrpListNo);
+ PrpListHost = (VOID *)(UINTN)NVME_PRP_BASE (Private);
+
+ Bytes = EFI_PAGES_TO_SIZE (PrpListNo);
PrpListPhyAddr = (UINT64)(UINTN)(PrpListHost);
//
@@ -75,19 +76,19 @@ NvmeCreatePrpList ( PrpListBase = (UINTN)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
- PrpEntry = (UINT8 *)(UINTN) (PrpListBase + PrpEntryIndex * sizeof(UINT64));
+ PrpEntry = (UINT8 *)(UINTN)(PrpListBase + PrpEntryIndex * sizeof (UINT64));
if (PrpEntryIndex != PrpEntryNo - 1) {
//
// Fill all PRP entries except of last one.
//
- CopyMem (PrpEntry, (VOID *)(UINTN) (&PhysicalAddr), sizeof (UINT64));
+ CopyMem (PrpEntry, (VOID *)(UINTN)(&PhysicalAddr), sizeof (UINT64));
PhysicalAddr += EFI_PAGE_SIZE;
} else {
//
// Fill last PRP entries with next PRP List pointer.
//
NewPhyAddr = (PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE);
- CopyMem (PrpEntry, (VOID *)(UINTN) (&NewPhyAddr), sizeof (UINT64));
+ CopyMem (PrpEntry, (VOID *)(UINTN)(&NewPhyAddr), sizeof (UINT64));
}
}
}
@@ -97,8 +98,8 @@ NvmeCreatePrpList ( //
PrpListBase = (UINTN)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
for (PrpEntryIndex = 0; PrpEntryIndex < ((Remainder != 0) ? Remainder : PrpEntryNo); ++PrpEntryIndex) {
- PrpEntry = (UINT8 *)(UINTN) (PrpListBase + PrpEntryIndex * sizeof(UINT64));
- CopyMem (PrpEntry, (VOID *)(UINTN) (&PhysicalAddr), sizeof (UINT64));
+ PrpEntry = (UINT8 *)(UINTN)(PrpListBase + PrpEntryIndex * sizeof (UINT64));
+ CopyMem (PrpEntry, (VOID *)(UINTN)(&PhysicalAddr), sizeof (UINT64));
PhysicalAddr += EFI_PAGE_SIZE;
}
@@ -114,10 +115,10 @@ NvmeCreatePrpList ( **/
EFI_STATUS
NvmeCheckCqStatus (
- IN NVME_CQ *Cq
+ IN NVME_CQ *Cq
)
{
- if (Cq->Sct == 0x0 && Cq->Sc == 0x0) {
+ if ((Cq->Sct == 0x0) && (Cq->Sc == 0x0)) {
return EFI_SUCCESS;
}
@@ -202,6 +203,7 @@ NvmeCheckCqStatus ( DEBUG ((DEBUG_INFO, "Reservation Conflict\n"));
break;
}
+
break;
case 0x1:
@@ -264,6 +266,7 @@ NvmeCheckCqStatus ( DEBUG ((DEBUG_INFO, "Attempted Write to Read Only Range\n"));
break;
}
+
break;
case 0x2:
@@ -290,6 +293,7 @@ NvmeCheckCqStatus ( DEBUG ((DEBUG_INFO, "Access Denied\n"));
break;
}
+
break;
default:
@@ -333,26 +337,26 @@ NvmeCheckCqStatus ( **/
EFI_STATUS
NvmePassThruExecute (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
)
{
- EFI_STATUS Status;
- NVME_SQ *Sq;
- NVME_CQ *Cq;
- UINT8 QueueId;
- UINTN SqSize;
- UINTN CqSize;
- EDKII_IOMMU_OPERATION MapOp;
- UINTN MapLength;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *MapData;
- VOID *MapMeta;
- UINT32 Bytes;
- UINT32 Offset;
- UINT32 Data32;
- UINT64 Timer;
+ EFI_STATUS Status;
+ NVME_SQ *Sq;
+ NVME_CQ *Cq;
+ UINT8 QueueId;
+ UINTN SqSize;
+ UINTN CqSize;
+ EDKII_IOMMU_OPERATION MapOp;
+ UINTN MapLength;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *MapData;
+ VOID *MapMeta;
+ UINT32 Bytes;
+ UINT32 Offset;
+ UINT32 Data32;
+ UINT64 Timer;
//
// Check the data fields in Packet parameter
@@ -378,7 +382,7 @@ NvmePassThruExecute ( return EFI_INVALID_PARAMETER;
}
- if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
+ if ((Packet->QueueType != NVME_ADMIN_QUEUE) && (Packet->QueueType != NVME_IO_QUEUE)) {
DEBUG ((
DEBUG_ERROR,
"%a, Invalid parameter: QueueId(%lx)\n",
@@ -413,7 +417,7 @@ NvmePassThruExecute ( ZeroMem (Sq, sizeof (NVME_SQ));
Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;
Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;
- Sq->Cid = Private->Cid[QueueId]++;;
+ Sq->Cid = Private->Cid[QueueId]++;
Sq->Nsid = Packet->NvmeCmd->Nsid;
//
@@ -436,7 +440,8 @@ NvmePassThruExecute ( //
if ((Sq->Opc & (BIT0 | BIT1)) != 0) {
if (((Packet->TransferLength != 0) && (Packet->TransferBuffer == NULL)) ||
- ((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL))) {
+ ((Packet->TransferLength == 0) && (Packet->TransferBuffer != NULL)))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -445,9 +450,11 @@ NvmePassThruExecute ( // allocated internally by the driver.
//
if ((Packet->QueueType == NVME_ADMIN_QUEUE) &&
- ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD))) {
+ ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))
+ {
if ((Packet->TransferBuffer != Private->SqBuffer[NVME_IO_QUEUE]) &&
- (Packet->TransferBuffer != Private->CqBuffer[NVME_IO_QUEUE])) {
+ (Packet->TransferBuffer != Private->CqBuffer[NVME_IO_QUEUE]))
+ {
DEBUG ((
DEBUG_ERROR,
"%a: Does not support external IO queues creation request.\n",
@@ -464,13 +471,13 @@ NvmePassThruExecute ( if ((Packet->TransferLength != 0) && (Packet->TransferBuffer != NULL)) {
MapLength = Packet->TransferLength;
- Status = IoMmuMap (
- MapOp,
- Packet->TransferBuffer,
- &MapLength,
- &PhyAddr,
- &MapData
- );
+ Status = IoMmuMap (
+ MapOp,
+ Packet->TransferBuffer,
+ &MapLength,
+ &PhyAddr,
+ &MapData
+ );
if (EFI_ERROR (Status) || (MapLength != Packet->TransferLength)) {
Status = EFI_OUT_OF_RESOURCES;
DEBUG ((DEBUG_ERROR, "%a: Fail to map data buffer.\n", __FUNCTION__));
@@ -480,20 +487,21 @@ NvmePassThruExecute ( Sq->Prp[0] = PhyAddr;
}
- if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
+ if ((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
MapLength = Packet->MetadataLength;
- Status = IoMmuMap (
- MapOp,
- Packet->MetadataBuffer,
- &MapLength,
- &PhyAddr,
- &MapMeta
- );
+ Status = IoMmuMap (
+ MapOp,
+ Packet->MetadataBuffer,
+ &MapLength,
+ &PhyAddr,
+ &MapMeta
+ );
if (EFI_ERROR (Status) || (MapLength != Packet->MetadataLength)) {
Status = EFI_OUT_OF_RESOURCES;
DEBUG ((DEBUG_ERROR, "%a: Fail to map meta data buffer.\n", __FUNCTION__));
goto Exit;
}
+
Sq->Mptr = PhyAddr;
}
}
@@ -510,18 +518,17 @@ NvmePassThruExecute ( //
// Create PrpList for remaining Data Buffer.
//
- PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
+ PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
Sq->Prp[1] = NvmeCreatePrpList (
Private,
PhyAddr,
- EFI_SIZE_TO_PAGES(Offset + Bytes) - 1
+ EFI_SIZE_TO_PAGES (Offset + Bytes) - 1
);
if (Sq->Prp[1] == 0) {
Status = EFI_OUT_OF_RESOURCES;
DEBUG ((DEBUG_ERROR, "%a: Create PRP list fail, Status - %r\n", __FUNCTION__, Status));
goto Exit;
}
-
} else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
}
@@ -529,18 +536,23 @@ NvmePassThruExecute ( if (Packet->NvmeCmd->Flags & CDW10_VALID) {
Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
}
+
if (Packet->NvmeCmd->Flags & CDW11_VALID) {
Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
}
+
if (Packet->NvmeCmd->Flags & CDW12_VALID) {
Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
}
+
if (Packet->NvmeCmd->Flags & CDW13_VALID) {
Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
}
+
if (Packet->NvmeCmd->Flags & CDW14_VALID) {
Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
}
+
if (Packet->NvmeCmd->Flags & CDW15_VALID) {
Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
}
@@ -552,6 +564,7 @@ NvmePassThruExecute ( if (Private->SqTdbl[QueueId].Sqt == SqSize) {
Private->SqTdbl[QueueId].Sqt = 0;
}
+
Data32 = ReadUnaligned32 ((UINT32 *)&Private->SqTdbl[QueueId]);
Status = NVME_SET_SQTDBL (Private, QueueId, &Data32);
if (EFI_ERROR (Status)) {
@@ -588,6 +601,7 @@ NvmePassThruExecute ( //
Status = EFI_TIMEOUT;
}
+
goto Exit;
}
@@ -597,7 +611,7 @@ NvmePassThruExecute ( Private->CqHdbl[QueueId].Cqh++;
if (Private->CqHdbl[QueueId].Cqh == CqSize) {
Private->CqHdbl[QueueId].Cqh = 0;
- Private->Pt[QueueId] ^= 1;
+ Private->Pt[QueueId] ^= 1;
}
//
@@ -643,14 +657,14 @@ Exit: EFI_STATUS
EFIAPI
NvmePassThruGetDevicePath (
- IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
- OUT UINTN *DevicePathLength,
- OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
+ OUT UINTN *DevicePathLength,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- if (This == NULL || DevicePathLength == NULL || DevicePath == NULL) {
+ if ((This == NULL) || (DevicePathLength == NULL) || (DevicePath == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -705,15 +719,15 @@ NvmePassThruGetDevicePath ( EFI_STATUS
EFIAPI
NvmePassThruGetNextNameSpace (
- IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
- IN OUT UINT32 *NamespaceId
+ IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
+ IN OUT UINT32 *NamespaceId
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- UINT32 DeviceIndex;
- EFI_STATUS Status;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ UINT32 DeviceIndex;
+ EFI_STATUS Status;
- if (This == NULL || NamespaceId == NULL) {
+ if ((This == NULL) || (NamespaceId == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -736,7 +750,7 @@ NvmePassThruGetNextNameSpace ( // Start with the first namespace ID
//
*NamespaceId = Private->NamespaceInfo[0].NamespaceId;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
} else {
if (*NamespaceId > Private->ControllerData->Nn) {
return EFI_INVALID_PARAMETER;
@@ -750,15 +764,15 @@ NvmePassThruGetNextNameSpace ( if (*NamespaceId == Private->NamespaceInfo[DeviceIndex].NamespaceId) {
if ((DeviceIndex + 1) < Private->ActiveNamespaceNum) {
*NamespaceId = Private->NamespaceInfo[DeviceIndex + 1].NamespaceId;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
}
+
break;
}
}
}
return Status;
-
}
/**
@@ -795,15 +809,15 @@ NvmePassThruGetNextNameSpace ( EFI_STATUS
EFIAPI
NvmePassThru (
- IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
- IN UINT32 NamespaceId,
- IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
+ IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_STATUS Status;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
- if (This == NULL || Packet == NULL) {
+ if ((This == NULL) || (Packet == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -812,7 +826,8 @@ NvmePassThru ( // Check NamespaceId is valid or not.
//
if ((NamespaceId > Private->ControllerData->Nn) &&
- (NamespaceId != (UINT32) -1)) {
+ (NamespaceId != (UINT32)-1))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -823,6 +838,4 @@ NvmePassThru ( );
return Status;
-
}
-
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.h b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.h index 00e8f0abda..080e785126 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiPassThru.h @@ -11,8 +11,6 @@ #ifndef _NVM_EXPRESS_PEI_PASSTHRU_H_
#define _NVM_EXPRESS_PEI_PASSTHRU_H_
-
-
/**
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function only
supports blocking execution of the command.
@@ -46,9 +44,9 @@ **/
EFI_STATUS
NvmePassThruExecute (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
);
/**
@@ -71,9 +69,9 @@ NvmePassThruExecute ( EFI_STATUS
EFIAPI
NvmePassThruGetDevicePath (
- IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
- OUT UINTN *DevicePathLength,
- OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
+ OUT UINTN *DevicePathLength,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -115,8 +113,8 @@ NvmePassThruGetDevicePath ( EFI_STATUS
EFIAPI
NvmePassThruGetNextNameSpace (
- IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
- IN OUT UINT32 *NamespaceId
+ IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
+ IN OUT UINT32 *NamespaceId
);
/**
@@ -153,9 +151,9 @@ NvmePassThruGetNextNameSpace ( EFI_STATUS
EFIAPI
NvmePassThru (
- IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
- IN UINT32 NamespaceId,
- IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
+ IN EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *This,
+ IN UINT32 NamespaceId,
+ IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiS3.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiS3.c index f409285d54..d704c62eaa 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiS3.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiS3.c @@ -26,18 +26,18 @@ **/
BOOLEAN
NvmeS3SkipThisController (
- IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
- IN UINTN HcDevicePathLength
+ IN EFI_DEVICE_PATH_PROTOCOL *HcDevicePath,
+ IN UINTN HcDevicePathLength
)
{
- EFI_STATUS Status;
- UINT8 DummyData;
- UINTN S3InitDevicesLength;
- EFI_DEVICE_PATH_PROTOCOL *S3InitDevices;
- EFI_DEVICE_PATH_PROTOCOL *DevicePathInst;
- UINTN DevicePathInstLength;
- BOOLEAN EntireEnd;
- BOOLEAN Skip;
+ EFI_STATUS Status;
+ UINT8 DummyData;
+ UINTN S3InitDevicesLength;
+ EFI_DEVICE_PATH_PROTOCOL *S3InitDevices;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathInst;
+ UINTN DevicePathInstLength;
+ BOOLEAN EntireEnd;
+ BOOLEAN Skip;
//
// From the LockBox, get the list of device paths for devices need to be
@@ -47,7 +47,7 @@ NvmeS3SkipThisController ( S3InitDevicesLength = sizeof (DummyData);
EntireEnd = FALSE;
Skip = TRUE;
- Status = RestoreLockBox (&gS3StorageDeviceInitListGuid, &DummyData, &S3InitDevicesLength);
+ Status = RestoreLockBox (&gS3StorageDeviceInitListGuid, &DummyData, &S3InitDevicesLength);
if (Status != EFI_BUFFER_TOO_SMALL) {
return Skip;
} else {
@@ -83,7 +83,7 @@ NvmeS3SkipThisController ( }
DevicePathInst = S3InitDevices;
- S3InitDevices = (EFI_DEVICE_PATH_PROTOCOL *)((UINTN) S3InitDevices + DevicePathInstLength);
+ S3InitDevices = (EFI_DEVICE_PATH_PROTOCOL *)((UINTN)S3InitDevices + DevicePathInstLength);
if (HcDevicePathLength >= DevicePathInstLength) {
continue;
@@ -97,7 +97,8 @@ NvmeS3SkipThisController ( DevicePathInst,
HcDevicePath,
HcDevicePathLength - sizeof (EFI_DEVICE_PATH_PROTOCOL)
- ) == 0) {
+ ) == 0)
+ {
Skip = FALSE;
break;
}
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.c index 094d61bb8a..d45487efed 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.c @@ -47,27 +47,27 @@ **/
EFI_STATUS
TrustTransferNvmeDevice (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN OUT VOID *Buffer,
- IN UINT8 SecurityProtocolId,
- IN UINT16 SecurityProtocolSpecificData,
- IN UINTN TransferLength,
- IN BOOLEAN IsTrustSend,
- IN UINT64 Timeout,
- OUT UINTN *TransferLengthOut
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN OUT VOID *Buffer,
+ IN UINT8 SecurityProtocolId,
+ IN UINT16 SecurityProtocolSpecificData,
+ IN UINTN TransferLength,
+ IN BOOLEAN IsTrustSend,
+ IN UINT64 Timeout,
+ OUT UINTN *TransferLengthOut
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- UINT16 SpecificData;
- EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ UINT16 SpecificData;
+ EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI *NvmePassThru;
NvmePassThru = &Private->NvmePassThruPpi;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -103,10 +103,10 @@ TrustTransferNvmeDevice ( );
if (!IsTrustSend) {
- if (EFI_ERROR (Status)) {
+ if (EFI_ERROR (Status)) {
*TransferLengthOut = 0;
} else {
- *TransferLengthOut = (UINTN) TransferLength;
+ *TransferLengthOut = (UINTN)TransferLength;
}
}
@@ -126,17 +126,17 @@ TrustTransferNvmeDevice ( EFI_STATUS
EFIAPI
NvmeStorageSecurityGetDeviceNo (
- IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
- OUT UINTN *NumberofDevices
+ IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
+ OUT UINTN *NumberofDevices
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- if (This == NULL || NumberofDevices == NULL) {
+ if ((This == NULL) || (NumberofDevices == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY (This);
+ Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY (This);
*NumberofDevices = Private->ActiveNamespaceNum;
return EFI_SUCCESS;
@@ -176,9 +176,9 @@ NvmeStorageSecurityGetDevicePath ( OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- if (This == NULL || DevicePathLength == NULL || DevicePath == NULL) {
+ if ((This == NULL) || (DevicePathLength == NULL) || (DevicePath == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -295,8 +295,8 @@ NvmeStorageSecurityReceiveData ( OUT UINTN *PayloadTransferSize
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_STATUS Status;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
if ((PayloadBuffer == NULL) || (PayloadTransferSize == NULL) || (PayloadBufferSize == 0)) {
return EFI_INVALID_PARAMETER;
@@ -394,8 +394,8 @@ NvmeStorageSecuritySendData ( IN VOID *PayloadBuffer
)
{
- PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
- EFI_STATUS Status;
+ PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
if ((PayloadBuffer == NULL) && (PayloadBufferSize != 0)) {
return EFI_INVALID_PARAMETER;
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.h b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.h index 18f3e1ce26..16351882ef 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiStorageSecurity.h @@ -24,8 +24,8 @@ EFI_STATUS
EFIAPI
NvmeStorageSecurityGetDeviceNo (
- IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
- OUT UINTN *NumberofDevices
+ IN EDKII_PEI_STORAGE_SECURITY_CMD_PPI *This,
+ OUT UINTN *NumberofDevices
);
/**
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c index ff2a2314fa..a7118cc16c 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c @@ -20,16 +20,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) PciBusComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) PciBusComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)PciBusComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)PciBusComponentNameGetControllerName,
"en"
};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mPciBusDriverNameTable[] = {
- { "eng;en", (CHAR16 *) L"PCI Bus Driver" },
- { NULL , NULL }
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mPciBusDriverNameTable[] = {
+ { "eng;en", (CHAR16 *)L"PCI Bus Driver" },
+ { NULL, NULL }
};
/**
@@ -159,11 +158,11 @@ PciBusComponentNameGetDriverName ( EFI_STATUS
EFIAPI
PciBusComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
return EFI_UNSUPPORTED;
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h b/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h index b211391b35..0e46a13b42 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h @@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#ifndef _EFI_PCI_BUS_COMPONENT_NAME_H_
#define _EFI_PCI_BUS_COMPONENT_NAME_H_
@@ -16,6 +15,7 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2; //
// EFI Component Name Functions
//
+
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -63,7 +63,6 @@ PciBusComponentNameGetDriverName ( OUT CHAR16 **DriverName
);
-
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -135,12 +134,11 @@ PciBusComponentNameGetDriverName ( EFI_STATUS
EFIAPI
PciBusComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
-
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c index 64284ac825..337b2090d9 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c @@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// PCI Bus Driver Global Variables
//
-EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
+EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = {
PciBusDriverBindingSupported,
PciBusDriverBindingStart,
PciBusDriverBindingStop,
@@ -29,17 +29,17 @@ EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding = { EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport = NULL;
-UINTN gPciHostBridgeNumber = 0;
-BOOLEAN gFullEnumeration = TRUE;
-UINT64 gAllOne = 0xFFFFFFFFFFFFFFFFULL;
-UINT64 gAllZero = 0;
+UINTN gPciHostBridgeNumber = 0;
+BOOLEAN gFullEnumeration = TRUE;
+UINT64 gAllOne = 0xFFFFFFFFFFFFFFFFULL;
+UINT64 gAllZero = 0;
-EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
-EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
-EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
-EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
+EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
+EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
+EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
+EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugRequest = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugRequest = {
PciHotPlugRequestNotify
};
@@ -61,8 +61,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugReques EFI_STATUS
EFIAPI
PciBusEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
@@ -119,15 +119,15 @@ PciBusEntryPoint ( EFI_STATUS
EFIAPI
PciBusDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- EFI_DEV_PATH_PTR Node;
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_DEV_PATH_PTR Node;
//
// Check RemainingDevicePath validation
@@ -143,9 +143,10 @@ PciBusDriverBindingSupported ( // check its validation
//
Node.DevPath = RemainingDevicePath;
- if (Node.DevPath->Type != HARDWARE_DEVICE_PATH ||
- Node.DevPath->SubType != HW_PCI_DP ||
- DevicePathNodeLength(Node.DevPath) != sizeof(PCI_DEVICE_PATH)) {
+ if ((Node.DevPath->Type != HARDWARE_DEVICE_PATH) ||
+ (Node.DevPath->SubType != HW_PCI_DP) ||
+ (DevicePathNodeLength (Node.DevPath) != sizeof (PCI_DEVICE_PATH)))
+ {
return EFI_UNSUPPORTED;
}
}
@@ -157,7 +158,7 @@ PciBusDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -174,11 +175,11 @@ PciBusDriverBindingSupported ( // Close the I/O Abstraction(s) used to perform the supported test
//
gBS->CloseProtocol (
- Controller,
- &gEfiPciRootBridgeIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
//
// Open the EFI Device Path protocol needed to perform the supported test
@@ -186,7 +187,7 @@ PciBusDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID **) &ParentDevicePath,
+ (VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -203,11 +204,11 @@ PciBusDriverBindingSupported ( // Close protocol, don't use device path protocol in the Support() function
//
gBS->CloseProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
return EFI_SUCCESS;
}
@@ -234,9 +235,9 @@ PciBusDriverBindingStart ( IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
//
// Initialize PciRootBridgeIo to suppress incorrect compiler warning.
@@ -259,7 +260,7 @@ PciBusDriverBindingStart ( gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
- (VOID **) &gIncompatiblePciDeviceSupport
+ (VOID **)&gIncompatiblePciDeviceSupport
);
//
@@ -268,10 +269,10 @@ PciBusDriverBindingStart ( //
gPciPlatformProtocol = NULL;
gBS->LocateProtocol (
- &gEfiPciPlatformProtocolGuid,
- NULL,
- (VOID **) &gPciPlatformProtocol
- );
+ &gEfiPciPlatformProtocolGuid,
+ NULL,
+ (VOID **)&gPciPlatformProtocol
+ );
//
// If PCI Platform protocol doesn't exist, try to Pci Override Protocol.
@@ -279,32 +280,32 @@ PciBusDriverBindingStart ( if (gPciPlatformProtocol == NULL) {
gPciOverrideProtocol = NULL;
gBS->LocateProtocol (
- &gEfiPciOverrideProtocolGuid,
- NULL,
- (VOID **) &gPciOverrideProtocol
- );
+ &gEfiPciOverrideProtocolGuid,
+ NULL,
+ (VOID **)&gPciOverrideProtocol
+ );
}
if (mIoMmuProtocol == NULL) {
gBS->LocateProtocol (
- &gEdkiiIoMmuProtocolGuid,
- NULL,
- (VOID **) &mIoMmuProtocol
- );
+ &gEdkiiIoMmuProtocolGuid,
+ NULL,
+ (VOID **)&mIoMmuProtocol
+ );
}
if (mDeviceSecurityProtocol == NULL) {
gBS->LocateProtocol (
- &gEdkiiDeviceSecurityProtocolGuid,
- NULL,
- (VOID **) &mDeviceSecurityProtocol
- );
+ &gEdkiiDeviceSecurityProtocolGuid,
+ NULL,
+ (VOID **)&mDeviceSecurityProtocol
+ );
}
if (PcdGetBool (PcdPciDisableBusEnumeration)) {
gFullEnumeration = FALSE;
} else {
- gFullEnumeration = (BOOLEAN) ((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
+ gFullEnumeration = (BOOLEAN)((SearchHostBridgeHandle (Controller) ? FALSE : TRUE));
}
//
@@ -313,7 +314,7 @@ PciBusDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID **) &ParentDevicePath,
+ (VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -342,7 +343,7 @@ PciBusDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -399,10 +400,10 @@ PciBusDriverBindingStart ( EFI_STATUS
EFIAPI
PciBusDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -414,17 +415,17 @@ PciBusDriverBindingStop ( // Close the bus driver
//
gBS->CloseProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
gBS->CloseProtocol (
- Controller,
- &gEfiPciRootBridgeIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
DestroyRootBridgeByHandle (
Controller
@@ -440,7 +441,6 @@ PciBusDriverBindingStop ( AllChildrenStopped = TRUE;
for (Index = 0; Index < NumberOfChildren; Index++) {
-
//
// De register all the pci device
//
@@ -457,4 +457,3 @@ PciBusDriverBindingStop ( return EFI_SUCCESS;
}
-
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h index a619a68526..4b58c3ea9b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#ifndef _EFI_PCI_BUS_H_
#define _EFI_PCI_BUS_H_
@@ -44,15 +43,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <IndustryStandard/PeImage.h>
#include <IndustryStandard/Acpi.h>
-typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
-typedef struct _PCI_BAR PCI_BAR;
+typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
+typedef struct _PCI_BAR PCI_BAR;
#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
-#define EFI_PCI_IOV_POLICY_ARI 0x0001
-#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
-#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
+#define EFI_PCI_IOV_POLICY_ARI 0x0001
+#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
+#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
typedef enum {
PciBarTypeUnknown = 0,
@@ -81,11 +80,11 @@ typedef enum { #include "PciHotPlugSupport.h"
#include "PciLib.h"
-#define VGABASE1 0x3B0
-#define VGALIMIT1 0x3BB
+#define VGABASE1 0x3B0
+#define VGALIMIT1 0x3BB
-#define VGABASE2 0x3C0
-#define VGALIMIT2 0x3DF
+#define VGABASE2 0x3C0
+#define VGALIMIT2 0x3DF
#define ISABASE 0x100
#define ISALIMIT 0x3FF
@@ -94,63 +93,63 @@ typedef enum { // PCI BAR parameters
//
struct _PCI_BAR {
- UINT64 BaseAddress;
- UINT64 Length;
- UINT64 Alignment;
- PCI_BAR_TYPE BarType;
- BOOLEAN BarTypeFixed;
- UINT16 Offset;
+ UINT64 BaseAddress;
+ UINT64 Length;
+ UINT64 Alignment;
+ PCI_BAR_TYPE BarType;
+ BOOLEAN BarTypeFixed;
+ UINT16 Offset;
};
//
// defined in PCI Card Specification, 8.0
//
-#define PCI_CARD_MEMORY_BASE_0 0x1C
-#define PCI_CARD_MEMORY_LIMIT_0 0x20
-#define PCI_CARD_MEMORY_BASE_1 0x24
-#define PCI_CARD_MEMORY_LIMIT_1 0x28
-#define PCI_CARD_IO_BASE_0_LOWER 0x2C
-#define PCI_CARD_IO_BASE_0_UPPER 0x2E
-#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
-#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
-#define PCI_CARD_IO_BASE_1_LOWER 0x34
-#define PCI_CARD_IO_BASE_1_UPPER 0x36
-#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
-#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
-#define PCI_CARD_BRIDGE_CONTROL 0x3E
-
-#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
-#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
-
-#define RB_IO_RANGE 1
-#define RB_MEM32_RANGE 2
-#define RB_PMEM32_RANGE 3
-#define RB_MEM64_RANGE 4
-#define RB_PMEM64_RANGE 5
-
-#define PPB_BAR_0 0
-#define PPB_BAR_1 1
-#define PPB_IO_RANGE 2
-#define PPB_MEM32_RANGE 3
-#define PPB_PMEM32_RANGE 4
-#define PPB_PMEM64_RANGE 5
-#define PPB_MEM64_RANGE 0xFF
-
-#define P2C_BAR_0 0
-#define P2C_MEM_1 1
-#define P2C_MEM_2 2
-#define P2C_IO_1 3
-#define P2C_IO_2 4
-
-#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
-#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
-#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
-#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
-#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
-#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
-#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
-
-#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
+#define PCI_CARD_MEMORY_BASE_0 0x1C
+#define PCI_CARD_MEMORY_LIMIT_0 0x20
+#define PCI_CARD_MEMORY_BASE_1 0x24
+#define PCI_CARD_MEMORY_LIMIT_1 0x28
+#define PCI_CARD_IO_BASE_0_LOWER 0x2C
+#define PCI_CARD_IO_BASE_0_UPPER 0x2E
+#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
+#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
+#define PCI_CARD_IO_BASE_1_LOWER 0x34
+#define PCI_CARD_IO_BASE_1_UPPER 0x36
+#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
+#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
+#define PCI_CARD_BRIDGE_CONTROL 0x3E
+
+#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
+#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
+
+#define RB_IO_RANGE 1
+#define RB_MEM32_RANGE 2
+#define RB_PMEM32_RANGE 3
+#define RB_MEM64_RANGE 4
+#define RB_PMEM64_RANGE 5
+
+#define PPB_BAR_0 0
+#define PPB_BAR_1 1
+#define PPB_IO_RANGE 2
+#define PPB_MEM32_RANGE 3
+#define PPB_PMEM32_RANGE 4
+#define PPB_PMEM64_RANGE 5
+#define PPB_MEM64_RANGE 0xFF
+
+#define P2C_BAR_0 0
+#define P2C_MEM_1 1
+#define P2C_MEM_2 2
+#define P2C_IO_1 3
+#define P2C_IO_2 4
+
+#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
+#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
+#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
+#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
+#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
+#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
+#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
+
+#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
//
// Define option for attribute
@@ -158,130 +157,130 @@ struct _PCI_BAR { #define EFI_SET_SUPPORTS 0
#define EFI_SET_ATTRIBUTES 1
-#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
+#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
struct _PCI_IO_DEVICE {
- UINT32 Signature;
- EFI_HANDLE Handle;
- EFI_PCI_IO_PROTOCOL PciIo;
- LIST_ENTRY Link;
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PROTOCOL PciIo;
+ LIST_ENTRY Link;
- EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- EFI_LOAD_FILE2_PROTOCOL LoadFile2;
+ EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_LOAD_FILE2_PROTOCOL LoadFile2;
//
// PCI configuration space header type
//
- PCI_TYPE00 Pci;
+ PCI_TYPE00 Pci;
//
// Bus number, Device number, Function number
//
- UINT8 BusNumber;
- UINT8 DeviceNumber;
- UINT8 FunctionNumber;
+ UINT8 BusNumber;
+ UINT8 DeviceNumber;
+ UINT8 FunctionNumber;
//
// BAR for this PCI Device
//
- PCI_BAR PciBar[PCI_MAX_BAR];
+ PCI_BAR PciBar[PCI_MAX_BAR];
//
// The bridge device this pci device is subject to
//
- PCI_IO_DEVICE *Parent;
+ PCI_IO_DEVICE *Parent;
//
// A linked list for children Pci Device if it is bridge device
//
- LIST_ENTRY ChildList;
+ LIST_ENTRY ChildList;
//
// TRUE if the PCI bus driver creates the handle for this PCI device
//
- BOOLEAN Registered;
+ BOOLEAN Registered;
//
// TRUE if the PCI bus driver successfully allocates the resource required by
// this PCI device
//
- BOOLEAN Allocated;
+ BOOLEAN Allocated;
//
// The attribute this PCI device currently set
//
- UINT64 Attributes;
+ UINT64 Attributes;
//
// The attributes this PCI device actually supports
//
- UINT64 Supports;
+ UINT64 Supports;
//
// The resource decode the bridge supports
//
- UINT32 Decodes;
+ UINT32 Decodes;
//
// TRUE if the ROM image is from the PCI Option ROM BAR
//
- BOOLEAN EmbeddedRom;
+ BOOLEAN EmbeddedRom;
//
// The OptionRom Size
//
- UINT32 RomSize;
+ UINT32 RomSize;
//
// TRUE if all OpROM (in device or in platform specific position) have been processed
//
- BOOLEAN AllOpRomProcessed;
+ BOOLEAN AllOpRomProcessed;
//
// TRUE if there is any EFI driver in the OptionRom
//
- BOOLEAN BusOverride;
+ BOOLEAN BusOverride;
//
// A list tracking reserved resource on a bridge device
//
- LIST_ENTRY ReservedResourceList;
+ LIST_ENTRY ReservedResourceList;
//
// A list tracking image handle of platform specific overriding driver
//
- LIST_ENTRY OptionRomDriverList;
+ LIST_ENTRY OptionRomDriverList;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
- EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
+ EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
//
// Bus number ranges for a PCI Root Bridge device
//
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
- BOOLEAN IsPciExp;
+ BOOLEAN IsPciExp;
//
// For SR-IOV
//
- UINT8 PciExpressCapabilityOffset;
- UINT32 AriCapabilityOffset;
- UINT32 SrIovCapabilityOffset;
- UINT32 MrIovCapabilityOffset;
- PCI_BAR VfPciBar[PCI_MAX_BAR];
- UINT32 SystemPageSize;
- UINT16 InitialVFs;
- UINT16 ReservedBusNum;
+ UINT8 PciExpressCapabilityOffset;
+ UINT32 AriCapabilityOffset;
+ UINT32 SrIovCapabilityOffset;
+ UINT32 MrIovCapabilityOffset;
+ PCI_BAR VfPciBar[PCI_MAX_BAR];
+ UINT32 SystemPageSize;
+ UINT16 InitialVFs;
+ UINT16 ReservedBusNum;
//
// Per PCI to PCI Bridge spec, I/O window is 4K aligned,
// but some chipsets support non-standard I/O window alignments less than 4K.
// This field is used to support this case.
//
- UINT16 BridgeIoAlignment;
- UINT32 ResizableBarOffset;
- UINT32 ResizableBarNumber;
+ UINT16 BridgeIoAlignment;
+ UINT32 ResizableBarOffset;
+ UINT32 ResizableBarNumber;
};
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
@@ -296,24 +295,22 @@ struct _PCI_IO_DEVICE { #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
-
-
//
// Global Variables
//
-extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
-extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
-extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
-extern BOOLEAN gFullEnumeration;
-extern UINTN gPciHostBridgeNumber;
-extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
-extern UINT64 gAllOne;
-extern UINT64 gAllZero;
-extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
-extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
-extern BOOLEAN mReserveIsaAliases;
-extern BOOLEAN mReserveVgaAliases;
+extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
+extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
+extern BOOLEAN gFullEnumeration;
+extern UINTN gPciHostBridgeNumber;
+extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
+extern UINT64 gAllOne;
+extern UINT64 gAllZero;
+extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
+extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
+extern BOOLEAN mReserveIsaAliases;
+extern BOOLEAN mReserveVgaAliases;
/**
Macro that checks whether device is a GFX device.
@@ -324,7 +321,7 @@ extern BOOLEAN mReserveVgaAliases; @retval FALSE Device is not a GFX device.
**/
-#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
+#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
/**
Test to see if this driver supports ControllerHandle. Any ControllerHandle
@@ -343,9 +340,9 @@ extern BOOLEAN mReserveVgaAliases; EFI_STATUS
EFIAPI
PciBusDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -365,9 +362,9 @@ PciBusDriverBindingSupported ( EFI_STATUS
EFIAPI
PciBusDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -387,10 +384,10 @@ PciBusDriverBindingStart ( EFI_STATUS
EFIAPI
PciBusDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c index 6283d60220..ba4b099bc5 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c @@ -22,19 +22,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
PciOperateRegister (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT16 Command,
- IN UINT8 Offset,
- IN UINT8 Operation,
- OUT UINT16 *PtrCommand
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 Command,
+ IN UINT8 Offset,
+ IN UINT8 Operation,
+ OUT UINT16 *PtrCommand
)
{
- UINT16 OldCommand;
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 OldCommand;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
- OldCommand = 0;
- PciIo = &PciIoDevice->PciIo;
+ OldCommand = 0;
+ PciIo = &PciIoDevice->PciIo;
if (Operation != EFI_SET_REGISTER) {
Status = PciIo->Pci.Read (
@@ -52,9 +52,9 @@ PciOperateRegister ( }
if (Operation == EFI_ENABLE_REGISTER) {
- OldCommand = (UINT16) (OldCommand | Command);
+ OldCommand = (UINT16)(OldCommand | Command);
} else if (Operation == EFI_DISABLE_REGISTER) {
- OldCommand = (UINT16) (OldCommand & ~(Command));
+ OldCommand = (UINT16)(OldCommand & ~(Command));
} else {
OldCommand = Command;
}
@@ -124,10 +124,8 @@ LocateCapabilityRegBlock ( if (*Offset != 0) {
CapabilityPtr = *Offset;
} else {
-
CapabilityPtr = 0;
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
-
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
@@ -136,7 +134,6 @@ LocateCapabilityRegBlock ( &CapabilityPtr
);
} else {
-
PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint8,
@@ -156,12 +153,12 @@ LocateCapabilityRegBlock ( &CapabilityEntry
);
- CapabilityID = (UINT8) CapabilityEntry;
+ CapabilityID = (UINT8)CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;
if (NextRegBlock != NULL) {
- *NextRegBlock = (UINT8) (CapabilityEntry >> 8);
+ *NextRegBlock = (UINT8)(CapabilityEntry >> 8);
}
return EFI_SUCCESS;
@@ -171,11 +168,11 @@ LocateCapabilityRegBlock ( // Certain PCI device may incorrectly have capability pointing to itself,
// break to avoid dead loop.
//
- if (CapabilityPtr == (UINT8) (CapabilityEntry >> 8)) {
+ if (CapabilityPtr == (UINT8)(CapabilityEntry >> 8)) {
break;
}
- CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
+ CapabilityPtr = (UINT8)(CapabilityEntry >> 8);
}
return EFI_NOT_FOUND;
@@ -196,16 +193,16 @@ LocateCapabilityRegBlock ( **/
EFI_STATUS
LocatePciExpressCapabilityRegBlock (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT16 CapId,
- IN OUT UINT32 *Offset,
- OUT UINT32 *NextRegBlock OPTIONAL
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 CapId,
+ IN OUT UINT32 *Offset,
+ OUT UINT32 *NextRegBlock OPTIONAL
)
{
- EFI_STATUS Status;
- UINT32 CapabilityPtr;
- UINT32 CapabilityEntry;
- UINT16 CapabilityID;
+ EFI_STATUS Status;
+ UINT32 CapabilityPtr;
+ UINT32 CapabilityEntry;
+ UINT16 CapabilityID;
//
// To check the capability of this device supports
@@ -225,13 +222,13 @@ LocatePciExpressCapabilityRegBlock ( // Mask it to DWORD alignment per PCI spec
//
CapabilityPtr &= 0xFFC;
- Status = PciIoDevice->PciIo.Pci.Read (
- &PciIoDevice->PciIo,
- EfiPciIoWidthUint32,
- CapabilityPtr,
- 1,
- &CapabilityEntry
- );
+ Status = PciIoDevice->PciIo.Pci.Read (
+ &PciIoDevice->PciIo,
+ EfiPciIoWidthUint32,
+ CapabilityPtr,
+ 1,
+ &CapabilityEntry
+ );
if (EFI_ERROR (Status)) {
break;
}
@@ -249,7 +246,7 @@ LocatePciExpressCapabilityRegBlock ( break;
}
- CapabilityID = (UINT16) CapabilityEntry;
+ CapabilityID = (UINT16)CapabilityEntry;
if (CapabilityID == CapId) {
*Offset = CapabilityPtr;
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h index cf9903270d..1822afea97 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h @@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#ifndef _EFI_PCI_COMMAND_H_
#define _EFI_PCI_COMMAND_H_
@@ -16,7 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
-#define EFI_PCI_COMMAND_BITS_OWNED ( \
+#define EFI_PCI_COMMAND_BITS_OWNED ( \
EFI_PCI_COMMAND_IO_SPACE | \
EFI_PCI_COMMAND_MEMORY_SPACE | \
EFI_PCI_COMMAND_BUS_MASTER | \
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
-#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
+#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
EFI_PCI_BRIDGE_CONTROL_ISA | \
EFI_PCI_BRIDGE_CONTROL_VGA | \
EFI_PCI_BRIDGE_CONTROL_VGA_16 | \
@@ -44,13 +43,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // They should be cleared at the beginning. The other registers
// are owned by chipset, we should not touch them.
//
-#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
+#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
EFI_PCI_BRIDGE_CONTROL_ISA | \
EFI_PCI_BRIDGE_CONTROL_VGA | \
EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
)
-
#define EFI_GET_REGISTER 1
#define EFI_SET_REGISTER 2
#define EFI_ENABLE_REGISTER 3
@@ -70,11 +68,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
PciOperateRegister (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT16 Command,
- IN UINT8 Offset,
- IN UINT8 Operation,
- OUT UINT16 *PtrCommand
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 Command,
+ IN UINT8 Offset,
+ IN UINT8 Operation,
+ OUT UINT16 *PtrCommand
);
/**
@@ -127,10 +125,10 @@ LocateCapabilityRegBlock ( **/
EFI_STATUS
LocatePciExpressCapabilityRegBlock (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT16 CapId,
- IN OUT UINT32 *Offset,
- OUT UINT32 *NextRegBlock OPTIONAL
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 CapId,
+ IN OUT UINT32 *Offset,
+ OUT UINT32 *NextRegBlock OPTIONAL
);
/**
@@ -142,7 +140,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_READ_COMMAND_REGISTER(a,b) \
+#define PCI_READ_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
/**
@@ -154,7 +152,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_SET_COMMAND_REGISTER(a,b) \
+#define PCI_SET_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
/**
@@ -166,7 +164,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_ENABLE_COMMAND_REGISTER(a,b) \
+#define PCI_ENABLE_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
/**
@@ -178,7 +176,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_DISABLE_COMMAND_REGISTER(a,b) \
+#define PCI_DISABLE_COMMAND_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
/**
@@ -190,7 +188,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \
+#define PCI_READ_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
/**
@@ -202,7 +200,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \
+#define PCI_SET_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
/**
@@ -214,7 +212,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \
+#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
/**
@@ -226,7 +224,7 @@ LocatePciExpressCapabilityRegBlock ( @return status of PciIo operation
**/
-#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \
+#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a, b) \
PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index 292dd25da8..581e9075ad 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -35,7 +35,7 @@ InitializePciDevicePool ( **/
VOID
InsertRootBridge (
- IN PCI_IO_DEVICE *RootBridge
+ IN PCI_IO_DEVICE *RootBridge
)
{
InsertTailList (&mPciDevicePool, &(RootBridge->Link));
@@ -51,8 +51,8 @@ InsertRootBridge ( **/
VOID
InsertPciDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_IO_DEVICE *PciDeviceNode
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_IO_DEVICE *PciDeviceNode
)
{
InsertTailList (&Bridge->ChildList, &(PciDeviceNode->Link));
@@ -67,7 +67,7 @@ InsertPciDevice ( **/
VOID
DestroyRootBridge (
- IN PCI_IO_DEVICE *RootBridge
+ IN PCI_IO_DEVICE *RootBridge
)
{
DestroyPciDeviceTree (RootBridge);
@@ -85,7 +85,7 @@ DestroyRootBridge ( **/
VOID
FreePciDevice (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
ASSERT (PciIoDevice != NULL);
@@ -116,14 +116,13 @@ FreePciDevice ( **/
VOID
DestroyPciDeviceTree (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
)
{
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
while (!IsListEmpty (&Bridge->ChildList)) {
-
CurrentLink = Bridge->ChildList.ForwardLink;
//
@@ -156,12 +155,11 @@ DestroyPciDeviceTree ( **/
EFI_STATUS
DestroyRootBridgeByHandle (
- IN EFI_HANDLE Controller
+ IN EFI_HANDLE Controller
)
{
-
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
CurrentLink = mPciDevicePool.ForwardLink;
@@ -169,7 +167,6 @@ DestroyRootBridgeByHandle ( Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (Temp->Handle == Controller) {
-
RemoveEntryList (CurrentLink);
DestroyPciDeviceTree (Temp);
@@ -202,17 +199,17 @@ DestroyRootBridgeByHandle ( **/
EFI_STATUS
RegisterPciDevice (
- IN EFI_HANDLE Controller,
- IN PCI_IO_DEVICE *PciIoDevice,
- OUT EFI_HANDLE *Handle OPTIONAL
+ IN EFI_HANDLE Controller,
+ IN PCI_IO_DEVICE *PciIoDevice,
+ OUT EFI_HANDLE *Handle OPTIONAL
)
{
- EFI_STATUS Status;
- VOID *PlatformOpRomBuffer;
- UINTN PlatformOpRomSize;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT8 Data8;
- BOOLEAN HasEfiImage;
+ EFI_STATUS Status;
+ VOID *PlatformOpRomBuffer;
+ UINTN PlatformOpRomSize;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 Data8;
+ BOOLEAN HasEfiImage;
//
// Install the pciio protocol, device path protocol
@@ -240,7 +237,6 @@ RegisterPciDevice ( // Process OpRom
//
if (!PciIoDevice->AllOpRomProcessed) {
-
//
// Get the OpRom provided by platform
//
@@ -253,7 +249,7 @@ RegisterPciDevice ( );
if (!EFI_ERROR (Status)) {
PciIoDevice->EmbeddedRom = FALSE;
- PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;
+ PciIoDevice->RomSize = (UINT32)PlatformOpRomSize;
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
//
@@ -279,7 +275,7 @@ RegisterPciDevice ( );
if (!EFI_ERROR (Status)) {
PciIoDevice->EmbeddedRom = FALSE;
- PciIoDevice->RomSize = (UINT32) PlatformOpRomSize;
+ PciIoDevice->RomSize = (UINT32)PlatformOpRomSize;
PciIoDevice->PciIo.RomSize = PlatformOpRomSize;
PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
//
@@ -324,9 +320,7 @@ RegisterPciDevice ( }
}
-
if (!PciIoDevice->AllOpRomProcessed) {
-
PciIoDevice->AllOpRomProcessed = TRUE;
//
@@ -374,7 +368,7 @@ RegisterPciDevice ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &(PciIoDevice->PciRootBridgeIo),
+ (VOID **)&(PciIoDevice->PciRootBridgeIo),
gPciBusDriverBinding.DriverBindingHandle,
PciIoDevice->Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -405,15 +399,14 @@ RegisterPciDevice ( **/
VOID
RemoveAllPciDeviceOnBridge (
- EFI_HANDLE RootBridgeHandle,
- PCI_IO_DEVICE *Bridge
+ EFI_HANDLE RootBridgeHandle,
+ PCI_IO_DEVICE *Bridge
)
{
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
while (!IsListEmpty (&Bridge->ChildList)) {
-
CurrentLink = Bridge->ChildList.ForwardLink;
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
@@ -453,22 +446,22 @@ RemoveAllPciDeviceOnBridge ( **/
EFI_STATUS
DeRegisterPciDevice (
- IN EFI_HANDLE Controller,
- IN EFI_HANDLE Handle
+ IN EFI_HANDLE Controller,
+ IN EFI_HANDLE Handle
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
- PCI_IO_DEVICE *Node;
- LIST_ENTRY *CurrentLink;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *Node;
+ LIST_ENTRY *CurrentLink;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Status = gBS->OpenProtocol (
Handle,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -488,12 +481,11 @@ DeRegisterPciDevice ( //
if (!IsListEmpty (&PciIoDevice->ChildList)) {
-
CurrentLink = PciIoDevice->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {
- Node = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
- Status = DeRegisterPciDevice (Controller, Node->Handle);
+ Node = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
+ Status = DeRegisterPciDevice (Controller, Node->Handle);
if (EFI_ERROR (Status)) {
return Status;
@@ -559,22 +551,22 @@ DeRegisterPciDevice ( NULL
);
}
+
//
// Restore Status
//
Status = EFI_SUCCESS;
}
-
if (EFI_ERROR (Status)) {
gBS->OpenProtocol (
- Controller,
- &gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
- gPciBusDriverBinding.DriverBindingHandle,
- Handle,
- EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
- );
+ Controller,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ (VOID **)&PciRootBridgeIo,
+ gPciBusDriverBinding.DriverBindingHandle,
+ Handle,
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
+ );
return Status;
}
@@ -586,7 +578,6 @@ DeRegisterPciDevice ( PciIoDevice->Registered = FALSE;
PciIoDevice->Handle = NULL;
} else {
-
//
// Handle may be closed before
//
@@ -613,11 +604,11 @@ DeRegisterPciDevice ( **/
EFI_STATUS
StartPciDevicesOnBridge (
- IN EFI_HANDLE Controller,
- IN PCI_IO_DEVICE *RootBridge,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
- IN OUT UINT8 *NumberOfChildren,
- IN OUT EFI_HANDLE *ChildHandleBuffer
+ IN EFI_HANDLE Controller,
+ IN PCI_IO_DEVICE *RootBridge,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
+ IN OUT UINT8 *NumberOfChildren,
+ IN OUT EFI_HANDLE *ChildHandleBuffer
)
{
@@ -632,14 +623,13 @@ StartPciDevicesOnBridge ( CurrentLink = RootBridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &RootBridge->ChildList) {
-
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (RemainingDevicePath != NULL) {
-
Node.DevPath = RemainingDevicePath;
- if (Node.Pci->Device != PciIoDevice->DeviceNumber ||
- Node.Pci->Function != PciIoDevice->FunctionNumber) {
+ if ((Node.Pci->Device != PciIoDevice->DeviceNumber) ||
+ (Node.Pci->Function != PciIoDevice->FunctionNumber))
+ {
CurrentLink = CurrentLink->ForwardLink;
continue;
}
@@ -661,10 +651,9 @@ StartPciDevicesOnBridge ( PciIoDevice,
NULL
);
-
}
- if (NumberOfChildren != NULL && ChildHandleBuffer != NULL && PciIoDevice->Registered) {
+ if ((NumberOfChildren != NULL) && (ChildHandleBuffer != NULL) && PciIoDevice->Registered) {
ChildHandleBuffer[*NumberOfChildren] = PciIoDevice->Handle;
(*NumberOfChildren)++;
}
@@ -705,15 +694,12 @@ StartPciDevicesOnBridge ( return Status;
} else {
-
//
// Currently, the PCI bus driver only support PCI-PCI bridge
//
return EFI_UNSUPPORTED;
}
-
} else {
-
//
// If remaining device path is NULL,
// try to enable all the pci devices under this bridge
@@ -724,10 +710,9 @@ StartPciDevicesOnBridge ( PciIoDevice,
NULL
);
-
}
- if (NumberOfChildren != NULL && ChildHandleBuffer != NULL && PciIoDevice->Registered) {
+ if ((NumberOfChildren != NULL) && (ChildHandleBuffer != NULL) && PciIoDevice->Registered) {
ChildHandleBuffer[*NumberOfChildren] = PciIoDevice->Handle;
(*NumberOfChildren)++;
}
@@ -754,7 +739,6 @@ StartPciDevicesOnBridge ( Supports,
NULL
);
-
}
CurrentLink = CurrentLink->ForwardLink;
@@ -780,12 +764,12 @@ StartPciDevicesOnBridge ( **/
EFI_STATUS
StartPciDevices (
- IN EFI_HANDLE Controller
+ IN EFI_HANDLE Controller
)
{
- PCI_IO_DEVICE *RootBridge;
- EFI_HANDLE ThisHostBridge;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *RootBridge;
+ EFI_HANDLE ThisHostBridge;
+ LIST_ENTRY *CurrentLink;
RootBridge = GetRootBridgeByHandle (Controller);
ASSERT (RootBridge != NULL);
@@ -794,19 +778,18 @@ StartPciDevices ( CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
-
RootBridge = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
//
// Locate the right root bridge to start
//
if (RootBridge->PciRootBridgeIo->ParentHandle == ThisHostBridge) {
StartPciDevicesOnBridge (
- RootBridge->Handle,
- RootBridge,
- NULL,
- NULL,
- NULL
- );
+ RootBridge->Handle,
+ RootBridge,
+ NULL,
+ NULL,
+ NULL
+ );
}
CurrentLink = CurrentLink->ForwardLink;
@@ -826,27 +809,27 @@ StartPciDevices ( **/
PCI_IO_DEVICE *
CreateRootBridge (
- IN EFI_HANDLE RootBridgeHandle
+ IN EFI_HANDLE RootBridgeHandle
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *Dev;
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *Dev;
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Dev = AllocateZeroPool (sizeof (PCI_IO_DEVICE));
if (Dev == NULL) {
return NULL;
}
- Dev->Signature = PCI_IO_DEVICE_SIGNATURE;
- Dev->Handle = RootBridgeHandle;
+ Dev->Signature = PCI_IO_DEVICE_SIGNATURE;
+ Dev->Handle = RootBridgeHandle;
InitializeListHead (&Dev->ChildList);
Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiDevicePathProtocolGuid,
- (VOID **) &ParentDevicePath,
+ (VOID **)&ParentDevicePath,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -868,7 +851,7 @@ CreateRootBridge ( Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -909,16 +892,15 @@ CreateRootBridge ( **/
PCI_IO_DEVICE *
GetRootBridgeByHandle (
- EFI_HANDLE RootBridgeHandle
+ EFI_HANDLE RootBridgeHandle
)
{
- PCI_IO_DEVICE *RootBridgeDev;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *RootBridgeDev;
+ LIST_ENTRY *CurrentLink;
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
-
RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (RootBridgeDev->Handle == RootBridgeHandle) {
return RootBridgeDev;
@@ -942,18 +924,16 @@ GetRootBridgeByHandle ( **/
BOOLEAN
PciDeviceExisted (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
-
- PCI_IO_DEVICE *Temp;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
-
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (Temp == PciIoDevice) {
@@ -982,20 +962,18 @@ PciDeviceExisted ( **/
PCI_IO_DEVICE *
LocateVgaDeviceOnHostBridge (
- IN EFI_HANDLE HostBridgeHandle
+ IN EFI_HANDLE HostBridgeHandle
)
{
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *PciIoDevice;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *PciIoDevice;
CurrentLink = mPciDevicePool.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &mPciDevicePool) {
-
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
- if (PciIoDevice->PciRootBridgeIo->ParentHandle== HostBridgeHandle) {
-
+ if (PciIoDevice->PciRootBridgeIo->ParentHandle == HostBridgeHandle) {
PciIoDevice = LocateVgaDevice (PciIoDevice);
if (PciIoDevice != NULL) {
@@ -1019,28 +997,27 @@ LocateVgaDeviceOnHostBridge ( **/
PCI_IO_DEVICE *
LocateVgaDevice (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
)
{
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *PciIoDevice;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *PciIoDevice;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
-
PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
- if (IS_PCI_VGA(&PciIoDevice->Pci) &&
- (PciIoDevice->Attributes &
- (EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY |
- EFI_PCI_IO_ATTRIBUTE_VGA_IO |
- EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
+ if (IS_PCI_VGA (&PciIoDevice->Pci) &&
+ ((PciIoDevice->Attributes &
+ (EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY |
+ EFI_PCI_IO_ATTRIBUTE_VGA_IO |
+ EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0))
+ {
return PciIoDevice;
}
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
-
PciIoDevice = LocateVgaDevice (PciIoDevice);
if (PciIoDevice != NULL) {
@@ -1053,4 +1030,3 @@ LocateVgaDevice ( return NULL;
}
-
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h index 3dae540da7..ca367e7b92 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h @@ -26,7 +26,7 @@ InitializePciDevicePool ( **/
VOID
InsertRootBridge (
- IN PCI_IO_DEVICE *RootBridge
+ IN PCI_IO_DEVICE *RootBridge
);
/**
@@ -39,8 +39,8 @@ InsertRootBridge ( **/
VOID
InsertPciDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_IO_DEVICE *PciDeviceNode
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_IO_DEVICE *PciDeviceNode
);
/**
@@ -51,7 +51,7 @@ InsertPciDevice ( **/
VOID
DestroyRootBridge (
- IN PCI_IO_DEVICE *RootBridge
+ IN PCI_IO_DEVICE *RootBridge
);
/**
@@ -63,7 +63,7 @@ DestroyRootBridge ( **/
VOID
DestroyPciDeviceTree (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
);
/**
@@ -81,7 +81,7 @@ DestroyPciDeviceTree ( **/
EFI_STATUS
DestroyRootBridgeByHandle (
- IN EFI_HANDLE Controller
+ IN EFI_HANDLE Controller
);
/**
@@ -101,9 +101,9 @@ DestroyRootBridgeByHandle ( **/
EFI_STATUS
RegisterPciDevice (
- IN EFI_HANDLE Controller,
- IN PCI_IO_DEVICE *PciIoDevice,
- OUT EFI_HANDLE *Handle OPTIONAL
+ IN EFI_HANDLE Controller,
+ IN PCI_IO_DEVICE *PciIoDevice,
+ OUT EFI_HANDLE *Handle OPTIONAL
);
/**
@@ -116,8 +116,8 @@ RegisterPciDevice ( **/
VOID
RemoveAllPciDeviceOnBridge (
- EFI_HANDLE RootBridgeHandle,
- PCI_IO_DEVICE *Bridge
+ EFI_HANDLE RootBridgeHandle,
+ PCI_IO_DEVICE *Bridge
);
/**
@@ -135,8 +135,8 @@ RemoveAllPciDeviceOnBridge ( **/
EFI_STATUS
DeRegisterPciDevice (
- IN EFI_HANDLE Controller,
- IN EFI_HANDLE Handle
+ IN EFI_HANDLE Controller,
+ IN EFI_HANDLE Handle
);
/**
@@ -156,11 +156,11 @@ DeRegisterPciDevice ( **/
EFI_STATUS
StartPciDevicesOnBridge (
- IN EFI_HANDLE Controller,
- IN PCI_IO_DEVICE *RootBridge,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
- IN OUT UINT8 *NumberOfChildren,
- IN OUT EFI_HANDLE *ChildHandleBuffer
+ IN EFI_HANDLE Controller,
+ IN PCI_IO_DEVICE *RootBridge,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
+ IN OUT UINT8 *NumberOfChildren,
+ IN OUT EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -175,7 +175,7 @@ StartPciDevicesOnBridge ( **/
EFI_STATUS
StartPciDevices (
- IN EFI_HANDLE Controller
+ IN EFI_HANDLE Controller
);
/**
@@ -189,7 +189,7 @@ StartPciDevices ( **/
PCI_IO_DEVICE *
CreateRootBridge (
- IN EFI_HANDLE RootBridgeHandle
+ IN EFI_HANDLE RootBridgeHandle
);
/**
@@ -203,10 +203,9 @@ CreateRootBridge ( **/
PCI_IO_DEVICE *
GetRootBridgeByHandle (
- EFI_HANDLE RootBridgeHandle
+ EFI_HANDLE RootBridgeHandle
);
-
/**
Judge whether Pci device existed.
@@ -219,8 +218,8 @@ GetRootBridgeByHandle ( **/
BOOLEAN
PciDeviceExisted (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -233,7 +232,7 @@ PciDeviceExisted ( **/
PCI_IO_DEVICE *
LocateVgaDeviceOnHostBridge (
- IN EFI_HANDLE HostBridgeHandle
+ IN EFI_HANDLE HostBridgeHandle
);
/**
@@ -246,10 +245,9 @@ LocateVgaDeviceOnHostBridge ( **/
PCI_IO_DEVICE *
LocateVgaDevice (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
);
-
/**
Destroy a pci device node.
@@ -260,7 +258,7 @@ LocateVgaDevice ( **/
VOID
FreePciDevice (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c index 3531e6b6ef..c829408bcb 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c @@ -16,7 +16,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
InitializePciDriverOverrideInstance (
- IN OUT PCI_IO_DEVICE *PciIoDevice
+ IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
PciIoDevice->PciDriverOverride.GetDriver = GetDriver;
@@ -31,16 +31,16 @@ InitializePciDriverOverrideInstance ( **/
EFI_HANDLE
LocateImageHandle (
- IN EFI_DEVICE_PATH_PROTOCOL *ImagePath
+ IN EFI_DEVICE_PATH_PROTOCOL *ImagePath
)
{
- EFI_STATUS Status;
- EFI_HANDLE *Handles;
- UINTN Index;
- UINTN HandleNum;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- UINTN ImagePathSize;
- EFI_HANDLE ImageHandle;
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN Index;
+ UINTN HandleNum;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN ImagePathSize;
+ EFI_HANDLE ImageHandle;
Status = gBS->LocateHandleBuffer (
ByProtocol,
@@ -57,13 +57,15 @@ LocateImageHandle ( ImagePathSize = GetDevicePathSize (ImagePath);
for (Index = 0; Index < HandleNum; Index++) {
- Status = gBS->HandleProtocol (Handles[Index], &gEfiLoadedImageDevicePathProtocolGuid, (VOID **) &DevicePath);
+ Status = gBS->HandleProtocol (Handles[Index], &gEfiLoadedImageDevicePathProtocolGuid, (VOID **)&DevicePath);
if (EFI_ERROR (Status)) {
continue;
}
+
if ((ImagePathSize == GetDevicePathSize (DevicePath)) &&
(CompareMem (ImagePath, DevicePath, ImagePathSize) == 0)
- ) {
+ )
+ {
ImageHandle = Handles[Index];
break;
}
@@ -92,8 +94,8 @@ LocateImageHandle ( EFI_STATUS
EFIAPI
GetDriver (
- IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
- IN OUT EFI_HANDLE *DriverImageHandle
+ IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
+ IN OUT EFI_HANDLE *DriverImageHandle
)
{
PCI_IO_DEVICE *PciIoDevice;
@@ -103,12 +105,12 @@ GetDriver ( Override = NULL;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS (This);
- ReturnNext = (BOOLEAN) (*DriverImageHandle == NULL);
+ ReturnNext = (BOOLEAN)(*DriverImageHandle == NULL);
for ( Link = GetFirstNode (&PciIoDevice->OptionRomDriverList)
- ; !IsNull (&PciIoDevice->OptionRomDriverList, Link)
- ; Link = GetNextNode (&PciIoDevice->OptionRomDriverList, Link)
- ) {
-
+ ; !IsNull (&PciIoDevice->OptionRomDriverList, Link)
+ ; Link = GetNextNode (&PciIoDevice->OptionRomDriverList, Link)
+ )
+ {
Override = DRIVER_OVERRIDE_FROM_LINK (Link);
if (ReturnNext) {
@@ -159,12 +161,12 @@ GetDriver ( **/
EFI_STATUS
AddDriver (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN EFI_HANDLE DriverImageHandle,
- IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN EFI_HANDLE DriverImageHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
)
{
- PCI_DRIVER_OVERRIDE_LIST *Node;
+ PCI_DRIVER_OVERRIDE_LIST *Node;
//
// Caller should pass in either Image Handle or Image Path, but not both.
@@ -182,7 +184,6 @@ AddDriver ( InsertTailList (&PciIoDevice->OptionRomDriverList, &Node->Link);
- PciIoDevice->BusOverride = TRUE;
+ PciIoDevice->BusOverride = TRUE;
return EFI_SUCCESS;
}
-
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h index 03447a59c0..78d13d6482 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h @@ -6,23 +6,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#ifndef _EFI_PCI_DRIVER_OVERRRIDE_H_
#define _EFI_PCI_DRIVER_OVERRRIDE_H_
-#define DRIVER_OVERRIDE_SIGNATURE SIGNATURE_32 ('d', 'r', 'o', 'v')
+#define DRIVER_OVERRIDE_SIGNATURE SIGNATURE_32 ('d', 'r', 'o', 'v')
//
// PCI driver override driver image list
//
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- EFI_HANDLE DriverImageHandle;
- EFI_DEVICE_PATH_PROTOCOL *DriverImagePath;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ EFI_HANDLE DriverImageHandle;
+ EFI_DEVICE_PATH_PROTOCOL *DriverImagePath;
} PCI_DRIVER_OVERRIDE_LIST;
-
#define DRIVER_OVERRIDE_FROM_LINK(a) \
CR (a, PCI_DRIVER_OVERRIDE_LIST, Link, DRIVER_OVERRIDE_SIGNATURE)
@@ -34,7 +32,7 @@ typedef struct { **/
VOID
InitializePciDriverOverrideInstance (
- IN OUT PCI_IO_DEVICE *PciIoDevice
+ IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -51,12 +49,11 @@ InitializePciDriverOverrideInstance ( **/
EFI_STATUS
AddDriver (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN EFI_HANDLE DriverImageHandle,
- IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN EFI_HANDLE DriverImageHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath
);
-
/**
Uses a bus specific algorithm to retrieve a driver image handle for a controller.
@@ -76,8 +73,8 @@ AddDriver ( EFI_STATUS
EFIAPI
GetDriver (
- IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
- IN OUT EFI_HANDLE *DriverImageHandle
+ IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
+ IN OUT EFI_HANDLE *DriverImageHandle
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c index 99f8642f13..3f8c6e6da7 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c @@ -22,8 +22,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
PciEnumerator (
- IN EFI_HANDLE Controller,
- IN EFI_HANDLE HostBridgeHandle
+ IN EFI_HANDLE Controller,
+ IN EFI_HANDLE HostBridgeHandle
)
{
EFI_STATUS Status;
@@ -35,7 +35,7 @@ PciEnumerator ( Status = gBS->OpenProtocol (
HostBridgeHandle,
&gEfiPciHostBridgeResourceAllocationProtocolGuid,
- (VOID **) &PciResAlloc,
+ (VOID **)&PciResAlloc,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -117,22 +117,22 @@ PciRootBridgeEnumerator ( IN PCI_IO_DEVICE *RootBridgeDev
)
{
- EFI_STATUS Status;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;
- UINT8 SubBusNumber;
- UINT8 StartBusNumber;
- UINT8 PaddedBusRange;
- EFI_HANDLE RootBridgeHandle;
- UINT8 Desc;
- UINT64 AddrLen;
- UINT64 AddrRangeMin;
-
- SubBusNumber = 0;
- StartBusNumber = 0;
- PaddedBusRange = 0;
+ EFI_STATUS Status;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;
+ UINT8 SubBusNumber;
+ UINT8 StartBusNumber;
+ UINT8 PaddedBusRange;
+ EFI_HANDLE RootBridgeHandle;
+ UINT8 Desc;
+ UINT64 AddrLen;
+ UINT64 AddrRangeMin;
+
+ SubBusNumber = 0;
+ StartBusNumber = 0;
+ PaddedBusRange = 0;
//
// Get the root bridge handle
@@ -151,16 +151,17 @@ PciRootBridgeEnumerator ( Status = PciResAlloc->StartBusEnumeration (
PciResAlloc,
RootBridgeHandle,
- (VOID **) &Configuration
+ (VOID **)&Configuration
);
if (EFI_ERROR (Status)) {
return Status;
}
- if (Configuration == NULL || Configuration->Desc == ACPI_END_TAG_DESCRIPTOR) {
+ if ((Configuration == NULL) || (Configuration->Desc == ACPI_END_TAG_DESCRIPTOR)) {
return EFI_INVALID_PARAMETER;
}
+
RootBridgeDev->BusNumberRanges = Configuration;
//
@@ -173,16 +174,17 @@ PciRootBridgeEnumerator ( Configuration2 = Configuration3;
}
}
+
//
// All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,
// so only need to swap these two fields.
//
if (Configuration2 != Configuration1) {
- AddrRangeMin = Configuration1->AddrRangeMin;
+ AddrRangeMin = Configuration1->AddrRangeMin;
Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;
Configuration2->AddrRangeMin = AddrRangeMin;
- AddrLen = Configuration1->AddrLen;
+ AddrLen = Configuration1->AddrLen;
Configuration1->AddrLen = Configuration2->AddrLen;
Configuration2->AddrLen = AddrLen;
}
@@ -191,7 +193,7 @@ PciRootBridgeEnumerator ( //
// Get the bus number to start with
//
- StartBusNumber = (UINT8) (Configuration->AddrRangeMin);
+ StartBusNumber = (UINT8)(Configuration->AddrRangeMin);
//
// Initialize the subordinate bus number
@@ -204,23 +206,22 @@ PciRootBridgeEnumerator ( ResetAllPpbBusNumber (
RootBridgeDev,
StartBusNumber
- );
+ );
//
// Assign bus number
//
Status = PciScanBus (
- RootBridgeDev,
- StartBusNumber,
- &SubBusNumber,
- &PaddedBusRange
- );
+ RootBridgeDev,
+ StartBusNumber,
+ &SubBusNumber,
+ &PaddedBusRange
+ );
if (EFI_ERROR (Status)) {
return Status;
}
-
//
// Assign max bus number scanned
//
@@ -237,14 +238,15 @@ PciRootBridgeEnumerator ( while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {
Configuration++;
}
- AddrLen = Configuration->AddrLen;
+
+ AddrLen = Configuration->AddrLen;
Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;
//
// Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.
//
Configuration++;
- Desc = Configuration->Desc;
+ Desc = Configuration->Desc;
Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;
//
@@ -259,7 +261,7 @@ PciRootBridgeEnumerator ( //
// Restore changed fields
//
- Configuration->Desc = Desc;
+ Configuration->Desc = Desc;
(Configuration - 1)->AddrLen = AddrLen;
return Status;
@@ -276,13 +278,13 @@ PciRootBridgeEnumerator ( **/
VOID
ProcessOptionRom (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT64 RomBase,
- IN UINT64 MaxLength
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT64 RomBase,
+ IN UINT64 MaxLength
)
{
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
//
// Go through bridges to reach all devices
@@ -291,15 +293,13 @@ ProcessOptionRom ( while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) {
-
//
// Go further to process the option rom under this bridge
//
ProcessOptionRom (Temp, RomBase, MaxLength);
}
- if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {
-
+ if ((Temp->RomSize != 0) && (Temp->RomSize <= MaxLength)) {
//
// Load and process the option rom
//
@@ -323,25 +323,25 @@ ProcessOptionRom ( **/
EFI_STATUS
PciAssignBusNumber (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber,
- OUT UINT8 *SubBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber,
+ OUT UINT8 *SubBusNumber
)
{
- EFI_STATUS Status;
- PCI_TYPE00 Pci;
- UINT8 Device;
- UINT8 Func;
- UINT64 Address;
- UINTN SecondBus;
- UINT16 Register;
- UINT8 Register8;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_STATUS Status;
+ PCI_TYPE00 Pci;
+ UINT8 Device;
+ UINT8 Func;
+ UINT64 Address;
+ UINTN SecondBus;
+ UINT16 Register;
+ UINT8 Register8;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
PciRootBridgeIo = Bridge->PciRootBridgeIo;
- SecondBus = 0;
- Register = 0;
+ SecondBus = 0;
+ Register = 0;
*SubBusNumber = StartBusNumber;
@@ -350,19 +350,18 @@ PciAssignBusNumber ( //
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
-
//
// Check to see whether a pci device is present
//
Status = PciDevicePresent (
- PciRootBridgeIo,
- &Pci,
- StartBusNumber,
- Device,
- Func
- );
-
- if (EFI_ERROR (Status) && Func == 0) {
+ PciRootBridgeIo,
+ &Pci,
+ StartBusNumber,
+ Device,
+ Func
+ );
+
+ if (EFI_ERROR (Status) && (Func == 0)) {
//
// go to next device if there is no Function 0
//
@@ -370,8 +369,8 @@ PciAssignBusNumber ( }
if (!EFI_ERROR (Status) &&
- (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
-
+ (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)))
+ {
//
// Reserved one bus for cardbus bridge
//
@@ -379,11 +378,12 @@ PciAssignBusNumber ( if (EFI_ERROR (Status)) {
return Status;
}
+
SecondBus = *SubBusNumber;
- Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
+ Register = (UINT16)((SecondBus << 8) | (UINT16)StartBusNumber);
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
@@ -397,32 +397,31 @@ PciAssignBusNumber ( // Initialize SubBusNumber to SecondBus
//
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
- Status = PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- EfiPciWidthUint8,
- Address,
- 1,
- SubBusNumber
- );
+ Status = PciRootBridgeIo->Pci.Write (
+ PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ SubBusNumber
+ );
//
// If it is PPB, resursively search down this bridge
//
if (IS_PCI_BRIDGE (&Pci)) {
-
Register8 = 0xFF;
- Status = PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- EfiPciWidthUint8,
- Address,
- 1,
- &Register8
- );
+ Status = PciRootBridgeIo->Pci.Write (
+ PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &Register8
+ );
Status = PciAssignBusNumber (
- Bridge,
- (UINT8) (SecondBus),
- SubBusNumber
- );
+ Bridge,
+ (UINT8)(SecondBus),
+ SubBusNumber
+ );
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
@@ -441,11 +440,9 @@ PciAssignBusNumber ( 1,
SubBusNumber
);
-
}
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
-
+ if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
//
// Skip sub functions, this is not a multi function device
//
@@ -470,16 +467,16 @@ PciAssignBusNumber ( **/
EFI_STATUS
DetermineRootBridgeAttributes (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
- IN PCI_IO_DEVICE *RootBridgeDev
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
+ IN PCI_IO_DEVICE *RootBridgeDev
)
{
UINT64 Attributes;
EFI_STATUS Status;
EFI_HANDLE RootBridgeHandle;
- Attributes = 0;
- RootBridgeHandle = RootBridgeDev->Handle;
+ Attributes = 0;
+ RootBridgeHandle = RootBridgeDev->Handle;
//
// Get root bridge attribute by calling into pci host bridge resource allocation protocol
@@ -524,13 +521,13 @@ DetermineRootBridgeAttributes ( **/
UINT32
GetMaxOptionRomSize (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
)
{
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *Temp;
- UINT32 MaxOptionRomSize;
- UINT32 TempOptionRomSize;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
+ UINT32 MaxOptionRomSize;
+ UINT32 TempOptionRomSize;
MaxOptionRomSize = 0;
@@ -541,7 +538,6 @@ GetMaxOptionRomSize ( while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) {
-
//
// Get max option rom size under this bridge
//
@@ -554,9 +550,7 @@ GetMaxOptionRomSize ( if (Temp->RomSize > TempOptionRomSize) {
TempOptionRomSize = Temp->RomSize;
}
-
} else {
-
//
// For devices get the rom size directly
//
@@ -588,17 +582,16 @@ GetMaxOptionRomSize ( **/
EFI_STATUS
PciHostBridgeDeviceAttribute (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
)
{
- EFI_HANDLE RootBridgeHandle;
- PCI_IO_DEVICE *RootBridgeDev;
- EFI_STATUS Status;
+ EFI_HANDLE RootBridgeHandle;
+ PCI_IO_DEVICE *RootBridgeDev;
+ EFI_STATUS Status;
RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
-
//
// Get RootBridg Device by handle
//
@@ -615,7 +608,6 @@ PciHostBridgeDeviceAttribute ( if (EFI_ERROR (Status)) {
return Status;
}
-
}
return EFI_SUCCESS;
@@ -642,58 +634,57 @@ GetResourceAllocationStatus ( OUT UINT64 *PMem64ResStatus
)
{
- UINT8 *Temp;
- UINT64 ResStatus;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;
+ UINT8 *Temp;
+ UINT64 ResStatus;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;
- Temp = (UINT8 *) AcpiConfig;
+ Temp = (UINT8 *)AcpiConfig;
while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
-
- ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
- ResStatus = ACPIAddressDesc->AddrTranslationOffset;
+ ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp;
+ ResStatus = ACPIAddressDesc->AddrTranslationOffset;
switch (ACPIAddressDesc->ResType) {
- case 0:
- if (ACPIAddressDesc->AddrSpaceGranularity == 32) {
- if (ACPIAddressDesc->SpecificFlag == 0x06) {
- //
- // Pmem32
- //
- *PMem32ResStatus = ResStatus;
- } else {
- //
- // Mem32
- //
- *Mem32ResStatus = ResStatus;
+ case 0:
+ if (ACPIAddressDesc->AddrSpaceGranularity == 32) {
+ if (ACPIAddressDesc->SpecificFlag == 0x06) {
+ //
+ // Pmem32
+ //
+ *PMem32ResStatus = ResStatus;
+ } else {
+ //
+ // Mem32
+ //
+ *Mem32ResStatus = ResStatus;
+ }
}
- }
- if (ACPIAddressDesc->AddrSpaceGranularity == 64) {
- if (ACPIAddressDesc->SpecificFlag == 0x06) {
- //
- // PMem64
- //
- *PMem64ResStatus = ResStatus;
- } else {
- //
- // Mem64
- //
- *Mem64ResStatus = ResStatus;
+ if (ACPIAddressDesc->AddrSpaceGranularity == 64) {
+ if (ACPIAddressDesc->SpecificFlag == 0x06) {
+ //
+ // PMem64
+ //
+ *PMem64ResStatus = ResStatus;
+ } else {
+ //
+ // Mem64
+ //
+ *Mem64ResStatus = ResStatus;
+ }
}
- }
- break;
+ break;
- case 1:
- //
- // Io
- //
- *IoResStatus = ResStatus;
- break;
+ case 1:
+ //
+ // Io
+ //
+ *IoResStatus = ResStatus;
+ break;
- default:
- break;
+ default:
+ break;
}
Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
@@ -711,18 +702,19 @@ GetResourceAllocationStatus ( **/
EFI_STATUS
RejectPciDevice (
- IN PCI_IO_DEVICE *PciDevice
+ IN PCI_IO_DEVICE *PciDevice
)
{
- PCI_IO_DEVICE *Bridge;
- PCI_IO_DEVICE *Temp;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Bridge;
+ PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
//
// Remove the padding resource from a bridge
//
- if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&
- PciDevice->ResourcePaddingDescriptors != NULL ) {
+ if ( IS_PCI_BRIDGE (&PciDevice->Pci) &&
+ (PciDevice->ResourcePaddingDescriptors != NULL))
+ {
FreePool (PciDevice->ResourcePaddingDescriptors);
PciDevice->ResourcePaddingDescriptors = NULL;
return EFI_SUCCESS;
@@ -782,10 +774,10 @@ RejectPciDevice ( **/
BOOLEAN
IsRejectiveDevice (
- IN PCI_RESOURCE_NODE *PciResNode
+ IN PCI_RESOURCE_NODE *PciResNode
)
{
- PCI_IO_DEVICE *Temp;
+ PCI_IO_DEVICE *Temp;
Temp = PciResNode->PciDev;
@@ -831,16 +823,16 @@ IsRejectiveDevice ( **/
PCI_RESOURCE_NODE *
GetLargerConsumerDevice (
- IN PCI_RESOURCE_NODE *PciResNode1,
- IN PCI_RESOURCE_NODE *PciResNode2
+ IN PCI_RESOURCE_NODE *PciResNode1,
+ IN PCI_RESOURCE_NODE *PciResNode2
)
{
if (PciResNode2 == NULL) {
return PciResNode1;
}
- if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \
- && (PciResNode2->ResourceUsage != PciResUsagePadding) )
+ if ( (IS_PCI_BRIDGE (&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \
+ && (PciResNode2->ResourceUsage != PciResUsagePadding))
{
return PciResNode1;
}
@@ -856,7 +848,6 @@ GetLargerConsumerDevice ( return PciResNode2;
}
-
/**
Get the max resource consumer in the host resource pool.
@@ -867,19 +858,18 @@ GetLargerConsumerDevice ( **/
PCI_RESOURCE_NODE *
GetMaxResourceConsumerDevice (
- IN PCI_RESOURCE_NODE *ResPool
+ IN PCI_RESOURCE_NODE *ResPool
)
{
- PCI_RESOURCE_NODE *Temp;
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *PciResNode;
- PCI_RESOURCE_NODE *PPBResNode;
+ PCI_RESOURCE_NODE *Temp;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *PciResNode;
+ PCI_RESOURCE_NODE *PPBResNode;
- PciResNode = NULL;
+ PciResNode = NULL;
CurrentLink = ResPool->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {
-
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (!IsRejectiveDevice (Temp)) {
@@ -887,11 +877,11 @@ GetMaxResourceConsumerDevice ( continue;
}
- if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \
- && (Temp->ResourceUsage != PciResUsagePadding))
+ if ( (IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \
+ && (Temp->ResourceUsage != PciResUsagePadding))
{
- PPBResNode = GetMaxResourceConsumerDevice (Temp);
- PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);
+ PPBResNode = GetMaxResourceConsumerDevice (Temp);
+ PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);
} else {
PciResNode = GetLargerConsumerDevice (PciResNode, Temp);
}
@@ -922,49 +912,48 @@ GetMaxResourceConsumerDevice ( **/
EFI_STATUS
PciHostBridgeAdjustAllocation (
- IN PCI_RESOURCE_NODE *IoPool,
- IN PCI_RESOURCE_NODE *Mem32Pool,
- IN PCI_RESOURCE_NODE *PMem32Pool,
- IN PCI_RESOURCE_NODE *Mem64Pool,
- IN PCI_RESOURCE_NODE *PMem64Pool,
- IN UINT64 IoResStatus,
- IN UINT64 Mem32ResStatus,
- IN UINT64 PMem32ResStatus,
- IN UINT64 Mem64ResStatus,
- IN UINT64 PMem64ResStatus
+ IN PCI_RESOURCE_NODE *IoPool,
+ IN PCI_RESOURCE_NODE *Mem32Pool,
+ IN PCI_RESOURCE_NODE *PMem32Pool,
+ IN PCI_RESOURCE_NODE *Mem64Pool,
+ IN PCI_RESOURCE_NODE *PMem64Pool,
+ IN UINT64 IoResStatus,
+ IN UINT64 Mem32ResStatus,
+ IN UINT64 PMem32ResStatus,
+ IN UINT64 Mem64ResStatus,
+ IN UINT64 PMem64ResStatus
)
{
- BOOLEAN AllocationAjusted;
- PCI_RESOURCE_NODE *PciResNode;
- PCI_RESOURCE_NODE *ResPool[5];
- PCI_IO_DEVICE *RemovedPciDev[5];
- UINT64 ResStatus[5];
- UINTN RemovedPciDevNum;
- UINTN DevIndex;
- UINTN ResType;
- EFI_STATUS Status;
- EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
+ BOOLEAN AllocationAjusted;
+ PCI_RESOURCE_NODE *PciResNode;
+ PCI_RESOURCE_NODE *ResPool[5];
+ PCI_IO_DEVICE *RemovedPciDev[5];
+ UINT64 ResStatus[5];
+ UINTN RemovedPciDevNum;
+ UINTN DevIndex;
+ UINTN ResType;
+ EFI_STATUS Status;
+ EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
PciResNode = NULL;
ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));
- RemovedPciDevNum = 0;
+ RemovedPciDevNum = 0;
- ResPool[0] = IoPool;
- ResPool[1] = Mem32Pool;
- ResPool[2] = PMem32Pool;
- ResPool[3] = Mem64Pool;
- ResPool[4] = PMem64Pool;
+ ResPool[0] = IoPool;
+ ResPool[1] = Mem32Pool;
+ ResPool[2] = PMem32Pool;
+ ResPool[3] = Mem64Pool;
+ ResPool[4] = PMem64Pool;
- ResStatus[0] = IoResStatus;
- ResStatus[1] = Mem32ResStatus;
- ResStatus[2] = PMem32ResStatus;
- ResStatus[3] = Mem64ResStatus;
- ResStatus[4] = PMem64ResStatus;
+ ResStatus[0] = IoResStatus;
+ ResStatus[1] = Mem32ResStatus;
+ ResStatus[2] = PMem32ResStatus;
+ ResStatus[3] = Mem64ResStatus;
+ ResStatus[4] = PMem64ResStatus;
AllocationAjusted = FALSE;
for (ResType = 0; ResType < 5; ResType++) {
-
if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {
continue;
}
@@ -1005,7 +994,9 @@ PciHostBridgeAdjustAllocation ( DEBUG ((
DEBUG_ERROR,
"PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
- PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber
+ PciResNode->PciDev->BusNumber,
+ PciResNode->PciDev->DeviceNumber,
+ PciResNode->PciDev->FunctionNumber
));
//
@@ -1015,16 +1006,16 @@ PciHostBridgeAdjustAllocation ( // Have no way to get ReqRes, AllocRes & Bar here
//
ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
- AllocFailExtendedData.DevicePathSize = (UINT16) sizeof (EFI_DEVICE_PATH_PROTOCOL);
- AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;
+ AllocFailExtendedData.DevicePathSize = (UINT16)sizeof (EFI_DEVICE_PATH_PROTOCOL);
+ AllocFailExtendedData.DevicePath = (UINT8 *)PciResNode->PciDev->DevicePath;
AllocFailExtendedData.Bar = PciResNode->Bar;
REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
- EFI_PROGRESS_CODE,
- EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
- (VOID *) &AllocFailExtendedData,
- sizeof (AllocFailExtendedData)
- );
+ EFI_PROGRESS_CODE,
+ EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
+ (VOID *)&AllocFailExtendedData,
+ sizeof (AllocFailExtendedData)
+ );
//
// Add it to the array and indicate at least a device has been rejected
@@ -1033,6 +1024,7 @@ PciHostBridgeAdjustAllocation ( AllocationAjusted = TRUE;
}
}
+
//
// End for
//
@@ -1071,16 +1063,16 @@ ConstructAcpiResourceRequestor ( OUT VOID **Config
)
{
- UINT8 NumConfig;
- UINT8 Aperture;
- UINT8 *Configuration;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
+ UINT8 NumConfig;
+ UINT8 Aperture;
+ UINT8 *Configuration;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
NumConfig = 0;
Aperture = 0;
- *Config = NULL;
+ *Config = NULL;
//
// if there is io request, add to the io aperture
@@ -1123,7 +1115,6 @@ ConstructAcpiResourceRequestor ( }
if (NumConfig != 0) {
-
//
// If there is at least one type of resource request,
// allocate a acpi resource node
@@ -1133,18 +1124,18 @@ ConstructAcpiResourceRequestor ( return EFI_OUT_OF_RESOURCES;
}
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
//
// Deal with io aperture
//
if ((Aperture & 0x01) != 0) {
- Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
+ Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Ptr->Len = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
//
// Io
//
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
//
// non ISA range
//
@@ -1154,16 +1145,17 @@ ConstructAcpiResourceRequestor ( Ptr++;
}
+
//
// Deal with mem32 aperture
//
if ((Aperture & 0x02) != 0) {
- Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
+ Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Ptr->Len = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
//
// Mem
//
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
//
// Nonprefechable
//
@@ -1172,8 +1164,8 @@ ConstructAcpiResourceRequestor ( // 32 bit
//
Ptr->AddrSpaceGranularity = 32;
- Ptr->AddrLen = Mem32Node->Length;
- Ptr->AddrRangeMax = Mem32Node->Alignment;
+ Ptr->AddrLen = Mem32Node->Length;
+ Ptr->AddrRangeMax = Mem32Node->Alignment;
Ptr++;
}
@@ -1182,12 +1174,12 @@ ConstructAcpiResourceRequestor ( // Deal with Pmem32 aperture
//
if ((Aperture & 0x04) != 0) {
- Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
+ Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Ptr->Len = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
//
// Mem
//
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
//
// prefechable
//
@@ -1196,21 +1188,22 @@ ConstructAcpiResourceRequestor ( // 32 bit
//
Ptr->AddrSpaceGranularity = 32;
- Ptr->AddrLen = PMem32Node->Length;
- Ptr->AddrRangeMax = PMem32Node->Alignment;
+ Ptr->AddrLen = PMem32Node->Length;
+ Ptr->AddrRangeMax = PMem32Node->Alignment;
Ptr++;
}
+
//
// Deal with mem64 aperture
//
if ((Aperture & 0x08) != 0) {
- Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
+ Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Ptr->Len = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
//
// Mem
//
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
//
// nonprefechable
//
@@ -1219,21 +1212,22 @@ ConstructAcpiResourceRequestor ( // 64 bit
//
Ptr->AddrSpaceGranularity = 64;
- Ptr->AddrLen = Mem64Node->Length;
- Ptr->AddrRangeMax = Mem64Node->Alignment;
+ Ptr->AddrLen = Mem64Node->Length;
+ Ptr->AddrRangeMax = Mem64Node->Alignment;
Ptr++;
}
+
//
// Deal with Pmem64 aperture
//
if ((Aperture & 0x10) != 0) {
- Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
+ Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Ptr->Len = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
//
// Mem
//
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
//
// prefechable
//
@@ -1242,8 +1236,8 @@ ConstructAcpiResourceRequestor ( // 64 bit
//
Ptr->AddrSpaceGranularity = 64;
- Ptr->AddrLen = PMem64Node->Length;
- Ptr->AddrRangeMax = PMem64Node->Alignment;
+ Ptr->AddrLen = PMem64Node->Length;
+ Ptr->AddrRangeMax = PMem64Node->Alignment;
Ptr++;
}
@@ -1251,13 +1245,11 @@ ConstructAcpiResourceRequestor ( //
// put the checksum
//
- PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;
-
- PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
- PtrEnd->Checksum = 0;
+ PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr;
+ PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
+ PtrEnd->Checksum = 0;
} else {
-
//
// If there is no resource request
//
@@ -1266,9 +1258,9 @@ ConstructAcpiResourceRequestor ( return EFI_OUT_OF_RESOURCES;
}
- PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Configuration);
- PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
- PtrEnd->Checksum = 0;
+ PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Configuration);
+ PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
+ PtrEnd->Checksum = 0;
}
*Config = Configuration;
@@ -1297,9 +1289,9 @@ GetResourceBase ( OUT UINT64 *PMem64Base
)
{
- UINT8 *Temp;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- UINT64 ResStatus;
+ UINT8 *Temp;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ UINT64 ResStatus;
ASSERT (Config != NULL);
@@ -1309,58 +1301,57 @@ GetResourceBase ( *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;
*PMem64Base = 0xFFFFFFFFFFFFFFFFULL;
- Temp = (UINT8 *) Config;
+ Temp = (UINT8 *)Config;
while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
-
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp;
ResStatus = Ptr->AddrTranslationOffset;
if (ResStatus == EFI_RESOURCE_SATISFIED) {
-
switch (Ptr->ResType) {
-
- //
- // Memory type aperture
- //
- case 0:
-
//
- // Check to see the granularity
+ // Memory type aperture
//
- if (Ptr->AddrSpaceGranularity == 32) {
- if ((Ptr->SpecificFlag & 0x06) != 0) {
- *PMem32Base = Ptr->AddrRangeMin;
- } else {
- *Mem32Base = Ptr->AddrRangeMin;
+ case 0:
+
+ //
+ // Check to see the granularity
+ //
+ if (Ptr->AddrSpaceGranularity == 32) {
+ if ((Ptr->SpecificFlag & 0x06) != 0) {
+ *PMem32Base = Ptr->AddrRangeMin;
+ } else {
+ *Mem32Base = Ptr->AddrRangeMin;
+ }
}
- }
- if (Ptr->AddrSpaceGranularity == 64) {
- if ((Ptr->SpecificFlag & 0x06) != 0) {
- *PMem64Base = Ptr->AddrRangeMin;
- } else {
- *Mem64Base = Ptr->AddrRangeMin;
+ if (Ptr->AddrSpaceGranularity == 64) {
+ if ((Ptr->SpecificFlag & 0x06) != 0) {
+ *PMem64Base = Ptr->AddrRangeMin;
+ } else {
+ *Mem64Base = Ptr->AddrRangeMin;
+ }
}
- }
- break;
- case 1:
+ break;
- //
- // Io type aperture
- //
- *IoBase = Ptr->AddrRangeMin;
- break;
+ case 1:
- default:
- break;
+ //
+ // Io type aperture
+ //
+ *IoBase = Ptr->AddrRangeMin;
+ break;
+ default:
+ break;
}
+
//
// End switch
//
}
+
//
// End for
//
@@ -1380,28 +1371,28 @@ GetResourceBase ( **/
EFI_STATUS
PciBridgeEnumerator (
- IN PCI_IO_DEVICE *BridgeDev
+ IN PCI_IO_DEVICE *BridgeDev
)
{
- UINT8 SubBusNumber;
- UINT8 StartBusNumber;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
+ UINT8 SubBusNumber;
+ UINT8 StartBusNumber;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
- SubBusNumber = 0;
- StartBusNumber = 0;
- PciIo = &(BridgeDev->PciIo);
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
+ SubBusNumber = 0;
+ StartBusNumber = 0;
+ PciIo = &(BridgeDev->PciIo);
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
if (EFI_ERROR (Status)) {
return Status;
}
Status = PciAssignBusNumber (
- BridgeDev,
- StartBusNumber,
- &SubBusNumber
- );
+ BridgeDev,
+ StartBusNumber,
+ &SubBusNumber
+ );
if (EFI_ERROR (Status)) {
return Status;
@@ -1426,7 +1417,6 @@ PciBridgeEnumerator ( }
return EFI_SUCCESS;
-
}
/**
@@ -1443,17 +1433,17 @@ PciBridgeResourceAllocator ( IN PCI_IO_DEVICE *Bridge
)
{
- PCI_RESOURCE_NODE *IoBridge;
- PCI_RESOURCE_NODE *Mem32Bridge;
- PCI_RESOURCE_NODE *PMem32Bridge;
- PCI_RESOURCE_NODE *Mem64Bridge;
- PCI_RESOURCE_NODE *PMem64Bridge;
- UINT64 IoBase;
- UINT64 Mem32Base;
- UINT64 PMem32Base;
- UINT64 Mem64Base;
- UINT64 PMem64Base;
- EFI_STATUS Status;
+ PCI_RESOURCE_NODE *IoBridge;
+ PCI_RESOURCE_NODE *Mem32Bridge;
+ PCI_RESOURCE_NODE *PMem32Bridge;
+ PCI_RESOURCE_NODE *Mem64Bridge;
+ PCI_RESOURCE_NODE *PMem64Bridge;
+ UINT64 IoBase;
+ UINT64 Mem32Base;
+ UINT64 PMem32Base;
+ UINT64 Mem64Base;
+ UINT64 PMem64Base;
+ EFI_STATUS Status;
IoBridge = CreateResourceNode (
Bridge,
@@ -1596,12 +1586,12 @@ PciBridgeResourceAllocator ( **/
EFI_STATUS
GetResourceBaseFromBridge (
- IN PCI_IO_DEVICE *Bridge,
- OUT UINT64 *IoBase,
- OUT UINT64 *Mem32Base,
- OUT UINT64 *PMem32Base,
- OUT UINT64 *Mem64Base,
- OUT UINT64 *PMem64Base
+ IN PCI_IO_DEVICE *Bridge,
+ OUT UINT64 *IoBase,
+ OUT UINT64 *Mem32Base,
+ OUT UINT64 *PMem32Base,
+ OUT UINT64 *Mem64Base,
+ OUT UINT64 *PMem64Base
)
{
if (!Bridge->Allocated) {
@@ -1615,7 +1605,6 @@ GetResourceBaseFromBridge ( *PMem64Base = gAllOne;
if (IS_PCI_BRIDGE (&Bridge->Pci)) {
-
if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {
*IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;
}
@@ -1633,7 +1622,6 @@ GetResourceBaseFromBridge ( } else {
*PMem64Base = gAllOne;
}
-
}
if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {
@@ -1735,17 +1723,17 @@ GetResourceBaseFromBridge ( **/
EFI_STATUS
NotifyPhase (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
)
{
- EFI_HANDLE HostBridgeHandle;
- EFI_HANDLE RootBridgeHandle;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- EFI_STATUS Status;
+ EFI_HANDLE HostBridgeHandle;
+ EFI_HANDLE RootBridgeHandle;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_STATUS Status;
- HostBridgeHandle = NULL;
- RootBridgeHandle = NULL;
+ HostBridgeHandle = NULL;
+ RootBridgeHandle = NULL;
if (gPciPlatformProtocol != NULL) {
//
// Get Host Bridge Handle.
@@ -1758,7 +1746,7 @@ NotifyPhase ( Status = gBS->HandleProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo
+ (VOID **)&PciRootBridgeIo
);
if (EFI_ERROR (Status)) {
@@ -1776,7 +1764,7 @@ NotifyPhase ( Phase,
ChipsetEntry
);
- } else if (gPciOverrideProtocol != NULL){
+ } else if (gPciOverrideProtocol != NULL) {
//
// Get Host Bridge Handle.
//
@@ -1788,7 +1776,7 @@ NotifyPhase ( Status = gBS->HandleProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo
+ (VOID **)&PciRootBridgeIo
);
if (EFI_ERROR (Status)) {
@@ -1823,7 +1811,6 @@ NotifyPhase ( Phase,
ChipsetExit
);
-
} else if (gPciOverrideProtocol != NULL) {
//
// Call PlatformPci::PhaseNotify() if the protocol is present.
@@ -1865,11 +1852,11 @@ NotifyPhase ( **/
EFI_STATUS
PreprocessController (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
)
{
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;
@@ -1889,7 +1876,7 @@ PreprocessController ( Status = gBS->OpenProtocol (
HostBridgeHandle,
&gEfiPciHostBridgeResourceAllocationProtocolGuid,
- (VOID **) &PciResAlloc,
+ (VOID **)&PciResAlloc,
NULL,
NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1906,7 +1893,7 @@ PreprocessController ( Bridge = Bridge->Parent;
}
- RootBridgeHandle = Bridge->Handle;
+ RootBridgeHandle = Bridge->Handle;
RootBridgePciAddress.Register = 0;
RootBridgePciAddress.Function = Func;
@@ -2002,25 +1989,25 @@ PreprocessController ( EFI_STATUS
EFIAPI
PciHotPlugRequestNotify (
- IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,
- IN EFI_PCI_HOTPLUG_OPERATION Operation,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,
- IN OUT UINT8 *NumberOfChildren,
- IN OUT EFI_HANDLE * ChildHandleBuffer
+ IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL *This,
+ IN EFI_PCI_HOTPLUG_OPERATION Operation,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL,
+ IN OUT UINT8 *NumberOfChildren,
+ IN OUT EFI_HANDLE *ChildHandleBuffer
)
{
- PCI_IO_DEVICE *Bridge;
- PCI_IO_DEVICE *Temp;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINTN Index;
- EFI_HANDLE RootBridgeHandle;
- EFI_STATUS Status;
+ PCI_IO_DEVICE *Bridge;
+ PCI_IO_DEVICE *Temp;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN Index;
+ EFI_HANDLE RootBridgeHandle;
+ EFI_STATUS Status;
//
// Check input parameter validity
//
- if ((Controller == NULL) || (NumberOfChildren == NULL)){
+ if ((Controller == NULL) || (NumberOfChildren == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -2028,7 +2015,7 @@ PciHotPlugRequestNotify ( return EFI_INVALID_PARAMETER;
}
- if (Operation == EfiPciHotPlugRequestAdd){
+ if (Operation == EfiPciHotPlugRequestAdd) {
if (ChildHandleBuffer == NULL) {
return EFI_INVALID_PARAMETER;
}
@@ -2041,7 +2028,7 @@ PciHotPlugRequestNotify ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -2078,7 +2065,6 @@ PciHotPlugRequestNotify ( }
if (IsListEmpty (&Bridge->ChildList)) {
-
Status = PciBridgeEnumerator (Bridge);
if (EFI_ERROR (Status)) {
@@ -2087,25 +2073,23 @@ PciHotPlugRequestNotify ( }
Status = StartPciDevicesOnBridge (
- RootBridgeHandle,
- Bridge,
- RemainingDevicePath,
- NumberOfChildren,
- ChildHandleBuffer
- );
+ RootBridgeHandle,
+ Bridge,
+ RemainingDevicePath,
+ NumberOfChildren,
+ ChildHandleBuffer
+ );
return Status;
}
if (Operation == EfiPciHotplugRequestRemove) {
-
if (*NumberOfChildren == 0) {
//
// Remove all devices on the bridge
//
RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);
return EFI_SUCCESS;
-
}
for (Index = 0; Index < *NumberOfChildren; Index++) {
@@ -2117,8 +2101,8 @@ PciHotPlugRequestNotify ( if (EFI_ERROR (Status)) {
return Status;
}
-
}
+
//
// End for
//
@@ -2139,13 +2123,13 @@ PciHotPlugRequestNotify ( **/
BOOLEAN
SearchHostBridgeHandle (
- IN EFI_HANDLE RootBridgeHandle
+ IN EFI_HANDLE RootBridgeHandle
)
{
- EFI_HANDLE HostBridgeHandle;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- UINTN Index;
- EFI_STATUS Status;
+ EFI_HANDLE HostBridgeHandle;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ UINTN Index;
+ EFI_STATUS Status;
//
// Get the rootbridge Io protocol to find the host bridge handle
@@ -2153,7 +2137,7 @@ SearchHostBridgeHandle ( Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -2185,10 +2169,10 @@ SearchHostBridgeHandle ( **/
EFI_STATUS
AddHostBridgeEnumerator (
- IN EFI_HANDLE HostBridgeHandle
+ IN EFI_HANDLE HostBridgeHandle
)
{
- UINTN Index;
+ UINTN Index;
if (HostBridgeHandle == NULL) {
return EFI_ABORTED;
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h index 133454126c..2c81def04c 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h @@ -24,8 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
PciEnumerator (
- IN EFI_HANDLE Controller,
- IN EFI_HANDLE HostBridgeHandle
+ IN EFI_HANDLE Controller,
+ IN EFI_HANDLE HostBridgeHandle
);
/**
@@ -55,9 +55,9 @@ PciRootBridgeEnumerator ( **/
VOID
ProcessOptionRom (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT64 RomBase,
- IN UINT64 MaxLength
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT64 RomBase,
+ IN UINT64 MaxLength
);
/**
@@ -73,9 +73,9 @@ ProcessOptionRom ( **/
EFI_STATUS
PciAssignBusNumber (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber,
- OUT UINT8 *SubBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber,
+ OUT UINT8 *SubBusNumber
);
/**
@@ -91,8 +91,8 @@ PciAssignBusNumber ( **/
EFI_STATUS
DetermineRootBridgeAttributes (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
- IN PCI_IO_DEVICE *RootBridgeDev
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
+ IN PCI_IO_DEVICE *RootBridgeDev
);
/**
@@ -105,7 +105,7 @@ DetermineRootBridgeAttributes ( **/
UINT32
GetMaxOptionRomSize (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
);
/**
@@ -120,7 +120,7 @@ GetMaxOptionRomSize ( **/
EFI_STATUS
PciHostBridgeDeviceAttribute (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -155,7 +155,7 @@ GetResourceAllocationStatus ( **/
EFI_STATUS
RejectPciDevice (
- IN PCI_IO_DEVICE *PciDevice
+ IN PCI_IO_DEVICE *PciDevice
);
/**
@@ -169,7 +169,7 @@ RejectPciDevice ( **/
BOOLEAN
IsRejectiveDevice (
- IN PCI_RESOURCE_NODE *PciResNode
+ IN PCI_RESOURCE_NODE *PciResNode
);
/**
@@ -183,8 +183,8 @@ IsRejectiveDevice ( **/
PCI_RESOURCE_NODE *
GetLargerConsumerDevice (
- IN PCI_RESOURCE_NODE *PciResNode1,
- IN PCI_RESOURCE_NODE *PciResNode2
+ IN PCI_RESOURCE_NODE *PciResNode1,
+ IN PCI_RESOURCE_NODE *PciResNode2
);
/**
@@ -197,7 +197,7 @@ GetLargerConsumerDevice ( **/
PCI_RESOURCE_NODE *
GetMaxResourceConsumerDevice (
- IN PCI_RESOURCE_NODE *ResPool
+ IN PCI_RESOURCE_NODE *ResPool
);
/**
@@ -220,16 +220,16 @@ GetMaxResourceConsumerDevice ( **/
EFI_STATUS
PciHostBridgeAdjustAllocation (
- IN PCI_RESOURCE_NODE *IoPool,
- IN PCI_RESOURCE_NODE *Mem32Pool,
- IN PCI_RESOURCE_NODE *PMem32Pool,
- IN PCI_RESOURCE_NODE *Mem64Pool,
- IN PCI_RESOURCE_NODE *PMem64Pool,
- IN UINT64 IoResStatus,
- IN UINT64 Mem32ResStatus,
- IN UINT64 PMem32ResStatus,
- IN UINT64 Mem64ResStatus,
- IN UINT64 PMem64ResStatus
+ IN PCI_RESOURCE_NODE *IoPool,
+ IN PCI_RESOURCE_NODE *Mem32Pool,
+ IN PCI_RESOURCE_NODE *PMem32Pool,
+ IN PCI_RESOURCE_NODE *Mem64Pool,
+ IN PCI_RESOURCE_NODE *PMem64Pool,
+ IN UINT64 IoResStatus,
+ IN UINT64 Mem32ResStatus,
+ IN UINT64 PMem32ResStatus,
+ IN UINT64 Mem64ResStatus,
+ IN UINT64 PMem64ResStatus
);
/**
@@ -292,7 +292,7 @@ GetResourceBase ( **/
EFI_STATUS
PciBridgeEnumerator (
- IN PCI_IO_DEVICE *BridgeDev
+ IN PCI_IO_DEVICE *BridgeDev
);
/**
@@ -325,12 +325,12 @@ PciBridgeResourceAllocator ( **/
EFI_STATUS
GetResourceBaseFromBridge (
- IN PCI_IO_DEVICE *Bridge,
- OUT UINT64 *IoBase,
- OUT UINT64 *Mem32Base,
- OUT UINT64 *PMem32Base,
- OUT UINT64 *Mem64Base,
- OUT UINT64 *PMem64Base
+ IN PCI_IO_DEVICE *Bridge,
+ OUT UINT64 *IoBase,
+ OUT UINT64 *Mem32Base,
+ OUT UINT64 *PMem32Base,
+ OUT UINT64 *Mem64Base,
+ OUT UINT64 *PMem64Base
);
/**
@@ -343,7 +343,7 @@ GetResourceBaseFromBridge ( **/
EFI_STATUS
PciHostBridgeP2CProcess (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -412,8 +412,8 @@ PciHostBridgeP2CProcess ( **/
EFI_STATUS
NotifyPhase (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -442,11 +442,11 @@ NotifyPhase ( **/
EFI_STATUS
PreprocessController (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -475,12 +475,12 @@ PreprocessController ( EFI_STATUS
EFIAPI
PciHotPlugRequestNotify (
- IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,
- IN EFI_PCI_HOTPLUG_OPERATION Operation,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,
- IN OUT UINT8 *NumberOfChildren,
- IN OUT EFI_HANDLE * ChildHandleBuffer
+ IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL *This,
+ IN EFI_PCI_HOTPLUG_OPERATION Operation,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL,
+ IN OUT UINT8 *NumberOfChildren,
+ IN OUT EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -494,7 +494,7 @@ PciHotPlugRequestNotify ( **/
BOOLEAN
SearchHostBridgeHandle (
- IN EFI_HANDLE RootBridgeHandle
+ IN EFI_HANDLE RootBridgeHandle
);
/**
@@ -509,7 +509,7 @@ SearchHostBridgeHandle ( **/
EFI_STATUS
AddHostBridgeEnumerator (
- IN EFI_HANDLE HostBridgeHandle
+ IN EFI_HANDLE HostBridgeHandle
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 5111bd513a..ed7f2d4ac6 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -9,13 +9,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciBus.h"
-extern CHAR16 *mBarTypeStr[];
-extern EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
+extern CHAR16 *mBarTypeStr[];
+extern EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
-#define OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
-#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
-#define SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
-#define DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
+#define OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
+#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
+#define SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
+#define DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
/**
This routine is used to check whether the pci device is present.
@@ -32,11 +32,11 @@ extern EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityP **/
EFI_STATUS
PciDevicePresent (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
- OUT PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
+ OUT PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
UINT64 Address;
@@ -58,7 +58,7 @@ PciDevicePresent ( Pci
);
- if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {
+ if (!EFI_ERROR (Status) && ((Pci->Hdr).VendorId != 0xffff)) {
//
// Read the entire config header for the device
//
@@ -91,37 +91,35 @@ PciDevicePresent ( **/
EFI_STATUS
PciPciDeviceInfoCollector (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber
)
{
- EFI_STATUS Status;
- PCI_TYPE00 Pci;
- UINT8 Device;
- UINT8 Func;
- UINT8 SecBus;
- PCI_IO_DEVICE *PciIoDevice;
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ PCI_TYPE00 Pci;
+ UINT8 Device;
+ UINT8 Func;
+ UINT8 SecBus;
+ PCI_IO_DEVICE *PciIoDevice;
+ EFI_PCI_IO_PROTOCOL *PciIo;
- Status = EFI_SUCCESS;
- SecBus = 0;
+ Status = EFI_SUCCESS;
+ SecBus = 0;
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
-
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
-
//
// Check to see whether PCI device is present
//
Status = PciDevicePresent (
Bridge->PciRootBridgeIo,
&Pci,
- (UINT8) StartBusNumber,
- (UINT8) Device,
- (UINT8) Func
+ (UINT8)StartBusNumber,
+ (UINT8)Device,
+ (UINT8)Func
);
- if (EFI_ERROR (Status) && Func == 0) {
+ if (EFI_ERROR (Status) && (Func == 0)) {
//
// go to next device if there is no Function 0
//
@@ -129,11 +127,10 @@ PciPciDeviceInfoCollector ( }
if (!EFI_ERROR (Status)) {
-
//
// Call back to host bridge function
//
- PreprocessController (Bridge, (UINT8) StartBusNumber, Device, Func, EfiPciBeforeResourceCollection);
+ PreprocessController (Bridge, (UINT8)StartBusNumber, Device, Func, EfiPciBeforeResourceCollection);
//
// Collect all the information about the PCI device discovered
@@ -141,7 +138,7 @@ PciPciDeviceInfoCollector ( Status = PciSearchDevice (
Bridge,
&Pci,
- (UINT8) StartBusNumber,
+ (UINT8)StartBusNumber,
Device,
Func,
&PciIoDevice
@@ -152,13 +149,12 @@ PciPciDeviceInfoCollector ( //
//
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
-
//
// If it is PPB, we need to get the secondary bus to continue the enumeration
//
- PciIo = &(PciIoDevice->PciIo);
+ PciIo = &(PciIoDevice->PciIo);
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);
if (EFI_ERROR (Status)) {
return Status;
@@ -182,20 +178,17 @@ PciPciDeviceInfoCollector ( //
Status = PciPciDeviceInfoCollector (
PciIoDevice,
- (UINT8) (SecBus)
+ (UINT8)(SecBus)
);
-
}
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
-
+ if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
//
// Skip sub functions, this is not a multi function device
//
Func = PCI_MAX_FUNC;
}
}
-
}
}
@@ -218,15 +211,15 @@ PciPciDeviceInfoCollector ( **/
EFI_STATUS
PciSearchDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func,
- OUT PCI_IO_DEVICE **PciDevice
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func,
+ OUT PCI_IO_DEVICE **PciDevice
)
{
- PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = NULL;
@@ -235,12 +228,13 @@ PciSearchDevice ( "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
IS_PCI_BRIDGE (Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :
- L"PCI",
- Bus, Device, Func
+ L"PCI",
+ Bus,
+ Device,
+ Func
));
if (!IS_PCI_BRIDGE (Pci)) {
-
if (IS_CARDBUS_BRIDGE (Pci)) {
PciIoDevice = GatherP2CInfo (
Bridge,
@@ -253,7 +247,6 @@ PciSearchDevice ( InitializeP2C (PciIoDevice);
}
} else {
-
//
// Create private data for Pci Device
//
@@ -264,11 +257,8 @@ PciSearchDevice ( Device,
Func
);
-
}
-
} else {
-
//
// Create private data for PPB
//
@@ -305,15 +295,11 @@ PciSearchDevice ( // Detect this function has option rom
//
if (gFullEnumeration) {
-
if (!IS_CARDBUS_BRIDGE (Pci)) {
-
GetOpRomInfo (PciIoDevice);
-
}
ResetPowerManagementFeature (PciIoDevice);
-
}
//
@@ -341,28 +327,26 @@ PciSearchDevice ( **/
VOID
DumpPpbPaddingResource (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN PCI_BAR_TYPE ResourceType
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN PCI_BAR_TYPE ResourceType
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- PCI_BAR_TYPE Type;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ PCI_BAR_TYPE Type;
if (PciIoDevice->ResourcePaddingDescriptors == NULL) {
return;
}
- if (ResourceType == PciBarTypeIo16 || ResourceType == PciBarTypeIo32) {
+ if ((ResourceType == PciBarTypeIo16) || (ResourceType == PciBarTypeIo32)) {
ResourceType = PciBarTypeIo;
}
for (Descriptor = PciIoDevice->ResourcePaddingDescriptors; Descriptor->Desc != ACPI_END_TAG_DESCRIPTOR; Descriptor++) {
-
Type = PciBarTypeUnknown;
- if (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) {
+ if ((Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_IO)) {
Type = PciBarTypeIo;
- } else if (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
-
+ } else if ((Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM)) {
if (Descriptor->AddrSpaceGranularity == 32) {
//
// prefetchable
@@ -400,11 +384,12 @@ DumpPpbPaddingResource ( DEBUG ((
DEBUG_INFO,
" Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
- mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLen
+ mBarTypeStr[Type],
+ Descriptor->AddrRangeMax,
+ Descriptor->AddrLen
));
}
}
-
}
/**
@@ -414,10 +399,10 @@ DumpPpbPaddingResource ( **/
VOID
DumpPciBars (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
if (PciIoDevice->PciBar[Index].BarType == PciBarTypeUnknown) {
@@ -427,8 +412,11 @@ DumpPciBars ( DEBUG ((
DEBUG_INFO,
" BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
- Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
- PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset
+ Index,
+ mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
+ PciIoDevice->PciBar[Index].Alignment,
+ PciIoDevice->PciBar[Index].Length,
+ PciIoDevice->PciBar[Index].Offset
));
}
@@ -440,10 +428,14 @@ DumpPciBars ( DEBUG ((
DEBUG_INFO,
" VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
- Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
- PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
+ Index,
+ mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
+ PciIoDevice->VfPciBar[Index].Alignment,
+ PciIoDevice->VfPciBar[Index].Length,
+ PciIoDevice->VfPciBar[Index].Offset
));
}
+
DEBUG ((DEBUG_INFO, "\n"));
}
@@ -461,16 +453,16 @@ DumpPciBars ( **/
PCI_IO_DEVICE *
GatherDeviceInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
- UINTN Offset;
- UINTN BarIndex;
- PCI_IO_DEVICE *PciIoDevice;
+ UINTN Offset;
+ UINTN BarIndex;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = CreatePciIoDevice (
Bridge,
@@ -488,9 +480,7 @@ GatherDeviceInfo ( // If it is a full enumeration, disconnect the device in advance
//
if (gFullEnumeration) {
-
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
-
}
//
@@ -503,17 +493,19 @@ GatherDeviceInfo ( //
// Parse the SR-IOV VF bars
//
- if (PcdGetBool (PcdSrIovSupport) && PciIoDevice->SrIovCapabilityOffset != 0) {
+ if (PcdGetBool (PcdSrIovSupport) && (PciIoDevice->SrIovCapabilityOffset != 0)) {
for (Offset = PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0, BarIndex = 0;
Offset <= PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5;
- BarIndex++) {
-
+ BarIndex++)
+ {
ASSERT (BarIndex < PCI_MAX_BAR);
Offset = PciIovParseVfBar (PciIoDevice, Offset, BarIndex);
}
}
- DEBUG_CODE (DumpPciBars (PciIoDevice););
+ DEBUG_CODE (
+ DumpPciBars (PciIoDevice);
+ );
return PciIoDevice;
}
@@ -531,21 +523,21 @@ GatherDeviceInfo ( **/
PCI_IO_DEVICE *
GatherPpbInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
- PCI_IO_DEVICE *PciIoDevice;
- EFI_STATUS Status;
- UINT8 Value;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT8 Temp;
- UINT32 PMemBaseLimit;
- UINT16 PrefetchableMemoryBase;
- UINT16 PrefetchableMemoryLimit;
+ PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ UINT8 Value;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 Temp;
+ UINT32 PMemBaseLimit;
+ UINT16 PrefetchableMemoryBase;
+ UINT16 PrefetchableMemoryLimit;
PciIoDevice = CreatePciIoDevice (
Bridge,
@@ -566,7 +558,6 @@ GatherPpbInfo ( // Initialize the bridge control register
//
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);
-
}
//
@@ -628,11 +619,11 @@ GatherPpbInfo ( }
Status = BarExisted (
- PciIoDevice,
- 0x24,
- NULL,
- &PMemBaseLimit
- );
+ PciIoDevice,
+ 0x24,
+ NULL,
+ &PMemBaseLimit
+ );
//
// Test if it supports 64 memory or not
@@ -642,17 +633,18 @@ GatherPpbInfo ( // 0 - the bridge supports only 32 bit addresses.
// 1 - the bridge supports 64-bit addresses.
//
- PrefetchableMemoryBase = (UINT16)(PMemBaseLimit & 0xffff);
+ PrefetchableMemoryBase = (UINT16)(PMemBaseLimit & 0xffff);
PrefetchableMemoryLimit = (UINT16)(PMemBaseLimit >> 16);
if (!EFI_ERROR (Status) &&
- (PrefetchableMemoryBase & 0x000f) == 0x0001 &&
- (PrefetchableMemoryLimit & 0x000f) == 0x0001) {
+ ((PrefetchableMemoryBase & 0x000f) == 0x0001) &&
+ ((PrefetchableMemoryLimit & 0x000f) == 0x0001))
+ {
Status = BarExisted (
- PciIoDevice,
- 0x28,
- NULL,
- NULL
- );
+ PciIoDevice,
+ 0x28,
+ NULL,
+ NULL
+ );
if (!EFI_ERROR (Status)) {
PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
@@ -672,12 +664,11 @@ GatherPpbInfo ( DEBUG_CODE (
DumpPpbPaddingResource (PciIoDevice, PciBarTypeUnknown);
DumpPciBars (PciIoDevice);
- );
+ );
return PciIoDevice;
}
-
/**
Create PCI device instance for PCI Card bridge device.
@@ -692,14 +683,14 @@ GatherPpbInfo ( **/
PCI_IO_DEVICE *
GatherP2CInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
- PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = CreatePciIoDevice (
Bridge,
@@ -735,7 +726,9 @@ GatherP2CInfo ( EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
EFI_BRIDGE_IO32_DECODE_SUPPORTED;
- DEBUG_CODE (DumpPciBars (PciIoDevice););
+ DEBUG_CODE (
+ DumpPciBars (PciIoDevice);
+ );
return PciIoDevice;
}
@@ -751,18 +744,17 @@ GatherP2CInfo ( **/
EFI_DEVICE_PATH_PROTOCOL *
CreatePciDevicePath (
- IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
- IN PCI_IO_DEVICE *PciIoDevice
+ IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
-
- PCI_DEVICE_PATH PciNode;
+ PCI_DEVICE_PATH PciNode;
//
// Create PCI device path
//
- PciNode.Header.Type = HARDWARE_DEVICE_PATH;
- PciNode.Header.SubType = HW_PCI_DP;
+ PciNode.Header.Type = HARDWARE_DEVICE_PATH;
+ PciNode.Header.SubType = HW_PCI_DP;
SetDevicePathNodeLength (&PciNode.Header, sizeof (PciNode));
PciNode.Device = PciIoDevice->DeviceNumber;
@@ -786,16 +778,16 @@ CreatePciDevicePath ( **/
EFI_STATUS
VfBarExisted (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINTN Offset,
- OUT UINT32 *BarLengthValue,
- OUT UINT32 *OriginalBarValue
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Offset,
+ OUT UINT32 *BarLengthValue,
+ OUT UINT32 *OriginalBarValue
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT32 OriginalValue;
- UINT32 Value;
- EFI_TPL OldTpl;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 OriginalValue;
+ UINT32 Value;
+ EFI_TPL OldTpl;
//
// Ensure it is called properly
@@ -860,36 +852,36 @@ VfBarExisted ( **/
EFI_STATUS
BarExisted (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINTN Offset,
- OUT UINT32 *BarLengthValue,
- OUT UINT32 *OriginalBarValue
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Offset,
+ OUT UINT32 *BarLengthValue,
+ OUT UINT32 *OriginalBarValue
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT32 OriginalValue;
- UINT32 Value;
- EFI_TPL OldTpl;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 OriginalValue;
+ UINT32 Value;
+ EFI_TPL OldTpl;
PciIo = &PciIoDevice->PciIo;
//
// Preserve the original value
//
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &OriginalValue);
//
// Raise TPL to high level to disable timer interrupt while the BAR is probed
//
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &gAllOne);
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &Value);
//
// Write back the original value
//
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &OriginalValue);
//
// Restore TPL to its original level
@@ -925,15 +917,15 @@ BarExisted ( **/
VOID
PciTestSupportedAttribute (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN OUT UINT16 *Command,
- IN OUT UINT16 *BridgeControl,
- OUT UINT16 *OldCommand,
- OUT UINT16 *OldBridgeControl
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN OUT UINT16 *Command,
+ IN OUT UINT16 *BridgeControl,
+ OUT UINT16 *OldCommand,
+ OUT UINT16 *OldBridgeControl
)
{
- EFI_TPL OldTpl;
- UINT16 CommandValue;
+ EFI_TPL OldTpl;
+ UINT16 CommandValue;
//
// Preserve the original value
@@ -943,7 +935,7 @@ PciTestSupportedAttribute ( //
// Raise TPL to high level to disable timer interrupt while the BAR is probed
//
- OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
CommandValue = *Command | *OldCommand;
PCI_SET_COMMAND_REGISTER (PciIoDevice, CommandValue);
@@ -961,7 +953,6 @@ PciTestSupportedAttribute ( gBS->RestoreTPL (OldTpl);
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
-
//
// Preserve the original value
//
@@ -984,7 +975,6 @@ PciTestSupportedAttribute ( // Restore TPL to its original level
//
gBS->RestoreTPL (OldTpl);
-
} else {
*OldBridgeControl = 0;
*BridgeControl = 0;
@@ -1002,10 +992,10 @@ PciTestSupportedAttribute ( **/
VOID
PciSetDeviceAttribute (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT16 Command,
- IN UINT16 BridgeControl,
- IN UINTN Option
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 Command,
+ IN UINT16 BridgeControl,
+ IN UINTN Option
)
{
UINT64 Attributes;
@@ -1044,18 +1034,17 @@ PciSetDeviceAttribute ( }
if (Option == EFI_SET_SUPPORTS) {
-
- Attributes |= (UINT64) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
- EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |
- EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |
- EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
- EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
+ Attributes |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
+ EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |
+ EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
if (IS_PCI_LPC (&PciIoDevice->Pci)) {
- Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
- Attributes |= (mReserveIsaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO : \
- (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);
+ Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
+ Attributes |= (mReserveIsaAliases ? (UINT64)EFI_PCI_IO_ATTRIBUTE_ISA_IO : \
+ (UINT64)EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);
}
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
@@ -1073,7 +1062,6 @@ PciSetDeviceAttribute ( EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);
}
} else {
-
if (IS_PCI_IDE (&PciIoDevice->Pci)) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO;
Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO;
@@ -1081,16 +1069,15 @@ PciSetDeviceAttribute ( if (IS_PCI_VGA (&PciIoDevice->Pci)) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;
- Attributes |= (mReserveVgaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO : \
- (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);
+ Attributes |= (mReserveVgaAliases ? (UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_IO : \
+ (UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);
}
}
- PciIoDevice->Supports = Attributes;
- PciIoDevice->Supports &= ( (PciIoDevice->Parent->Supports) | \
- EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | \
- EFI_PCI_IO_ATTRIBUTE_BUS_MASTER );
-
+ PciIoDevice->Supports = Attributes;
+ PciIoDevice->Supports &= ((PciIoDevice->Parent->Supports) | \
+ EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | \
+ EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);
} else {
//
// When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
@@ -1101,6 +1088,7 @@ PciSetDeviceAttribute ( if (!PciIoDevice->EmbeddedRom) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM;
}
+
PciIoDevice->Attributes = Attributes;
}
}
@@ -1117,19 +1105,19 @@ PciSetDeviceAttribute ( **/
EFI_STATUS
GetFastBackToBackSupport (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT8 StatusIndex
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT8 StatusIndex
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT32 StatusRegister;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT32 StatusRegister;
//
// Read the status register
//
- PciIo = &PciIoDevice->PciIo;
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
+ PciIo = &PciIoDevice->PciIo;
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
@@ -1153,18 +1141,17 @@ GetFastBackToBackSupport ( **/
VOID
ProcessOptionRomLight (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- PCI_IO_DEVICE *Temp;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
//
// For RootBridge, PPB , P2C, go recursively to traverse all its children
//
CurrentLink = PciIoDevice->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {
-
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) {
@@ -1185,17 +1172,17 @@ ProcessOptionRomLight ( **/
EFI_STATUS
DetermineDeviceAttribute (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- UINT16 Command;
- UINT16 BridgeControl;
- UINT16 OldCommand;
- UINT16 OldBridgeControl;
- BOOLEAN FastB2BSupport;
- PCI_IO_DEVICE *Temp;
- LIST_ENTRY *CurrentLink;
- EFI_STATUS Status;
+ UINT16 Command;
+ UINT16 BridgeControl;
+ UINT16 OldCommand;
+ UINT16 OldBridgeControl;
+ BOOLEAN FastB2BSupport;
+ PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
+ EFI_STATUS Status;
//
// For Root Bridge, just copy it by RootBridgeIo protocol
@@ -1203,22 +1190,21 @@ DetermineDeviceAttribute ( //
if (PciIoDevice->Parent == NULL) {
Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
- PciIoDevice->PciRootBridgeIo,
- &PciIoDevice->Supports,
- &PciIoDevice->Attributes
- );
+ PciIoDevice->PciRootBridgeIo,
+ &PciIoDevice->Supports,
+ &PciIoDevice->Attributes
+ );
if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Assume the PCI Root Bridge supports DAC
//
PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
- EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
-
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
} else {
-
//
// Set the attributes to be checked for common PCI devices and PPB or P2C
// Since some devices only support part of them, it is better to set the
@@ -1268,12 +1254,12 @@ DetermineDeviceAttribute ( //
CurrentLink = PciIoDevice->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {
-
- Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
- Status = DetermineDeviceAttribute (Temp);
+ Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
+ Status = DetermineDeviceAttribute (Temp);
if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Detect Fast Back to Back support for the device under the bridge
//
@@ -1284,13 +1270,12 @@ DetermineDeviceAttribute ( CurrentLink = CurrentLink->ForwardLink;
}
+
//
// Set or clear Fast Back to Back bit for the whole bridge
//
if (!IsListEmpty (&PciIoDevice->ChildList)) {
-
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
-
Status = GetFastBackToBackSupport (PciIoDevice, PCI_BRIDGE_STATUS_REGISTER_OFFSET);
if (EFI_ERROR (Status) || (!FastB2BSupport)) {
@@ -1313,6 +1298,7 @@ DetermineDeviceAttribute ( CurrentLink = CurrentLink->ForwardLink;
}
}
+
//
// End for IsListEmpty
//
@@ -1331,14 +1317,14 @@ DetermineDeviceAttribute ( **/
EFI_STATUS
UpdatePciInfo (
- IN OUT PCI_IO_DEVICE *PciIoDevice
+ IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_STATUS Status;
- UINTN BarIndex;
- BOOLEAN SetFlag;
- VOID *Configuration;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ EFI_STATUS Status;
+ UINTN BarIndex;
+ BOOLEAN SetFlag;
+ VOID *Configuration;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
Configuration = NULL;
Status = EFI_SUCCESS;
@@ -1351,37 +1337,36 @@ UpdatePciInfo ( Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
- (VOID **) &gIncompatiblePciDeviceSupport
+ (VOID **)&gIncompatiblePciDeviceSupport
);
}
- if (Status == EFI_SUCCESS) {
- //
- // Check whether the device belongs to incompatible devices from protocol or not
- // If it is , then get its special requirement in the ACPI table
- //
- Status = gIncompatiblePciDeviceSupport->CheckDevice (
- gIncompatiblePciDeviceSupport,
- PciIoDevice->Pci.Hdr.VendorId,
- PciIoDevice->Pci.Hdr.DeviceId,
- PciIoDevice->Pci.Hdr.RevisionID,
- PciIoDevice->Pci.Device.SubsystemVendorID,
- PciIoDevice->Pci.Device.SubsystemID,
- &Configuration
- );
+ if (Status == EFI_SUCCESS) {
+ //
+ // Check whether the device belongs to incompatible devices from protocol or not
+ // If it is , then get its special requirement in the ACPI table
+ //
+ Status = gIncompatiblePciDeviceSupport->CheckDevice (
+ gIncompatiblePciDeviceSupport,
+ PciIoDevice->Pci.Hdr.VendorId,
+ PciIoDevice->Pci.Hdr.DeviceId,
+ PciIoDevice->Pci.Hdr.RevisionID,
+ PciIoDevice->Pci.Device.SubsystemVendorID,
+ PciIoDevice->Pci.Device.SubsystemID,
+ &Configuration
+ );
}
- if (EFI_ERROR (Status) || Configuration == NULL ) {
+ if (EFI_ERROR (Status) || (Configuration == NULL)) {
return EFI_UNSUPPORTED;
}
//
// Update PCI device information from the ACPI table
//
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
while (Ptr->Desc != ACPI_END_TAG_DESCRIPTOR) {
-
if (Ptr->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
//
// The format is not support
@@ -1393,7 +1378,8 @@ UpdatePciInfo ( if ((Ptr->AddrTranslationOffset != MAX_UINT64) &&
(Ptr->AddrTranslationOffset != MAX_UINT8) &&
(Ptr->AddrTranslationOffset != BarIndex)
- ) {
+ )
+ {
//
// Skip updating when AddrTranslationOffset is not MAX_UINT64 or MAX_UINT8 (wide match).
// Skip updating when current BarIndex doesn't equal to AddrTranslationOffset.
@@ -1404,61 +1390,62 @@ UpdatePciInfo ( SetFlag = FALSE;
switch (Ptr->ResType) {
- case ACPI_ADDRESS_SPACE_TYPE_MEM:
-
- //
- // Make sure the bar is memory type
- //
- if (CheckBarType (PciIoDevice, (UINT8) BarIndex, PciBarTypeMem)) {
- SetFlag = TRUE;
+ case ACPI_ADDRESS_SPACE_TYPE_MEM:
//
- // Ignored if granularity is 0.
- // Ignored if PCI BAR is I/O or 32-bit memory.
- // If PCI BAR is 64-bit memory and granularity is 32, then
- // the PCI BAR resource is allocated below 4GB.
- // If PCI BAR is 64-bit memory and granularity is 64, then
- // the PCI BAR resource is allocated above 4GB.
+ // Make sure the bar is memory type
//
- if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeMem64) {
- switch (Ptr->AddrSpaceGranularity) {
- case 32:
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
- case 64:
- PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
- break;
- default:
- break;
+ if (CheckBarType (PciIoDevice, (UINT8)BarIndex, PciBarTypeMem)) {
+ SetFlag = TRUE;
+
+ //
+ // Ignored if granularity is 0.
+ // Ignored if PCI BAR is I/O or 32-bit memory.
+ // If PCI BAR is 64-bit memory and granularity is 32, then
+ // the PCI BAR resource is allocated below 4GB.
+ // If PCI BAR is 64-bit memory and granularity is 64, then
+ // the PCI BAR resource is allocated above 4GB.
+ //
+ if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeMem64) {
+ switch (Ptr->AddrSpaceGranularity) {
+ case 32:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
+ case 64:
+ PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
+ break;
+ default:
+ break;
+ }
}
- }
- if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypePMem64) {
- switch (Ptr->AddrSpaceGranularity) {
- case 32:
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
- case 64:
- PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
- break;
- default:
- break;
+ if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypePMem64) {
+ switch (Ptr->AddrSpaceGranularity) {
+ case 32:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
+ case 64:
+ PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
+ break;
+ default:
+ break;
+ }
}
}
- }
- break;
- case ACPI_ADDRESS_SPACE_TYPE_IO:
+ break;
- //
- // Make sure the bar is IO type
- //
- if (CheckBarType (PciIoDevice, (UINT8) BarIndex, PciBarTypeIo)) {
- SetFlag = TRUE;
- }
- break;
+ case ACPI_ADDRESS_SPACE_TYPE_IO:
+
+ //
+ // Make sure the bar is IO type
+ //
+ if (CheckBarType (PciIoDevice, (UINT8)BarIndex, PciBarTypeIo)) {
+ SetFlag = TRUE;
+ }
+
+ break;
}
if (SetFlag) {
-
//
// Update the new alignment for the device
//
@@ -1492,8 +1479,8 @@ UpdatePciInfo ( **/
VOID
SetNewAlign (
- IN OUT UINT64 *Alignment,
- IN UINT64 NewAlignment
+ IN OUT UINT64 *Alignment,
+ IN UINT64 NewAlignment
)
{
UINT64 OldAlignment;
@@ -1504,27 +1491,29 @@ SetNewAlign ( // so skip it
//
if ((NewAlignment == 0) || (NewAlignment == OLD_ALIGN)) {
- return ;
+ return;
}
+
//
// Check the validity of the parameter
//
- if (NewAlignment != EVEN_ALIGN &&
- NewAlignment != SQUAD_ALIGN &&
- NewAlignment != DQUAD_ALIGN ) {
+ if ((NewAlignment != EVEN_ALIGN) &&
+ (NewAlignment != SQUAD_ALIGN) &&
+ (NewAlignment != DQUAD_ALIGN))
+ {
*Alignment = NewAlignment;
- return ;
+ return;
}
- OldAlignment = (*Alignment) + 1;
- ShiftBit = 0;
+ OldAlignment = (*Alignment) + 1;
+ ShiftBit = 0;
//
// Get the first non-zero hex value of the length
//
while ((OldAlignment & 0x0F) == 0x00) {
OldAlignment = RShiftU64 (OldAlignment, 4);
- ShiftBit += 4;
+ ShiftBit += 4;
}
//
@@ -1547,10 +1536,10 @@ SetNewAlign ( //
// Update the old value
//
- NewAlignment = LShiftU64 (OldAlignment, ShiftBit) - 1;
- *Alignment = NewAlignment;
+ NewAlignment = LShiftU64 (OldAlignment, ShiftBit) - 1;
+ *Alignment = NewAlignment;
- return ;
+ return;
}
/**
@@ -1587,11 +1576,11 @@ PciIovParseVfBar ( Value = 0;
Status = VfBarExisted (
- PciIoDevice,
- Offset,
- &Value,
- &OriginalValue
- );
+ PciIoDevice,
+ Offset,
+ &Value,
+ &OriginalValue
+ );
if (EFI_ERROR (Status)) {
PciIoDevice->VfPciBar[BarIndex].BaseAddress = 0;
@@ -1601,133 +1590,130 @@ PciIovParseVfBar ( //
// Scan all the BARs anyway
//
- PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;
+ PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16)Offset;
return Offset + 4;
}
- PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;
+ PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16)Offset;
if ((Value & 0x01) != 0) {
//
// Device I/Os. Impossible
//
ASSERT (FALSE);
return Offset + 4;
-
} else {
-
- Mask = 0xfffffff0;
+ Mask = 0xfffffff0;
PciIoDevice->VfPciBar[BarIndex].BaseAddress = OriginalValue & Mask;
switch (Value & 0x07) {
+ //
+ // memory space; anywhere in 32 bit address space
+ //
+ case 0x00:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem32;
+ } else {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem32;
+ }
- //
- //memory space; anywhere in 32 bit address space
- //
- case 0x00:
- if ((Value & 0x08) != 0) {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem32;
- } else {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem32;
- }
+ PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+
+ //
+ // Adjust Length
+ //
+ PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
+ //
+ // Adjust Alignment
+ //
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+ break;
//
- // Adjust Length
- //
- PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
+ // memory space; anywhere in 64 bit address space
//
- // Adjust Alignment
- //
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
+ case 0x04:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem64;
+ } else {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem64;
+ }
- break;
+ //
+ // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
+ // is regarded as an extension for the first bar. As a result
+ // the sizing will be conducted on combined 64 bit value
+ // Here just store the masked first 32bit value for future size
+ // calculation
+ //
+ PciIoDevice->VfPciBar[BarIndex].Length = Value & Mask;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
- //
- // memory space; anywhere in 64 bit address space
- //
- case 0x04:
- if ((Value & 0x08) != 0) {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem64;
- } else {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem64;
- }
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- //
- // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
- // is regarded as an extension for the first bar. As a result
- // the sizing will be conducted on combined 64 bit value
- // Here just store the masked first 32bit value for future size
- // calculation
- //
- PciIoDevice->VfPciBar[BarIndex].Length = Value & Mask;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+ //
+ // Increment the offset to point to next DWORD
+ //
+ Offset += 4;
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
+ Status = VfBarExisted (
+ PciIoDevice,
+ Offset,
+ &Value,
+ &OriginalValue
+ );
- //
- // Increment the offset to point to next DWORD
- //
- Offset += 4;
+ if (EFI_ERROR (Status)) {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
+ return Offset + 4;
+ }
- Status = VfBarExisted (
- PciIoDevice,
- Offset,
- &Value,
- &OriginalValue
- );
+ //
+ // Fix the length to support some special 64 bit BAR
+ //
+ Value |= ((UINT32)-1 << HighBitSet32 (Value));
- if (EFI_ERROR (Status)) {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
- return Offset + 4;
- }
+ //
+ // Calculate the size of 64bit bar
+ //
+ PciIoDevice->VfPciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64)OriginalValue, 32);
- //
- // Fix the length to support some special 64 bit BAR
- //
- Value |= ((UINT32) -1 << HighBitSet32 (Value));
+ PciIoDevice->VfPciBar[BarIndex].Length = PciIoDevice->VfPciBar[BarIndex].Length | LShiftU64 ((UINT64)Value, 32);
+ PciIoDevice->VfPciBar[BarIndex].Length = (~(PciIoDevice->VfPciBar[BarIndex].Length)) + 1;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
- //
- // Calculate the size of 64bit bar
- //
- PciIoDevice->VfPciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64) OriginalValue, 32);
+ //
+ // Adjust Length
+ //
+ PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
+ //
+ // Adjust Alignment
+ //
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- PciIoDevice->VfPciBar[BarIndex].Length = PciIoDevice->VfPciBar[BarIndex].Length | LShiftU64 ((UINT64) Value, 32);
- PciIoDevice->VfPciBar[BarIndex].Length = (~(PciIoDevice->VfPciBar[BarIndex].Length)) + 1;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+ break;
//
- // Adjust Length
- //
- PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
- //
- // Adjust Alignment
+ // reserved
//
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
-
- break;
+ default:
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
+ PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
- //
- // reserved
- //
- default:
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
- PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
-
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- break;
+ break;
}
}
@@ -1786,12 +1772,12 @@ PciParseBar ( //
// Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
//
- PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
+ PciIoDevice->PciBar[BarIndex].Offset = (UINT8)Offset;
return Offset + 4;
}
PciIoDevice->PciBar[BarIndex].BarTypeFixed = FALSE;
- PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
+ PciIoDevice->PciBar[BarIndex].Offset = (UINT8)Offset;
if ((Value & 0x01) != 0) {
//
// Device I/Os
@@ -1805,7 +1791,6 @@ PciParseBar ( PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo32;
PciIoDevice->PciBar[BarIndex].Length = ((~(Value & Mask)) + 1);
PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
-
} else {
//
// It is a IO16 bar
@@ -1813,135 +1798,134 @@ PciParseBar ( PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo16;
PciIoDevice->PciBar[BarIndex].Length = 0x0000FFFF & ((~(Value & Mask)) + 1);
PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
-
}
+
//
// Workaround. Some platforms implement IO bar with 0 length
// Need to treat it as no-bar
//
if (PciIoDevice->PciBar[BarIndex].Length == 0) {
- PciIoDevice->PciBar[BarIndex].BarType = (PCI_BAR_TYPE) 0;
+ PciIoDevice->PciBar[BarIndex].BarType = (PCI_BAR_TYPE)0;
}
- PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
-
+ PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
} else {
-
- Mask = 0xfffffff0;
+ Mask = 0xfffffff0;
PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
switch (Value & 0x07) {
+ //
+ // memory space; anywhere in 32 bit address space
+ //
+ case 0x00:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
+ } else {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
+ }
- //
- //memory space; anywhere in 32 bit address space
- //
- case 0x00:
- if ((Value & 0x08) != 0) {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
- } else {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
- }
+ PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
+ //
+ // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
+ //
+ PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
+ } else {
+ PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
+ }
+
+ break;
+
+ //
+ // memory space; anywhere in 64 bit address space
+ //
+ case 0x04:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem64;
+ } else {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem64;
+ }
- PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
//
- // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
+ // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
+ // is regarded as an extension for the first bar. As a result
+ // the sizing will be conducted on combined 64 bit value
+ // Here just store the masked first 32bit value for future size
+ // calculation
//
- PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
- } else {
+ PciIoDevice->PciBar[BarIndex].Length = Value & Mask;
PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
- }
- break;
- //
- // memory space; anywhere in 64 bit address space
- //
- case 0x04:
- if ((Value & 0x08) != 0) {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem64;
- } else {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem64;
- }
+ //
+ // Increment the offset to point to next DWORD
+ //
+ Offset += 4;
- //
- // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
- // is regarded as an extension for the first bar. As a result
- // the sizing will be conducted on combined 64 bit value
- // Here just store the masked first 32bit value for future size
- // calculation
- //
- PciIoDevice->PciBar[BarIndex].Length = Value & Mask;
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
+ Status = BarExisted (
+ PciIoDevice,
+ Offset,
+ &Value,
+ &OriginalValue
+ );
- //
- // Increment the offset to point to next DWORD
- //
- Offset += 4;
+ if (EFI_ERROR (Status)) {
+ //
+ // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
+ //
+ if (PciIoDevice->PciBar[BarIndex].Length == 0) {
+ //
+ // some device implement MMIO bar with 0 length, need to treat it as no-bar
+ //
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
+ return Offset + 4;
+ }
+ }
- Status = BarExisted (
- PciIoDevice,
- Offset,
- &Value,
- &OriginalValue
- );
+ //
+ // Fix the length to support some special 64 bit BAR
+ //
+ if (Value == 0) {
+ DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
+ Value = (UINT32)-1;
+ } else {
+ Value |= ((UINT32)(-1) << HighBitSet32 (Value));
+ }
- if (EFI_ERROR (Status)) {
//
- // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
+ // Calculate the size of 64bit bar
//
- if (PciIoDevice->PciBar[BarIndex].Length == 0) {
+ PciIoDevice->PciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64)OriginalValue, 32);
+
+ PciIoDevice->PciBar[BarIndex].Length = PciIoDevice->PciBar[BarIndex].Length | LShiftU64 ((UINT64)Value, 32);
+ PciIoDevice->PciBar[BarIndex].Length = (~(PciIoDevice->PciBar[BarIndex].Length)) + 1;
+ if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
//
- // some device implement MMIO bar with 0 length, need to treat it as no-bar
+ // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
//
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
- return Offset + 4;
+ PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
+ } else {
+ PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
}
- }
- //
- // Fix the length to support some special 64 bit BAR
- //
- if (Value == 0) {
- DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
- Value = (UINT32) -1;
- } else {
- Value |= ((UINT32)(-1) << HighBitSet32 (Value));
- }
+ break;
//
- // Calculate the size of 64bit bar
+ // reserved
//
- PciIoDevice->PciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64) OriginalValue, 32);
-
- PciIoDevice->PciBar[BarIndex].Length = PciIoDevice->PciBar[BarIndex].Length | LShiftU64 ((UINT64) Value, 32);
- PciIoDevice->PciBar[BarIndex].Length = (~(PciIoDevice->PciBar[BarIndex].Length)) + 1;
- if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
- //
- // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
- //
- PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
- } else {
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
- }
-
- break;
+ default:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
+ PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
+ //
+ // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
+ //
+ PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
+ } else {
+ PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
+ }
- //
- // reserved
- //
- default:
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
- PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
- //
- // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
- //
- PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
- } else {
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
- }
- break;
+ break;
}
}
@@ -1970,11 +1954,11 @@ PciParseBar ( **/
VOID
InitializePciDevice (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT8 Offset;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 Offset;
PciIo = &(PciIoDevice->PciIo);
@@ -1996,10 +1980,10 @@ InitializePciDevice ( **/
VOID
InitializePpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = &(PciIoDevice->PciIo);
@@ -2040,10 +2024,10 @@ InitializePpb ( **/
VOID
InitializeP2C (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = &(PciIoDevice->PciIo);
@@ -2081,7 +2065,7 @@ InitializeP2C ( **/
EFI_STATUS
AuthenticatePciDevice (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
EDKII_DEVICE_IDENTIFIER DeviceIdentifier;
@@ -2094,15 +2078,15 @@ AuthenticatePciDevice ( DeviceIdentifier.Version = EDKII_DEVICE_IDENTIFIER_REVISION;
CopyGuid (&DeviceIdentifier.DeviceType, &gEdkiiDeviceIdentifierTypePciGuid);
DeviceIdentifier.DeviceHandle = NULL;
- Status = gBS->InstallMultipleProtocolInterfaces (
- &DeviceIdentifier.DeviceHandle,
- &gEfiDevicePathProtocolGuid,
- PciIoDevice->DevicePath,
- &gEdkiiDeviceIdentifierTypePciGuid,
- &PciIoDevice->PciIo,
- NULL
- );
- if (EFI_ERROR(Status)) {
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &DeviceIdentifier.DeviceHandle,
+ &gEfiDevicePathProtocolGuid,
+ PciIoDevice->DevicePath,
+ &gEdkiiDeviceIdentifierTypePciGuid,
+ &PciIoDevice->PciIo,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -2115,13 +2099,13 @@ AuthenticatePciDevice ( // No need to check return Status.
//
gBS->UninstallMultipleProtocolInterfaces (
- DeviceIdentifier.DeviceHandle,
- &gEfiDevicePathProtocolGuid,
- PciIoDevice->DevicePath,
- &gEdkiiDeviceIdentifierTypePciGuid,
- &PciIoDevice->PciIo,
- NULL
- );
+ DeviceIdentifier.DeviceHandle,
+ &gEfiDevicePathProtocolGuid,
+ PciIoDevice->DevicePath,
+ &gEdkiiDeviceIdentifierTypePciGuid,
+ &PciIoDevice->PciIo,
+ NULL
+ );
return Status;
}
@@ -2146,11 +2130,11 @@ AuthenticatePciDevice ( **/
PCI_IO_DEVICE *
CreatePciIoDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
PCI_IO_DEVICE *PciIoDevice;
@@ -2162,14 +2146,14 @@ CreatePciIoDevice ( return NULL;
}
- PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;
- PciIoDevice->Handle = NULL;
- PciIoDevice->PciRootBridgeIo = Bridge->PciRootBridgeIo;
- PciIoDevice->DevicePath = NULL;
- PciIoDevice->BusNumber = Bus;
- PciIoDevice->DeviceNumber = Device;
- PciIoDevice->FunctionNumber = Func;
- PciIoDevice->Decodes = 0;
+ PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;
+ PciIoDevice->Handle = NULL;
+ PciIoDevice->PciRootBridgeIo = Bridge->PciRootBridgeIo;
+ PciIoDevice->DevicePath = NULL;
+ PciIoDevice->BusNumber = Bus;
+ PciIoDevice->DeviceNumber = Device;
+ PciIoDevice->FunctionNumber = Func;
+ PciIoDevice->Decodes = 0;
if (gFullEnumeration) {
PciIoDevice->Allocated = FALSE;
@@ -2177,13 +2161,13 @@ CreatePciIoDevice ( PciIoDevice->Allocated = TRUE;
}
- PciIoDevice->Registered = FALSE;
- PciIoDevice->Attributes = 0;
- PciIoDevice->Supports = 0;
- PciIoDevice->BusOverride = FALSE;
- PciIoDevice->AllOpRomProcessed = FALSE;
+ PciIoDevice->Registered = FALSE;
+ PciIoDevice->Attributes = 0;
+ PciIoDevice->Supports = 0;
+ PciIoDevice->BusOverride = FALSE;
+ PciIoDevice->AllOpRomProcessed = FALSE;
- PciIoDevice->IsPciExp = FALSE;
+ PciIoDevice->IsPciExp = FALSE;
CopyMem (&(PciIoDevice->Pci), Pci, sizeof (PCI_TYPE01));
@@ -2207,12 +2191,12 @@ CreatePciIoDevice ( // Detect if PCI Express Device
//
PciIoDevice->PciExpressCapabilityOffset = 0;
- Status = LocateCapabilityRegBlock (
- PciIoDevice,
- EFI_PCI_CAPABILITY_ID_PCIEXP,
- &PciIoDevice->PciExpressCapabilityOffset,
- NULL
- );
+ Status = LocateCapabilityRegBlock (
+ PciIoDevice,
+ EFI_PCI_CAPABILITY_ID_PCIEXP,
+ &PciIoDevice->PciExpressCapabilityOffset,
+ NULL
+ );
if (!EFI_ERROR (Status)) {
PciIoDevice->IsPciExp = TRUE;
}
@@ -2224,10 +2208,11 @@ CreatePciIoDevice ( //
// If authentication fails, skip this device.
//
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
if (PciIoDevice->DevicePath != NULL) {
FreePool (PciIoDevice->DevicePath);
}
+
FreePool (PciIoDevice);
return NULL;
}
@@ -2255,32 +2240,32 @@ CreatePciIoDevice ( //
ParentPciIo = &Bridge->PciIo;
ParentPciIo->Pci.Read (
- ParentPciIo,
- EfiPciIoWidthUint32,
- Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,
- 1,
- &Data32
- );
+ ParentPciIo,
+ EfiPciIoWidthUint32,
+ Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,
+ 1,
+ &Data32
+ );
if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {
//
// ARI forward support in bridge, so enable it.
//
ParentPciIo->Pci.Read (
- ParentPciIo,
- EfiPciIoWidthUint32,
- Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
- 1,
- &Data32
- );
+ ParentPciIo,
+ EfiPciIoWidthUint32,
+ Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
+ 1,
+ &Data32
+ );
if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING) == 0) {
Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
ParentPciIo->Pci.Write (
- ParentPciIo,
- EfiPciIoWidthUint32,
- Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
- 1,
- &Data32
- );
+ ParentPciIo,
+ EfiPciIoWidthUint32,
+ Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
+ 1,
+ &Data32
+ );
DEBUG ((
DEBUG_INFO,
" ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
@@ -2307,17 +2292,17 @@ CreatePciIoDevice ( NULL
);
if (!EFI_ERROR (Status)) {
- UINT32 SupportedPageSize;
- UINT16 VFStride;
- UINT16 FirstVFOffset;
- UINT16 Data16;
- UINT32 PFRid;
- UINT32 LastVF;
+ UINT32 SupportedPageSize;
+ UINT16 VFStride;
+ UINT16 FirstVFOffset;
+ UINT16 Data16;
+ UINT32 PFRid;
+ UINT32 LastVF;
//
// If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
//
- if (PcdGetBool (PcdAriSupport) && PciIoDevice->AriCapabilityOffset != 0) {
+ if (PcdGetBool (PcdAriSupport) && (PciIoDevice->AriCapabilityOffset != 0)) {
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@@ -2392,7 +2377,7 @@ CreatePciIoDevice ( //
// Calculate LastVF
//
- PFRid = EFI_PCI_RID(Bus, Device, Func);
+ PFRid = EFI_PCI_RID (Bus, Device, Func);
LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
//
@@ -2403,12 +2388,16 @@ CreatePciIoDevice ( DEBUG ((
DEBUG_INFO,
" SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
- SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset
+ SupportedPageSize,
+ PciIoDevice->SystemPageSize >> 12,
+ FirstVFOffset
));
DEBUG ((
DEBUG_INFO,
" InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
- PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice->SrIovCapabilityOffset
+ PciIoDevice->InitialVFs,
+ PciIoDevice->ReservedBusNum,
+ PciIoDevice->SrIovCapabilityOffset
));
}
}
@@ -2434,17 +2423,17 @@ CreatePciIoDevice ( NULL
);
if (!EFI_ERROR (Status)) {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
- UINT32 Offset;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
+ UINT32 Offset;
Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)
- + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY),
+ + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY),
PciIo->Pci.Read (
- PciIo,
- EfiPciIoWidthUint8,
- Offset,
- sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL),
- &ResizableBarControl
- );
+ PciIo,
+ EfiPciIoWidthUint8,
+ Offset,
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL),
+ &ResizableBarControl
+ );
PciIoDevice->ResizableBarNumber = ResizableBarControl.Bits.ResizableBarNumber;
PciProgramResizableBar (PciIoDevice, PciResizableBarMax);
}
@@ -2482,16 +2471,15 @@ CreatePciIoDevice ( **/
EFI_STATUS
PciEnumeratorLight (
- IN EFI_HANDLE Controller
+ IN EFI_HANDLE Controller
)
{
-
- EFI_STATUS Status;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- PCI_IO_DEVICE *RootBridgeDev;
- UINT16 MinBus;
- UINT16 MaxBus;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
+ EFI_STATUS Status;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ PCI_IO_DEVICE *RootBridgeDev;
+ UINT16 MinBus;
+ UINT16 MaxBus;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
MinBus = 0;
MaxBus = PCI_MAX_BUS;
@@ -2510,23 +2498,22 @@ PciEnumeratorLight ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
+ if (EFI_ERROR (Status) && (Status != EFI_ALREADY_STARTED)) {
return Status;
}
- Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
+ Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **)&Descriptors);
if (EFI_ERROR (Status)) {
return Status;
}
while (PciGetBusRange (&Descriptors, &MinBus, &MaxBus, NULL) == EFI_SUCCESS) {
-
//
// Create a device node for root bridge device with a NULL host bridge controller handle
//
@@ -2544,11 +2531,10 @@ PciEnumeratorLight ( Status = PciPciDeviceInfoCollector (
RootBridgeDev,
- (UINT8) MinBus
+ (UINT8)MinBus
);
if (!EFI_ERROR (Status)) {
-
//
// Remove those PCI devices which are rejected when full enumeration
//
@@ -2569,7 +2555,6 @@ PciEnumeratorLight ( //
InsertRootBridge (RootBridgeDev);
} else {
-
//
// If unsuccessfully, destroy the entire node
//
@@ -2605,15 +2590,15 @@ PciGetBusRange ( while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
if (MinBus != NULL) {
- *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;
+ *MinBus = (UINT16)(*Descriptors)->AddrRangeMin;
}
if (MaxBus != NULL) {
- *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;
+ *MaxBus = (UINT16)(*Descriptors)->AddrRangeMax;
}
if (BusRange != NULL) {
- *BusRange = (UINT16) (*Descriptors)->AddrLen;
+ *BusRange = (UINT16)(*Descriptors)->AddrLen;
}
return EFI_SUCCESS;
@@ -2636,12 +2621,12 @@ PciGetBusRange ( **/
EFI_STATUS
StartManagingRootBridge (
- IN PCI_IO_DEVICE *RootBridgeDev
+ IN PCI_IO_DEVICE *RootBridgeDev
)
{
- EFI_HANDLE RootBridgeHandle;
- EFI_STATUS Status;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_HANDLE RootBridgeHandle;
+ EFI_STATUS Status;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
//
// Get the root bridge handle
@@ -2655,13 +2640,13 @@ StartManagingRootBridge ( Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
+ if (EFI_ERROR (Status) && (Status != EFI_ALREADY_STARTED)) {
return Status;
}
@@ -2671,7 +2656,6 @@ StartManagingRootBridge ( RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
return EFI_SUCCESS;
-
}
/**
@@ -2685,7 +2669,7 @@ StartManagingRootBridge ( **/
BOOLEAN
IsPciDeviceRejected (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
@@ -2706,9 +2690,8 @@ IsPciDeviceRejected ( // Only test base registers for P2C
//
for (BarOffset = 0x1C; BarOffset <= 0x38; BarOffset += 2 * sizeof (UINT32)) {
-
- Mask = (BarOffset < 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
- Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
+ Mask = (BarOffset < 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
+ Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
if (EFI_ERROR (Status)) {
continue;
}
@@ -2735,7 +2718,6 @@ IsPciDeviceRejected ( }
if ((TestValue & 0x01) != 0) {
-
//
// IO Bar
//
@@ -2744,9 +2726,7 @@ IsPciDeviceRejected ( if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
return TRUE;
}
-
} else {
-
//
// Mem Bar
//
@@ -2754,13 +2734,11 @@ IsPciDeviceRejected ( TestValue = TestValue & Mask;
if ((TestValue & 0x07) == 0x04) {
-
//
// Mem64 or PMem64
//
BarOffset += sizeof (UINT32);
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
-
//
// Test its high 32-Bit BAR
//
@@ -2769,9 +2747,7 @@ IsPciDeviceRejected ( return TRUE;
}
}
-
} else {
-
//
// Mem32 or PMem32
//
@@ -2794,24 +2770,23 @@ IsPciDeviceRejected ( **/
VOID
ResetAllPpbBusNumber (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber
)
{
- EFI_STATUS Status;
- PCI_TYPE00 Pci;
- UINT8 Device;
- UINT32 Register;
- UINT8 Func;
- UINT64 Address;
- UINT8 SecondaryBus;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_STATUS Status;
+ PCI_TYPE00 Pci;
+ UINT8 Device;
+ UINT32 Register;
+ UINT8 Func;
+ UINT64 Address;
+ UINT8 SecondaryBus;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
PciRootBridgeIo = Bridge->PciRootBridgeIo;
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
-
//
// Check to see whether a pci device is present
//
@@ -2823,7 +2798,7 @@ ResetAllPpbBusNumber ( Func
);
- if (EFI_ERROR (Status) && Func == 0) {
+ if (EFI_ERROR (Status) && (Func == 0)) {
//
// go to next device if there is no Function 0
//
@@ -2831,16 +2806,15 @@ ResetAllPpbBusNumber ( }
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {
-
- Register = 0;
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
- Status = PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- EfiPciWidthUint32,
- Address,
- 1,
- &Register
- );
+ Register = 0;
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
+ Status = PciRootBridgeIo->Pci.Read (
+ PciRootBridgeIo,
+ EfiPciWidthUint32,
+ Address,
+ 1,
+ &Register
+ );
SecondaryBus = (UINT8)(Register >> 8);
if (SecondaryBus != 0) {
@@ -2851,16 +2825,16 @@ ResetAllPpbBusNumber ( // Reset register 18h, 19h, 1Ah on PCI Bridge
//
Register &= 0xFF000000;
- Status = PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- EfiPciWidthUint32,
- Address,
- 1,
- &Register
- );
+ Status = PciRootBridgeIo->Pci.Write (
+ PciRootBridgeIo,
+ EfiPciWidthUint32,
+ Address,
+ 1,
+ &Register
+ );
}
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
+ if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
//
// Skip sub functions, this is not a multi function device
//
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h index 4581b270c9..0ded4bea4f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h @@ -24,11 +24,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
PciDevicePresent (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
- OUT PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
+ OUT PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
);
/**
@@ -46,8 +46,8 @@ PciDevicePresent ( **/
EFI_STATUS
PciPciDeviceInfoCollector (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber
);
/**
@@ -66,12 +66,12 @@ PciPciDeviceInfoCollector ( **/
EFI_STATUS
PciSearchDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func,
- OUT PCI_IO_DEVICE **PciDevice
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func,
+ OUT PCI_IO_DEVICE **PciDevice
);
/**
@@ -88,11 +88,11 @@ PciSearchDevice ( **/
PCI_IO_DEVICE *
GatherDeviceInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
);
/**
@@ -109,11 +109,11 @@ GatherDeviceInfo ( **/
PCI_IO_DEVICE *
GatherPpbInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
);
/**
@@ -130,11 +130,11 @@ GatherPpbInfo ( **/
PCI_IO_DEVICE *
GatherP2CInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
);
/**
@@ -148,8 +148,8 @@ GatherP2CInfo ( **/
EFI_DEVICE_PATH_PROTOCOL *
CreatePciDevicePath (
- IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
- IN PCI_IO_DEVICE *PciIoDevice
+ IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -166,10 +166,10 @@ CreatePciDevicePath ( **/
EFI_STATUS
VfBarExisted (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINTN Offset,
- OUT UINT32 *BarLengthValue,
- OUT UINT32 *OriginalBarValue
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Offset,
+ OUT UINT32 *BarLengthValue,
+ OUT UINT32 *OriginalBarValue
);
/**
@@ -186,10 +186,10 @@ VfBarExisted ( **/
EFI_STATUS
BarExisted (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINTN Offset,
- OUT UINT32 *BarLengthValue,
- OUT UINT32 *OriginalBarValue
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Offset,
+ OUT UINT32 *BarLengthValue,
+ OUT UINT32 *OriginalBarValue
);
/**
@@ -206,11 +206,11 @@ BarExisted ( **/
VOID
PciTestSupportedAttribute (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN OUT UINT16 *Command,
- IN OUT UINT16 *BridgeControl,
- OUT UINT16 *OldCommand,
- OUT UINT16 *OldBridgeControl
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN OUT UINT16 *Command,
+ IN OUT UINT16 *BridgeControl,
+ OUT UINT16 *OldCommand,
+ OUT UINT16 *OldBridgeControl
);
/**
@@ -224,10 +224,10 @@ PciTestSupportedAttribute ( **/
VOID
PciSetDeviceAttribute (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT16 Command,
- IN UINT16 BridgeControl,
- IN UINTN Option
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 Command,
+ IN UINT16 BridgeControl,
+ IN UINTN Option
);
/**
@@ -242,8 +242,8 @@ PciSetDeviceAttribute ( **/
EFI_STATUS
GetFastBackToBackSupport (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT8 StatusIndex
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT8 StatusIndex
);
/**
@@ -254,7 +254,7 @@ GetFastBackToBackSupport ( **/
EFI_STATUS
DetermineDeviceAttribute (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -269,7 +269,7 @@ DetermineDeviceAttribute ( **/
EFI_STATUS
UpdatePciInfo (
- IN OUT PCI_IO_DEVICE *PciIoDevice
+ IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -281,8 +281,8 @@ UpdatePciInfo ( **/
VOID
SetNewAlign (
- IN OUT UINT64 *Alignment,
- IN UINT64 NewAlignment
+ IN OUT UINT64 *Alignment,
+ IN UINT64 NewAlignment
);
/**
@@ -329,7 +329,7 @@ PciIovParseVfBar ( **/
VOID
InitializePciDevice (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -340,7 +340,7 @@ InitializePciDevice ( **/
VOID
InitializePpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -351,7 +351,7 @@ InitializePpb ( **/
VOID
InitializeP2C (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -369,11 +369,11 @@ InitializeP2C ( **/
PCI_IO_DEVICE *
CreatePciIoDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
);
/**
@@ -390,7 +390,7 @@ CreatePciIoDevice ( **/
EFI_STATUS
PciEnumeratorLight (
- IN EFI_HANDLE Controller
+ IN EFI_HANDLE Controller
);
/**
@@ -424,7 +424,7 @@ PciGetBusRange ( **/
EFI_STATUS
StartManagingRootBridge (
- IN PCI_IO_DEVICE *RootBridgeDev
+ IN PCI_IO_DEVICE *RootBridgeDev
);
/**
@@ -438,7 +438,7 @@ StartManagingRootBridge ( **/
BOOLEAN
IsPciDeviceRejected (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -450,8 +450,8 @@ IsPciDeviceRejected ( **/
VOID
ResetAllPpbBusNumber (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber
);
/**
@@ -463,8 +463,8 @@ ResetAllPpbBusNumber ( **/
VOID
DumpPpbPaddingResource (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN PCI_BAR_TYPE ResourceType
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN PCI_BAR_TYPE ResourceType
);
/**
@@ -474,7 +474,7 @@ DumpPpbPaddingResource ( **/
VOID
DumpPciBars (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c index 0dc8ec23b0..810867a200 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c @@ -13,7 +13,6 @@ EFI_HPC_LOCATION *gPciRootHpcPool = NULL; UINTN gPciRootHpcCount = 0;
ROOT_HPC_DATA *gPciRootHpcData = NULL;
-
/**
Event notification function to set Hot Plug controller status.
@@ -24,14 +23,14 @@ ROOT_HPC_DATA *gPciRootHpcData = NULL; VOID
EFIAPI
PciHPCInitialized (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- ROOT_HPC_DATA *HpcData;
+ ROOT_HPC_DATA *HpcData;
- HpcData = (ROOT_HPC_DATA *) Context;
- HpcData->Initialized = TRUE;
+ HpcData = (ROOT_HPC_DATA *)Context;
+ HpcData->Initialized = TRUE;
}
/**
@@ -46,12 +45,12 @@ PciHPCInitialized ( **/
BOOLEAN
EfiCompareDevicePath (
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
)
{
- UINTN Size1;
- UINTN Size2;
+ UINTN Size1;
+ UINTN Size2;
Size1 = GetDevicePathSize (DevicePath1);
Size2 = GetDevicePathSize (DevicePath2);
@@ -100,7 +99,7 @@ InitializeHotPlugSupport ( Status = gBS->LocateProtocol (
&gEfiPciHotPlugInitProtocolGuid,
NULL,
- (VOID **) &gPciHotPlugInit
+ (VOID **)&gPciHotPlugInit
);
if (EFI_ERROR (Status)) {
@@ -114,10 +113,9 @@ InitializeHotPlugSupport ( );
if (!EFI_ERROR (Status)) {
-
- gPciRootHpcPool = HpcList;
- gPciRootHpcCount = HpcCount;
- gPciRootHpcData = AllocateZeroPool (sizeof (ROOT_HPC_DATA) * gPciRootHpcCount);
+ gPciRootHpcPool = HpcList;
+ gPciRootHpcCount = HpcCount;
+ gPciRootHpcData = AllocateZeroPool (sizeof (ROOT_HPC_DATA) * gPciRootHpcCount);
if (gPciRootHpcData == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -139,16 +137,14 @@ InitializeHotPlugSupport ( **/
BOOLEAN
IsRootPciHotPlugBus (
- IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
- OUT UINTN *HpIndex OPTIONAL
+ IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
+ OUT UINTN *HpIndex OPTIONAL
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < gPciRootHpcCount; Index++) {
-
if (EfiCompareDevicePath (gPciRootHpcPool[Index].HpbDevicePath, HpbDevicePath)) {
-
if (HpIndex != NULL) {
*HpIndex = Index;
}
@@ -173,16 +169,14 @@ IsRootPciHotPlugBus ( **/
BOOLEAN
IsRootPciHotPlugController (
- IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
- OUT UINTN *HpIndex
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
+ OUT UINTN *HpIndex
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < gPciRootHpcCount; Index++) {
-
if (EfiCompareDevicePath (gPciRootHpcPool[Index].HpcDevicePath, HpcDevicePath)) {
-
if (HpIndex != NULL) {
*HpIndex = Index;
}
@@ -237,17 +231,16 @@ CreateEventForHpc ( **/
EFI_STATUS
AllRootHPCInitialized (
- IN UINTN TimeoutInMicroSeconds
+ IN UINTN TimeoutInMicroSeconds
)
{
UINT32 Delay;
UINTN Index;
- Delay = (UINT32) ((TimeoutInMicroSeconds / 30) + 1);
+ Delay = (UINT32)((TimeoutInMicroSeconds / 30) + 1);
do {
for (Index = 0; Index < gPciRootHpcCount; Index++) {
-
if (gPciRootHpcData[Index].Found && !gPciRootHpcData[Index].Initialized) {
break;
}
@@ -263,7 +256,6 @@ AllRootHPCInitialized ( gBS->Stall (30);
Delay--;
-
} while (Delay > 0);
return EFI_TIMEOUT;
@@ -280,10 +272,9 @@ AllRootHPCInitialized ( **/
BOOLEAN
IsSHPC (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
-
EFI_STATUS Status;
UINT8 Offset;
@@ -293,11 +284,11 @@ IsSHPC ( Offset = 0;
Status = LocateCapabilityRegBlock (
- PciIoDevice,
- EFI_PCI_CAPABILITY_ID_SHPC,
- &Offset,
- NULL
- );
+ PciIoDevice,
+ EFI_PCI_CAPABILITY_ID_SHPC,
+ &Offset,
+ NULL
+ );
//
// If the PCI-PCI bridge has the hot plug controller build-in,
@@ -328,13 +319,13 @@ IsSHPC ( **/
BOOLEAN
SupportsPcieHotplug (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- UINT32 Offset;
- EFI_STATUS Status;
- PCI_REG_PCIE_CAPABILITY Capability;
- PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
+ UINT32 Offset;
+ EFI_STATUS Status;
+ PCI_REG_PCIE_CAPABILITY Capability;
+ PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
if (PciIoDevice == NULL) {
return FALSE;
@@ -346,6 +337,7 @@ SupportsPcieHotplug ( if (!PciIoDevice->IsPciExp) {
return FALSE;
}
+
Offset = PciIoDevice->PciExpressCapabilityOffset +
OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability);
Status = PciIoDevice->PciIo.Pci.Read (
@@ -363,12 +355,13 @@ SupportsPcieHotplug ( // Check the contents of the register
//
switch (Capability.Bits.DevicePortType) {
- case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
- case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
- break;
- default:
- return FALSE;
+ case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
+ case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
+ break;
+ default:
+ return FALSE;
}
+
if (!Capability.Bits.SlotImplemented) {
return FALSE;
}
@@ -395,6 +388,7 @@ SupportsPcieHotplug ( if (SlotCapability.Bits.HotPlugCapable) {
return TRUE;
}
+
return FALSE;
}
@@ -406,34 +400,34 @@ SupportsPcieHotplug ( **/
VOID
GetResourcePaddingForHpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_STATUS Status;
- EFI_HPC_STATE State;
- UINT64 PciAddress;
- EFI_HPC_PADDING_ATTRIBUTES Attributes;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
+ EFI_STATUS Status;
+ EFI_HPC_STATE State;
+ UINT64 PciAddress;
+ EFI_HPC_PADDING_ATTRIBUTES Attributes;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
if (IsPciHotPlugBus (PciIoDevice)) {
//
// If PCI-PCI bridge device is PCI Hot Plug bus.
//
PciAddress = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
- Status = gPciHotPlugInit->GetResourcePadding (
- gPciHotPlugInit,
- PciIoDevice->DevicePath,
- PciAddress,
- &State,
- (VOID **) &Descriptors,
- &Attributes
- );
+ Status = gPciHotPlugInit->GetResourcePadding (
+ gPciHotPlugInit,
+ PciIoDevice->DevicePath,
+ PciAddress,
+ &State,
+ (VOID **)&Descriptors,
+ &Attributes
+ );
if (EFI_ERROR (Status)) {
return;
}
- if ((State & EFI_HPC_STATE_ENABLED) != 0 && (State & EFI_HPC_STATE_INITIALIZED) != 0) {
+ if (((State & EFI_HPC_STATE_ENABLED) != 0) && ((State & EFI_HPC_STATE_INITIALIZED) != 0)) {
PciIoDevice->ResourcePaddingDescriptors = Descriptors;
PciIoDevice->PaddingAttributes = Attributes;
}
@@ -453,7 +447,7 @@ GetResourcePaddingForHpb ( **/
BOOLEAN
IsPciHotPlugBus (
- PCI_IO_DEVICE *PciIoDevice
+ PCI_IO_DEVICE *PciIoDevice
)
{
if (IsSHPC (PciIoDevice)) {
@@ -475,10 +469,9 @@ IsPciHotPlugBus ( //
// Otherwise, see if it is a Root HPC
//
- if(IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL)) {
+ if (IsRootPciHotPlugBus (PciIoDevice->DevicePath, NULL)) {
return TRUE;
}
return FALSE;
}
-
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h index e97d75362d..6ee43db250 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h @@ -12,24 +12,24 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// stall 1 second, its unit is 100ns
//
-#define STALL_1_SECOND 1000000
+#define STALL_1_SECOND 1000000
//
// PCI Hot Plug controller private data
//
typedef struct {
- EFI_EVENT Event;
- BOOLEAN Found;
- BOOLEAN Initialized;
- VOID *Padding;
+ EFI_EVENT Event;
+ BOOLEAN Found;
+ BOOLEAN Initialized;
+ VOID *Padding;
} ROOT_HPC_DATA;
//
// Reference of some global variables
//
-extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;
-extern EFI_HPC_LOCATION *gPciRootHpcPool;
-extern ROOT_HPC_DATA *gPciRootHpcData;
+extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;
+extern EFI_HPC_LOCATION *gPciRootHpcPool;
+extern ROOT_HPC_DATA *gPciRootHpcData;
/**
Event notification function to set Hot Plug controller status.
@@ -41,8 +41,8 @@ extern ROOT_HPC_DATA *gPciRootHpcData; VOID
EFIAPI
PciHPCInitialized (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
);
/**
@@ -57,8 +57,8 @@ PciHPCInitialized ( **/
BOOLEAN
EfiCompareDevicePath (
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath1,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath2
);
/**
@@ -90,7 +90,7 @@ InitializeHotPlugSupport ( **/
BOOLEAN
IsPciHotPlugBus (
- PCI_IO_DEVICE *PciIoDevice
+ PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -106,8 +106,8 @@ IsPciHotPlugBus ( **/
BOOLEAN
IsRootPciHotPlugBus (
- IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
- OUT UINTN *HpIndex OPTIONAL
+ IN EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath,
+ OUT UINTN *HpIndex OPTIONAL
);
/**
@@ -123,8 +123,8 @@ IsRootPciHotPlugBus ( **/
BOOLEAN
IsRootPciHotPlugController (
- IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
- OUT UINTN *HpIndex
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
+ OUT UINTN *HpIndex
);
/**
@@ -153,7 +153,7 @@ CreateEventForHpc ( **/
EFI_STATUS
AllRootHPCInitialized (
- IN UINTN TimeoutInMicroSeconds
+ IN UINTN TimeoutInMicroSeconds
);
/**
@@ -167,7 +167,7 @@ AllRootHPCInitialized ( **/
BOOLEAN
IsSHPC (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -188,7 +188,7 @@ IsSHPC ( **/
BOOLEAN
SupportsPcieHotplug (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -199,7 +199,7 @@ SupportsPcieHotplug ( **/
VOID
GetResourcePaddingForHpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c index 996d6fbe92..843815d0cb 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -8,7 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciBus.h"
-extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
+extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
//
// Pci Io Protocol Interface
@@ -50,7 +50,7 @@ EFI_PCI_IO_PROTOCOL mPciIoInterface = { **/
VOID
InitializePciIoInstance (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));
@@ -73,12 +73,12 @@ InitializePciIoInstance ( **/
EFI_STATUS
PciIoVerifyBarAccess (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT8 BarIndex,
- IN PCI_BAR_TYPE Type,
- IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN IN UINTN Count,
- IN UINT64 *Offset
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT8 BarIndex,
+ IN PCI_BAR_TYPE Type,
+ IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN IN UINTN Count,
+ IN UINT64 *Offset
)
{
if ((UINT32)Width >= EfiPciIoWidthMaximum) {
@@ -104,11 +104,11 @@ PciIoVerifyBarAccess ( // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX
// If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
//
- if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {
+ if ((Width >= EfiPciIoWidthFifoUint8) && (Width <= EfiPciIoWidthFifoUint64)) {
Count = 1;
}
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & 0x03);
if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {
return EFI_INVALID_PARAMETER;
@@ -149,17 +149,16 @@ PciIoVerifyConfigAccess ( //
// If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
//
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & 0x03);
if (PciIoDevice->IsPciExp) {
if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {
return EFI_UNSUPPORTED;
}
- ExtendOffset = LShiftU64 (*Offset, 32);
- *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
- *Offset = (*Offset) | ExtendOffset;
-
+ ExtendOffset = LShiftU64 (*Offset, 32);
+ *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
+ *Offset = (*Offset) | ExtendOffset;
} else {
if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {
return EFI_UNSUPPORTED;
@@ -206,8 +205,8 @@ PciIoPollMem ( OUT UINT64 *Result
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -229,29 +228,34 @@ PciIoPollMem ( //
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
- Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
+ Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
}
- if ((*Result & Mask) == Value || Delay == 0) {
+
+ if (((*Result & Mask) == Value) || (Delay == 0)) {
return EFI_SUCCESS;
}
+
do {
//
// Stall 10 us = 100 * 100ns
//
gBS->Stall (10);
- Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
+ Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
}
+
if ((*Result & Mask) == Value) {
return EFI_SUCCESS;
}
+
if (Delay <= 100) {
return EFI_TIMEOUT;
}
+
Delay -= 100;
} while (TRUE);
}
@@ -259,7 +263,7 @@ PciIoPollMem ( Status = PciIoDevice->PciRootBridgeIo->PollMem (
PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Offset,
Mask,
Value,
@@ -313,8 +317,8 @@ PciIoPollIo ( OUT UINT64 *Result
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -332,29 +336,34 @@ PciIoPollIo ( //
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
- Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
+ Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
}
- if ((*Result & Mask) == Value || Delay == 0) {
+
+ if (((*Result & Mask) == Value) || (Delay == 0)) {
return EFI_SUCCESS;
}
+
do {
//
// Stall 10 us = 100 * 100ns
//
gBS->Stall (10);
- Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
+ Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
}
+
if ((*Result & Mask) == Value) {
return EFI_SUCCESS;
}
+
if (Delay <= 100) {
return EFI_TIMEOUT;
}
+
Delay -= 100;
} while (TRUE);
}
@@ -362,7 +371,7 @@ PciIoPollIo ( Status = PciIoDevice->PciRootBridgeIo->PollIo (
PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Offset,
Mask,
Value,
@@ -412,8 +421,8 @@ PciIoMemRead ( IN OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -436,18 +445,17 @@ PciIoMemRead ( if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
}
}
-
Status = PciIoDevice->PciRootBridgeIo->Mem.Read (
- PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
- Offset,
- Count,
- Buffer
- );
+ PciIoDevice->PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ Offset,
+ Count,
+ Buffer
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -491,8 +499,8 @@ PciIoMemWrite ( IN OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -515,17 +523,17 @@ PciIoMemWrite ( if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
}
}
Status = PciIoDevice->PciRootBridgeIo->Mem.Write (
- PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
- Offset,
- Count,
- Buffer
- );
+ PciIoDevice->PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ Offset,
+ Count,
+ Buffer
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -569,8 +577,8 @@ PciIoIoRead ( IN OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -593,13 +601,13 @@ PciIoIoRead ( if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
}
}
Status = PciIoDevice->PciRootBridgeIo->Io.Read (
PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Offset,
Count,
Buffer
@@ -647,8 +655,8 @@ PciIoIoWrite ( IN OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -671,13 +679,13 @@ PciIoIoWrite ( if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
}
}
Status = PciIoDevice->PciRootBridgeIo->Io.Write (
PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Offset,
Count,
Buffer
@@ -722,14 +730,14 @@ PciIoConfigRead ( IN OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
- UINT64 Address;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
+ UINT64 Address;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
- Address = Offset;
- Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
+ Address = Offset;
+ Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -740,13 +748,13 @@ PciIoConfigRead ( if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
}
}
Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Address,
Count,
Buffer
@@ -791,14 +799,14 @@ PciIoConfigWrite ( IN OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
- UINT64 Address;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
+ UINT64 Address;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
- Address = Offset;
- Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
+ Address = Offset;
+ Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -809,17 +817,17 @@ PciIoConfigWrite ( if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
Count *= (UINTN)(1 << (Width & 0x03));
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
}
}
Status = PciIoDevice->PciRootBridgeIo->Pci.Write (
- PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
- Address,
- Count,
- Buffer
- );
+ PciIoDevice->PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ Address,
+ Count,
+ Buffer
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -863,17 +871,17 @@ PciIoConfigWrite ( EFI_STATUS
EFIAPI
PciIoCopyMem (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 DestBarIndex,
- IN UINT64 DestOffset,
- IN UINT8 SrcBarIndex,
- IN UINT64 SrcOffset,
- IN UINTN Count
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -881,14 +889,15 @@ PciIoCopyMem ( return EFI_INVALID_PARAMETER;
}
- if (Width == EfiPciIoWidthFifoUint8 ||
- Width == EfiPciIoWidthFifoUint16 ||
- Width == EfiPciIoWidthFifoUint32 ||
- Width == EfiPciIoWidthFifoUint64 ||
- Width == EfiPciIoWidthFillUint8 ||
- Width == EfiPciIoWidthFillUint16 ||
- Width == EfiPciIoWidthFillUint32 ||
- Width == EfiPciIoWidthFillUint64) {
+ if ((Width == EfiPciIoWidthFifoUint8) ||
+ (Width == EfiPciIoWidthFifoUint16) ||
+ (Width == EfiPciIoWidthFifoUint32) ||
+ (Width == EfiPciIoWidthFifoUint64) ||
+ (Width == EfiPciIoWidthFillUint8) ||
+ (Width == EfiPciIoWidthFillUint16) ||
+ (Width == EfiPciIoWidthFillUint32) ||
+ (Width == EfiPciIoWidthFillUint64))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -906,19 +915,19 @@ PciIoCopyMem ( // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
//
if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
- if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {
+ if (((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0) || ((DestOffset & ((1 << (Width & 0x03)) - 1)) != 0)) {
Count *= (UINTN)(1 << (Width & 0x03));
- Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
}
}
Status = PciIoDevice->PciRootBridgeIo->CopyMem (
- PciIoDevice->PciRootBridgeIo,
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
- DestOffset,
- SrcOffset,
- Count
- );
+ PciIoDevice->PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ DestOffset,
+ SrcOffset,
+ Count
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -972,7 +981,7 @@ PciIoMap ( return EFI_INVALID_PARAMETER;
}
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
+ if ((HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) || (Mapping == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -982,13 +991,13 @@ PciIoMap ( }
Status = PciIoDevice->PciRootBridgeIo->Map (
- PciIoDevice->PciRootBridgeIo,
- RootBridgeIoOperation,
- HostAddress,
- NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+ PciIoDevice->PciRootBridgeIo,
+ RootBridgeIoOperation,
+ HostAddress,
+ NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -1001,19 +1010,20 @@ PciIoMap ( if (mIoMmuProtocol != NULL) {
if (!EFI_ERROR (Status)) {
switch (Operation) {
- case EfiPciIoOperationBusMasterRead:
- IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;
- break;
- case EfiPciIoOperationBusMasterWrite:
- IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;
- break;
- case EfiPciIoOperationBusMasterCommonBuffer:
- IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
- break;
- default:
- ASSERT(FALSE);
- return EFI_INVALID_PARAMETER;
+ case EfiPciIoOperationBusMasterRead:
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;
+ break;
+ case EfiPciIoOperationBusMasterWrite:
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ case EfiPciIoOperationBusMasterCommonBuffer:
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
}
+
mIoMmuProtocol->SetAttribute (
mIoMmuProtocol,
PciIoDevice->Handle,
@@ -1043,8 +1053,8 @@ PciIoUnmap ( IN VOID *Mapping
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -1058,9 +1068,9 @@ PciIoUnmap ( }
Status = PciIoDevice->PciRootBridgeIo->Unmap (
- PciIoDevice->PciRootBridgeIo,
- Mapping
- );
+ PciIoDevice->PciRootBridgeIo,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -1096,19 +1106,20 @@ PciIoUnmap ( EFI_STATUS
EFIAPI
PciIoAllocateBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
if ((Attributes &
- (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){
+ (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0)
+ {
return EFI_UNSUPPORTED;
}
@@ -1119,13 +1130,13 @@ PciIoAllocateBuffer ( }
Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (
- PciIoDevice->PciRootBridgeIo,
- Type,
- MemoryType,
- Pages,
- HostAddress,
- Attributes
- );
+ PciIoDevice->PciRootBridgeIo,
+ Type,
+ MemoryType,
+ Pages,
+ HostAddress,
+ Attributes
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -1153,21 +1164,21 @@ PciIoAllocateBuffer ( EFI_STATUS
EFIAPI
PciIoFreeBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINTN Pages,
- IN VOID *HostAddress
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (
- PciIoDevice->PciRootBridgeIo,
- Pages,
- HostAddress
- );
+ PciIoDevice->PciRootBridgeIo,
+ Pages,
+ HostAddress
+ );
if (EFI_ERROR (Status)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -1197,8 +1208,8 @@ PciIoFlush ( IN EFI_PCI_IO_PROTOCOL *This
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
@@ -1239,11 +1250,11 @@ PciIoGetLocation ( OUT UINTN *Function
)
{
- PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
- if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {
+ if ((Segment == NULL) || (Bus == NULL) || (Device == NULL) || (Function == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -1269,34 +1280,35 @@ PciIoGetLocation ( **/
BOOLEAN
CheckBarType (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT8 BarIndex,
- IN PCI_BAR_TYPE BarType
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT8 BarIndex,
+ IN PCI_BAR_TYPE BarType
)
{
switch (BarType) {
+ case PciBarTypeMem:
+
+ if ((PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32) &&
+ (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32) &&
+ (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64) &&
+ (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64))
+ {
+ return FALSE;
+ }
- case PciBarTypeMem:
-
- if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&
- PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&
- PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&
- PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {
- return FALSE;
- }
-
- return TRUE;
+ return TRUE;
- case PciBarTypeIo:
- if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&
- PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){
- return FALSE;
- }
+ case PciBarTypeIo:
+ if ((PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32) &&
+ (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16))
+ {
+ return FALSE;
+ }
- return TRUE;
+ return TRUE;
- default:
- break;
+ default:
+ break;
}
return FALSE;
@@ -1329,10 +1341,10 @@ ModifyRootBridgeAttributes ( // Get the current attributes of this PCI device's PCI Root Bridge
//
Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
- PciIoDevice->PciRootBridgeIo,
- &PciRootBridgeSupports,
- &PciRootBridgeAttributes
- );
+ PciIoDevice->PciRootBridgeIo,
+ &PciRootBridgeSupports,
+ &PciRootBridgeAttributes
+ );
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
@@ -1357,13 +1369,12 @@ ModifyRootBridgeAttributes ( // Call the PCI Root Bridge to attempt to modify the attributes
//
if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {
-
Status = PciIoDevice->PciRootBridgeIo->SetAttributes (
- PciIoDevice->PciRootBridgeIo,
- NewPciRootBridgeAttributes,
- NULL,
- NULL
- );
+ PciIoDevice->PciRootBridgeIo,
+ NewPciRootBridgeAttributes,
+ NULL,
+ NULL
+ );
if (EFI_ERROR (Status)) {
//
// The PCI Root Bridge could not modify the attributes, so return the error.
@@ -1396,8 +1407,8 @@ SupportPaletteSnoopAttributes ( IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
)
{
- PCI_IO_DEVICE *Temp;
- UINT16 VGACommand;
+ PCI_IO_DEVICE *Temp;
+ UINT16 VGACommand;
//
// Snoop attribute can be only modified by GFX
@@ -1428,11 +1439,11 @@ SupportPaletteSnoopAttributes ( //
return EFI_SUCCESS;
}
+
//
// Check if they are on the same bus
//
if (Temp->Parent == PciIoDevice->Parent) {
-
PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);
//
@@ -1474,7 +1485,6 @@ SupportPaletteSnoopAttributes ( } else {
return EFI_UNSUPPORTED;
}
-
} else {
//
// GFX should be set to snoop
@@ -1485,7 +1495,6 @@ SupportPaletteSnoopAttributes ( } else {
return EFI_UNSUPPORTED;
}
-
}
return EFI_SUCCESS;
@@ -1513,72 +1522,73 @@ SupportPaletteSnoopAttributes ( EFI_STATUS
EFIAPI
PciIoAttributes (
- IN EFI_PCI_IO_PROTOCOL * This,
+ IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
IN UINT64 Attributes,
OUT UINT64 *Result OPTIONAL
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
- PCI_IO_DEVICE *UpStreamBridge;
- PCI_IO_DEVICE *Temp;
+ PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *UpStreamBridge;
+ PCI_IO_DEVICE *Temp;
- UINT64 Supports;
- UINT64 UpStreamAttributes;
- UINT16 BridgeControl;
- UINT16 Command;
+ UINT64 Supports;
+ UINT64 UpStreamAttributes;
+ UINT16 BridgeControl;
+ UINT16 Command;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
switch (Operation) {
- case EfiPciIoAttributeOperationGet:
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
+ case EfiPciIoAttributeOperationGet:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
- *Result = PciIoDevice->Attributes;
- return EFI_SUCCESS;
+ *Result = PciIoDevice->Attributes;
+ return EFI_SUCCESS;
- case EfiPciIoAttributeOperationSupported:
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
+ case EfiPciIoAttributeOperationSupported:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
- *Result = PciIoDevice->Supports;
- return EFI_SUCCESS;
+ *Result = PciIoDevice->Supports;
+ return EFI_SUCCESS;
- case EfiPciIoAttributeOperationSet:
- Status = PciIoDevice->PciIo.Attributes (
- &(PciIoDevice->PciIo),
- EfiPciIoAttributeOperationEnable,
- Attributes,
- NULL
- );
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
+ case EfiPciIoAttributeOperationSet:
+ Status = PciIoDevice->PciIo.Attributes (
+ &(PciIoDevice->PciIo),
+ EfiPciIoAttributeOperationEnable,
+ Attributes,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_UNSUPPORTED;
+ }
- Status = PciIoDevice->PciIo.Attributes (
- &(PciIoDevice->PciIo),
- EfiPciIoAttributeOperationDisable,
- (~Attributes) & (PciIoDevice->Supports),
- NULL
- );
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
+ Status = PciIoDevice->PciIo.Attributes (
+ &(PciIoDevice->PciIo),
+ EfiPciIoAttributeOperationDisable,
+ (~Attributes) & (PciIoDevice->Supports),
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_UNSUPPORTED;
+ }
- return EFI_SUCCESS;
+ return EFI_SUCCESS;
- case EfiPciIoAttributeOperationEnable:
- case EfiPciIoAttributeOperationDisable:
- break;
+ case EfiPciIoAttributeOperationEnable:
+ case EfiPciIoAttributeOperationDisable:
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
+
//
// Just a trick for ENABLE attribute
// EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.
@@ -1631,7 +1641,6 @@ PciIoAttributes ( // For PPB & P2C, set relevant attribute bits
//
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
-
if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;
}
@@ -1647,16 +1656,16 @@ PciIoAttributes ( if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;
}
-
} else {
//
// Do with the attributes on VGA
// Only for VGA's legacy resource, we just can enable once.
//
if ((Attributes &
- (EFI_PCI_IO_ATTRIBUTE_VGA_IO |
- EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
- EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {
+ (EFI_PCI_IO_ATTRIBUTE_VGA_IO |
+ EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
+ EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0)
+ {
//
// Check if a VGA has been enabled before enabling a new one
//
@@ -1665,7 +1674,7 @@ PciIoAttributes ( // Check if there have been an active VGA device on the same Host Bridge
//
Temp = LocateVgaDeviceOnHostBridge (PciIoDevice->PciRootBridgeIo->ParentHandle);
- if (Temp != NULL && Temp != PciIoDevice) {
+ if ((Temp != NULL) && (Temp != PciIoDevice)) {
//
// An active VGA has been detected, so can not enable another
//
@@ -1678,7 +1687,6 @@ PciIoAttributes ( // Do with the attributes on GFX
//
if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
-
if (Operation == EfiPciIoAttributeOperationEnable) {
//
// Check if snoop can be enabled in current configuration
@@ -1686,7 +1694,6 @@ PciIoAttributes ( Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);
if (EFI_ERROR (Status)) {
-
//
// Enable operation is forbidden, so mask the bit in attributes
// so as to keep consistent with the actual Status
@@ -1696,7 +1703,6 @@ PciIoAttributes ( //
//
return EFI_UNSUPPORTED;
-
}
}
@@ -1718,6 +1724,7 @@ PciIoAttributes ( if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
Command |= EFI_PCI_COMMAND_BUS_MASTER;
}
+
//
// The upstream bridge should be also set to relevant attribute
// expect for IO, Mem and BusMaster
@@ -1727,7 +1734,7 @@ PciIoAttributes ( EFI_PCI_IO_ATTRIBUTE_MEMORY |
EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
)
- );
+ );
UpStreamBridge = PciIoDevice->Parent;
if (Operation == EfiPciIoAttributeOperationEnable) {
@@ -1745,13 +1752,12 @@ PciIoAttributes ( // Enable attributes of the upstream bridge
//
Status = UpStreamBridge->PciIo.Attributes (
- &(UpStreamBridge->PciIo),
- EfiPciIoAttributeOperationEnable,
- UpStreamAttributes,
- NULL
- );
+ &(UpStreamBridge->PciIo),
+ EfiPciIoAttributeOperationEnable,
+ UpStreamAttributes,
+ NULL
+ );
} else {
-
//
// Disable relevant attributes to command register and bridge control register
//
@@ -1761,8 +1767,7 @@ PciIoAttributes ( }
PciIoDevice->Attributes &= (~Attributes);
- Status = EFI_SUCCESS;
-
+ Status = EFI_SUCCESS;
}
if (EFI_ERROR (Status)) {
@@ -1790,20 +1795,20 @@ PciIoAttributes ( **/
UINT64
GetMmioAddressTranslationOffset (
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo,
- UINT64 AddrRangeMin,
- UINT64 AddrLen
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo,
+ UINT64 AddrRangeMin,
+ UINT64 AddrLen
)
{
- EFI_STATUS Status;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
+ EFI_STATUS Status;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
Status = RootBridgeIo->Configuration (
RootBridgeIo,
- (VOID **) &Configuration
+ (VOID **)&Configuration
);
if (EFI_ERROR (Status)) {
- return (UINT64) -1;
+ return (UINT64)-1;
}
// According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration()
@@ -1814,9 +1819,11 @@ GetMmioAddressTranslationOffset ( if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&
(Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) &&
(Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen)
- ) {
+ )
+ {
return Configuration->AddrTranslationOffset;
}
+
Configuration++;
}
@@ -1824,7 +1831,7 @@ GetMmioAddressTranslationOffset ( // The resource occupied by BAR should be in the range reported by RootBridge.
//
ASSERT (FALSE);
- return (UINT64) -1;
+ return (UINT64)-1;
}
/**
@@ -1852,19 +1859,19 @@ GetMmioAddressTranslationOffset ( EFI_STATUS
EFIAPI
PciIoGetBarAttributes (
- IN EFI_PCI_IO_PROTOCOL * This,
- IN UINT8 BarIndex,
- OUT UINT64 *Supports OPTIONAL,
- OUT VOID **Resources OPTIONAL
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports OPTIONAL,
+ OUT VOID **Resources OPTIONAL
)
{
- PCI_IO_DEVICE *PciIoDevice;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ PCI_IO_DEVICE *PciIoDevice;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
- if (Supports == NULL && Resources == NULL) {
+ if ((Supports == NULL) && (Resources == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -1886,69 +1893,69 @@ PciIoGetBarAttributes ( return EFI_OUT_OF_RESOURCES;
}
- *Resources = Descriptor;
+ *Resources = Descriptor;
Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Descriptor->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
+ Descriptor->Len = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
Descriptor->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
Descriptor->AddrLen = PciIoDevice->PciBar[BarIndex].Length;
Descriptor->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
switch (PciIoDevice->PciBar[BarIndex].BarType) {
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- //
- // Io
- //
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
- break;
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ //
+ // Io
+ //
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ break;
- case PciBarTypePMem32:
- //
- // prefetchable
- //
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case PciBarTypePMem32:
+ //
+ // prefetchable
+ //
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
//
// Fall through
//
- case PciBarTypeMem32:
- //
- // Mem
- //
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- //
- // 32 bit
- //
- Descriptor->AddrSpaceGranularity = 32;
- break;
+ case PciBarTypeMem32:
+ //
+ // Mem
+ //
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ //
+ // 32 bit
+ //
+ Descriptor->AddrSpaceGranularity = 32;
+ break;
- case PciBarTypePMem64:
- //
- // prefetchable
- //
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case PciBarTypePMem64:
+ //
+ // prefetchable
+ //
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
//
// Fall through
//
- case PciBarTypeMem64:
- //
- // Mem
- //
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- //
- // 64 bit
- //
- Descriptor->AddrSpaceGranularity = 64;
- break;
+ case PciBarTypeMem64:
+ //
+ // Mem
+ //
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ //
+ // 64 bit
+ //
+ Descriptor->AddrSpaceGranularity = 64;
+ break;
- default:
- break;
+ default:
+ break;
}
//
// put the checksum
//
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);
End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0;
@@ -1961,7 +1968,7 @@ PciIoGetBarAttributes ( Descriptor->AddrRangeMin,
Descriptor->AddrLen
);
- if (Descriptor->AddrTranslationOffset == (UINT64) -1) {
+ if (Descriptor->AddrTranslationOffset == (UINT64)-1) {
FreePool (Descriptor);
return EFI_UNSUPPORTED;
}
@@ -2002,30 +2009,31 @@ PciIoGetBarAttributes ( EFI_STATUS
EFIAPI
PciIoSetBarAttributes (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINT64 Attributes,
- IN UINT8 BarIndex,
- IN OUT UINT64 *Offset,
- IN OUT UINT64 *Length
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
)
{
- EFI_STATUS Status;
- PCI_IO_DEVICE *PciIoDevice;
- UINT64 NonRelativeOffset;
- UINT64 Supports;
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
+ UINT64 NonRelativeOffset;
+ UINT64 Supports;
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
//
// Make sure Offset and Length are not NULL
//
- if (Offset == NULL || Length == NULL) {
+ if ((Offset == NULL) || (Length == NULL)) {
return EFI_INVALID_PARAMETER;
}
if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {
return EFI_UNSUPPORTED;
}
+
//
// This driver does not support setting the WRITE_COMBINE or the CACHED attributes.
// If Attributes is not 0, then return EFI_UNSUPPORTED.
@@ -2035,19 +2043,20 @@ PciIoSetBarAttributes ( if (Attributes != (Attributes & Supports)) {
return EFI_UNSUPPORTED;
}
+
//
// Attributes must be supported. Make sure the BAR range described by BarIndex, Offset, and
// Length are valid for this PCI device.
//
NonRelativeOffset = *Offset;
- Status = PciIoVerifyBarAccess (
- PciIoDevice,
- BarIndex,
- PciBarTypeMem,
- EfiPciIoWidthUint8,
- (UINT32) *Length,
- &NonRelativeOffset
- );
+ Status = PciIoVerifyBarAccess (
+ PciIoDevice,
+ BarIndex,
+ PciBarTypeMem,
+ EfiPciIoWidthUint8,
+ (UINT32)*Length,
+ &NonRelativeOffset
+ );
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
@@ -2055,7 +2064,6 @@ PciIoSetBarAttributes ( return EFI_SUCCESS;
}
-
/**
Test whether two Pci devices has same parent bridge.
@@ -2068,12 +2076,12 @@ PciIoSetBarAttributes ( **/
BOOLEAN
PciDevicesOnTheSamePath (
- IN PCI_IO_DEVICE *PciDevice1,
- IN PCI_IO_DEVICE *PciDevice2
+ IN PCI_IO_DEVICE *PciDevice1,
+ IN PCI_IO_DEVICE *PciDevice2
)
{
- BOOLEAN Existed1;
- BOOLEAN Existed2;
+ BOOLEAN Existed1;
+ BOOLEAN Existed2;
if (PciDevice1->Parent == PciDevice2->Parent) {
return TRUE;
@@ -2082,5 +2090,5 @@ PciDevicesOnTheSamePath ( Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);
Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);
- return (BOOLEAN) (Existed1 || Existed2);
+ return (BOOLEAN)(Existed1 || Existed2);
}
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h index 5de6222f93..a73bd06bcf 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h @@ -17,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
InitializePciIoInstance (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -37,12 +37,12 @@ InitializePciIoInstance ( **/
EFI_STATUS
PciIoVerifyBarAccess (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT8 BarIndex,
- IN PCI_BAR_TYPE Type,
- IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN IN UINTN Count,
- IN UINT64 *Offset
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT8 BarIndex,
+ IN PCI_BAR_TYPE Type,
+ IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN IN UINTN Count,
+ IN UINT64 *Offset
);
/**
@@ -347,13 +347,13 @@ PciIoConfigWrite ( EFI_STATUS
EFIAPI
PciIoCopyMem (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
- IN UINT8 DestBarIndex,
- IN UINT64 DestOffset,
- IN UINT8 SrcBarIndex,
- IN UINT64 SrcOffset,
- IN UINTN Count
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
);
/**
@@ -426,12 +426,12 @@ PciIoUnmap ( EFI_STATUS
EFIAPI
PciIoAllocateBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
);
/**
@@ -449,9 +449,9 @@ PciIoAllocateBuffer ( EFI_STATUS
EFIAPI
PciIoFreeBuffer (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINTN Pages,
- IN VOID *HostAddress
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
);
/**
@@ -508,9 +508,9 @@ PciIoGetLocation ( **/
BOOLEAN
CheckBarType (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT8 BarIndex,
- IN PCI_BAR_TYPE BarType
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT8 BarIndex,
+ IN PCI_BAR_TYPE BarType
);
/**
@@ -569,7 +569,7 @@ SupportPaletteSnoopAttributes ( EFI_STATUS
EFIAPI
PciIoAttributes (
- IN EFI_PCI_IO_PROTOCOL * This,
+ IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
IN UINT64 Attributes,
OUT UINT64 *Result OPTIONAL
@@ -600,10 +600,10 @@ PciIoAttributes ( EFI_STATUS
EFIAPI
PciIoGetBarAttributes (
- IN EFI_PCI_IO_PROTOCOL * This,
- IN UINT8 BarIndex,
- OUT UINT64 *Supports OPTIONAL,
- OUT VOID **Resources OPTIONAL
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports OPTIONAL,
+ OUT VOID **Resources OPTIONAL
);
/**
@@ -633,14 +633,13 @@ PciIoGetBarAttributes ( EFI_STATUS
EFIAPI
PciIoSetBarAttributes (
- IN EFI_PCI_IO_PROTOCOL *This,
- IN UINT64 Attributes,
- IN UINT8 BarIndex,
- IN OUT UINT64 *Offset,
- IN OUT UINT64 *Length
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
);
-
/**
Test whether two Pci devices has same parent bridge.
@@ -653,8 +652,8 @@ PciIoSetBarAttributes ( **/
BOOLEAN
PciDevicesOnTheSamePath (
- IN PCI_IO_DEVICE *PciDevice1,
- IN PCI_IO_DEVICE *PciDevice2
+ IN PCI_IO_DEVICE *PciDevice1,
+ IN PCI_IO_DEVICE *PciDevice2
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c index 0ad1dfa526..63d149b3b8 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciBus.h"
GLOBAL_REMOVE_IF_UNREFERENCED
-CHAR16 *mBarTypeStr[] = {
+CHAR16 *mBarTypeStr[] = {
L"Unknow",
L" Io16",
L" Io32",
@@ -22,7 +22,7 @@ CHAR16 *mBarTypeStr[] = { L" Io",
L" Mem",
L"Unknow"
- };
+};
/**
Retrieve the max bus number that is assigned to the Root Bridge hierarchy.
@@ -35,7 +35,7 @@ CHAR16 *mBarTypeStr[] = { **/
UINT16
PciGetMaxBusNumber (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
)
{
PCI_IO_DEVICE *RootBridge;
@@ -49,6 +49,7 @@ PciGetMaxBusNumber ( while (RootBridge->Parent != NULL) {
RootBridge = RootBridge->Parent;
}
+
MaxNumberInRange = 0;
//
// Iterate the bus number ranges to get max PCI bus number
@@ -58,7 +59,8 @@ PciGetMaxBusNumber ( MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
BusNumberRanges++;
}
- return (UINT16) MaxNumberInRange;
+
+ return (UINT16)MaxNumberInRange;
}
/**
@@ -69,7 +71,7 @@ PciGetMaxBusNumber ( **/
VOID
GetBackPcCardBar (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
UINT32 Address;
@@ -91,9 +93,9 @@ GetBackPcCardBar ( &Address
);
- (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);
- (PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;
- (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;
+ (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64)(Address);
+ (PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;
+ (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;
Address = 0;
PciIoDevice->PciIo.Pci.Read (
@@ -103,9 +105,9 @@ GetBackPcCardBar ( 1,
&Address
);
- (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);
- (PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;
- (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;
+ (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64)(Address);
+ (PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;
+ (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;
Address = 0;
PciIoDevice->PciIo.Pci.Read (
@@ -115,7 +117,7 @@ GetBackPcCardBar ( 1,
&Address
);
- (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);
+ (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64)(Address);
(PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;
(PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;
@@ -127,13 +129,12 @@ GetBackPcCardBar ( 1,
&Address
);
- (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);
+ (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64)(Address);
(PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;
(PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;
-
}
- if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
+ if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
GetResourcePaddingForHpb (PciIoDevice);
}
}
@@ -148,13 +149,13 @@ GetBackPcCardBar ( **/
VOID
RemoveRejectedPciDevices (
- IN EFI_HANDLE RootBridgeHandle,
- IN PCI_IO_DEVICE *Bridge
+ IN EFI_HANDLE RootBridgeHandle,
+ IN PCI_IO_DEVICE *Bridge
)
{
- PCI_IO_DEVICE *Temp;
- LIST_ENTRY *CurrentLink;
- LIST_ENTRY *LastLink;
+ PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
+ LIST_ENTRY *LastLink;
if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
return;
@@ -163,7 +164,6 @@ RemoveRejectedPciDevices ( CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
-
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (IS_PCI_BRIDGE (&Temp->Pci)) {
@@ -176,7 +176,6 @@ RemoveRejectedPciDevices ( // Skip rejection for all PPBs, while detect rejection for others
//
if (IsPciDeviceRejected (Temp)) {
-
//
// For P2C, remove all devices on it
//
@@ -206,41 +205,49 @@ RemoveRejectedPciDevices ( **/
VOID
DumpBridgeResource (
- IN PCI_RESOURCE_NODE *BridgeResource
+ IN PCI_RESOURCE_NODE *BridgeResource
)
{
- LIST_ENTRY *Link;
- PCI_RESOURCE_NODE *Resource;
- PCI_BAR *Bar;
+ LIST_ENTRY *Link;
+ PCI_RESOURCE_NODE *Resource;
+ PCI_BAR *Bar;
if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
DEBUG ((
- DEBUG_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
+ DEBUG_INFO,
+ "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
- BridgeResource->Length, BridgeResource->Alignment
+ BridgeResource->Length,
+ BridgeResource->Alignment
));
for ( Link = GetFirstNode (&BridgeResource->ChildList)
- ; !IsNull (&BridgeResource->ChildList, Link)
- ; Link = GetNextNode (&BridgeResource->ChildList, Link)
- ) {
+ ; !IsNull (&BridgeResource->ChildList, Link)
+ ; Link = GetNextNode (&BridgeResource->ChildList, Link)
+ )
+ {
Resource = RESOURCE_NODE_FROM_LINK (Link);
if (Resource->ResourceUsage == PciResUsageTypical) {
Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
DEBUG ((
- DEBUG_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s [%02x|%02x|%02x:",
- Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
+ DEBUG_INFO,
+ " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s [%02x|%02x|%02x:",
+ Bar[Resource->Bar].BaseAddress,
+ Resource->Length,
+ Resource->Alignment,
IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :
- L"PCI",
- Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
+ L"PCI",
+ Resource->PciDev->BusNumber,
+ Resource->PciDev->DeviceNumber,
Resource->PciDev->FunctionNumber
));
if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||
(IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||
(IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))
- ) {
+ )
+ {
//
// The resource requirement comes from the device itself.
//
@@ -254,9 +261,11 @@ DumpBridgeResource ( } else {
DEBUG ((DEBUG_INFO, " Base = Padding;\tLength = 0x%lx;\tAlignment = 0x%lx", Resource->Length, Resource->Alignment));
}
+
if (BridgeResource->ResType != Resource->ResType) {
DEBUG ((DEBUG_INFO, "; Type = %s", mBarTypeStr[MIN (Resource->ResType, PciBarTypeMaxType)]));
}
+
DEBUG ((DEBUG_INFO, "\n"));
}
}
@@ -273,25 +282,27 @@ DumpBridgeResource ( **/
UINTN
FindResourceNode (
- IN PCI_IO_DEVICE *Device,
- IN PCI_RESOURCE_NODE *BridgeResource,
- OUT PCI_RESOURCE_NODE **DeviceResources OPTIONAL
+ IN PCI_IO_DEVICE *Device,
+ IN PCI_RESOURCE_NODE *BridgeResource,
+ OUT PCI_RESOURCE_NODE **DeviceResources OPTIONAL
)
{
- LIST_ENTRY *Link;
- PCI_RESOURCE_NODE *Resource;
- UINTN Count;
+ LIST_ENTRY *Link;
+ PCI_RESOURCE_NODE *Resource;
+ UINTN Count;
Count = 0;
for ( Link = BridgeResource->ChildList.ForwardLink
- ; Link != &BridgeResource->ChildList
- ; Link = Link->ForwardLink
- ) {
+ ; Link != &BridgeResource->ChildList
+ ; Link = Link->ForwardLink
+ )
+ {
Resource = RESOURCE_NODE_FROM_LINK (Link);
if (Resource->PciDev == Device) {
if (DeviceResources != NULL) {
DeviceResources[Count] = Resource;
}
+
Count++;
}
}
@@ -308,18 +319,18 @@ FindResourceNode ( **/
VOID
DumpResourceMap (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_RESOURCE_NODE **Resources,
- IN UINTN ResourceCount
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_RESOURCE_NODE **Resources,
+ IN UINTN ResourceCount
)
{
- EFI_STATUS Status;
- LIST_ENTRY *Link;
- PCI_IO_DEVICE *Device;
- UINTN Index;
- CHAR16 *Str;
- PCI_RESOURCE_NODE **ChildResources;
- UINTN ChildResourceCount;
+ EFI_STATUS Status;
+ LIST_ENTRY *Link;
+ PCI_IO_DEVICE *Device;
+ UINTN Index;
+ CHAR16 *Str;
+ PCI_RESOURCE_NODE **ChildResources;
+ UINTN ChildResourceCount;
DEBUG ((DEBUG_INFO, "PciBus: Resource Map for "));
@@ -333,8 +344,11 @@ DumpResourceMap ( );
if (EFI_ERROR (Status)) {
DEBUG ((
- DEBUG_INFO, "Bridge [%02x|%02x|%02x]\n",
- Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber
+ DEBUG_INFO,
+ "Bridge [%02x|%02x|%02x]\n",
+ Bridge->BusNumber,
+ Bridge->DeviceNumber,
+ Bridge->FunctionNumber
));
} else {
Str = ConvertDevicePathToText (
@@ -351,19 +365,21 @@ DumpResourceMap ( for (Index = 0; Index < ResourceCount; Index++) {
DumpBridgeResource (Resources[Index]);
}
+
DEBUG ((DEBUG_INFO, "\n"));
for ( Link = Bridge->ChildList.ForwardLink
- ; Link != &Bridge->ChildList
- ; Link = Link->ForwardLink
- ) {
+ ; Link != &Bridge->ChildList
+ ; Link = Link->ForwardLink
+ )
+ {
Device = PCI_IO_DEVICE_FROM_LINK (Link);
if (IS_PCI_BRIDGE (&Device->Pci)) {
-
ChildResourceCount = 0;
for (Index = 0; Index < ResourceCount; Index++) {
ChildResourceCount += FindResourceNode (Device, Resources[Index], NULL);
}
+
ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * ChildResourceCount);
ASSERT (ChildResources != NULL);
ChildResourceCount = 0;
@@ -387,14 +403,14 @@ DumpResourceMap ( **/
BOOLEAN
AdjustPciDeviceBarSize (
- IN PCI_IO_DEVICE *RootBridgeDev
+ IN PCI_IO_DEVICE *RootBridgeDev
)
{
- PCI_IO_DEVICE *PciIoDevice;
- LIST_ENTRY *CurrentLink;
- BOOLEAN Adjusted;
- UINTN Offset;
- UINTN BarIndex;
+ PCI_IO_DEVICE *PciIoDevice;
+ LIST_ENTRY *CurrentLink;
+ BOOLEAN Adjusted;
+ UINTN Offset;
+ UINTN BarIndex;
Adjusted = FALSE;
CurrentLink = RootBridgeDev->ChildList.ForwardLink;
@@ -411,7 +427,9 @@ AdjustPciDeviceBarSize ( DEBUG ((
DEBUG_ERROR,
"PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar Size\n",
- PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber
+ PciIoDevice->BusNumber,
+ PciIoDevice->DeviceNumber,
+ PciIoDevice->FunctionNumber
));
PciProgramResizableBar (PciIoDevice, PciResizableBarMin);
//
@@ -420,8 +438,11 @@ AdjustPciDeviceBarSize ( for (Offset = 0x10, BarIndex = 0; Offset <= 0x24 && BarIndex < PCI_MAX_BAR; BarIndex++) {
Offset = PciParseBar (PciIoDevice, Offset, BarIndex);
}
+
Adjusted = TRUE;
- DEBUG_CODE (DumpPciBars (PciIoDevice););
+ DEBUG_CODE (
+ DumpPciBars (PciIoDevice);
+ );
}
}
@@ -446,7 +467,7 @@ AdjustPciDeviceBarSize ( **/
EFI_STATUS
PciHostBridgeResourceAllocator (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
)
{
PCI_IO_DEVICE *RootBridgeDev;
@@ -494,8 +515,8 @@ PciHostBridgeResourceAllocator ( InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);
InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);
- RootBridgeDev = NULL;
- RootBridgeHandle = 0;
+ RootBridgeDev = NULL;
+ RootBridgeHandle = 0;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
//
@@ -519,7 +540,7 @@ PciHostBridgeResourceAllocator ( IoBridge = CreateResourceNode (
RootBridgeDev,
0,
- FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,
+ FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF : 0xFFF,
RB_IO_RANGE,
PciBarTypeIo16,
PciResUsageTypical
@@ -645,6 +666,7 @@ PciHostBridgeResourceAllocator ( return Status;
}
}
+
//
// End while, at least one Root Bridge should be found.
//
@@ -665,6 +687,7 @@ PciHostBridgeResourceAllocator ( //
return EFI_OUT_OF_RESOURCES;
}
+
//
// Allocation succeed.
// Get host bridge handle for status report, and then skip the main while
@@ -672,7 +695,6 @@ PciHostBridgeResourceAllocator ( HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;
break;
-
} else {
//
// If Hot Plug is supported
@@ -688,14 +710,14 @@ PciHostBridgeResourceAllocator ( // If the resource allocation is unsuccessful, free resources on bridge
//
- RootBridgeDev = NULL;
- RootBridgeHandle = 0;
+ RootBridgeDev = NULL;
+ RootBridgeHandle = 0;
- IoResStatus = EFI_RESOURCE_SATISFIED;
- Mem32ResStatus = EFI_RESOURCE_SATISFIED;
- PMem32ResStatus = EFI_RESOURCE_SATISFIED;
- Mem64ResStatus = EFI_RESOURCE_SATISFIED;
- PMem64ResStatus = EFI_RESOURCE_SATISFIED;
+ IoResStatus = EFI_RESOURCE_SATISFIED;
+ Mem32ResStatus = EFI_RESOURCE_SATISFIED;
+ PMem32ResStatus = EFI_RESOURCE_SATISFIED;
+ Mem64ResStatus = EFI_RESOURCE_SATISFIED;
+ PMem64ResStatus = EFI_RESOURCE_SATISFIED;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
//
@@ -741,6 +763,7 @@ PciHostBridgeResourceAllocator ( FreePool (AcpiConfig);
}
}
+
//
// End while
//
@@ -755,36 +778,38 @@ PciHostBridgeResourceAllocator ( ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
- EFI_PROGRESS_CODE,
- EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
- (VOID *) &AllocFailExtendedData,
- sizeof (AllocFailExtendedData)
- );
+ EFI_PROGRESS_CODE,
+ EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
+ (VOID *)&AllocFailExtendedData,
+ sizeof (AllocFailExtendedData)
+ );
- //
- // When resource conflict happens, adjust the BAR size first.
- // Only when adjusting BAR size doesn't help or BAR size cannot be adjusted,
- // reject the device who requests largest resource that causes conflict.
- //
+ //
+ // When resource conflict happens, adjust the BAR size first.
+ // Only when adjusting BAR size doesn't help or BAR size cannot be adjusted,
+ // reject the device who requests largest resource that causes conflict.
+ //
ResizableBarAdjusted = FALSE;
if (ResizableBarNeedAdjust) {
- ResizableBarAdjusted = AdjustPciDeviceBarSize (RootBridgeDev);
+ ResizableBarAdjusted = AdjustPciDeviceBarSize (RootBridgeDev);
ResizableBarNeedAdjust = FALSE;
}
+
if (!ResizableBarAdjusted) {
Status = PciHostBridgeAdjustAllocation (
- &IoPool,
- &Mem32Pool,
- &PMem32Pool,
- &Mem64Pool,
- &PMem64Pool,
- IoResStatus,
- Mem32ResStatus,
- PMem32ResStatus,
- Mem64ResStatus,
- PMem64ResStatus
- );
+ &IoPool,
+ &Mem32Pool,
+ &PMem32Pool,
+ &Mem64Pool,
+ &PMem64Pool,
+ IoResStatus,
+ Mem32ResStatus,
+ PMem32ResStatus,
+ Mem64ResStatus,
+ PMem64ResStatus
+ );
}
+
//
// Destroy all the resource tree
//
@@ -801,6 +826,7 @@ PciHostBridgeResourceAllocator ( }
}
}
+
//
// End main while
//
@@ -809,11 +835,11 @@ PciHostBridgeResourceAllocator ( // Raise the EFI_IOB_PCI_RES_ALLOC status code
//
REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
- EFI_PROGRESS_CODE,
- EFI_IO_BUS_PCI | EFI_IOB_PCI_RES_ALLOC,
- (VOID *) &HandleExtendedData,
- sizeof (HandleExtendedData)
- );
+ EFI_PROGRESS_CODE,
+ EFI_IO_BUS_PCI | EFI_IOB_PCI_RES_ALLOC,
+ (VOID *)&HandleExtendedData,
+ sizeof (HandleExtendedData)
+ );
//
// Notify pci bus driver starts to program the resource
@@ -824,9 +850,9 @@ PciHostBridgeResourceAllocator ( return Status;
}
- RootBridgeDev = NULL;
+ RootBridgeDev = NULL;
- RootBridgeHandle = 0;
+ RootBridgeHandle = 0;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
//
@@ -842,11 +868,11 @@ PciHostBridgeResourceAllocator ( // Get acpi resource node for all the resource types
//
AcpiConfig = NULL;
- Status = PciResAlloc->GetProposedResources (
- PciResAlloc,
- RootBridgeDev->Handle,
- &AcpiConfig
- );
+ Status = PciResAlloc->GetProposedResources (
+ PciResAlloc,
+ RootBridgeDev->Handle,
+ &AcpiConfig
+ );
if (EFI_ERROR (Status)) {
return Status;
@@ -930,15 +956,17 @@ PciHostBridgeResourceAllocator ( // The original value is programmed by ProgramResource() above.
//
DEBUG ((
- DEBUG_INFO, "Process Option ROM: BAR Base/Length = %lx/%lx\n",
- RootBridgeDev->PciBar[0].BaseAddress, RootBridgeDev->PciBar[0].Length
+ DEBUG_INFO,
+ "Process Option ROM: BAR Base/Length = %lx/%lx\n",
+ RootBridgeDev->PciBar[0].BaseAddress,
+ RootBridgeDev->PciBar[0].Length
));
ProcessOptionRom (RootBridgeDev, RootBridgeDev->PciBar[0].BaseAddress, RootBridgeDev->PciBar[0].Length);
- IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;
- Mem32Bridge ->PciDev->PciBar[Mem32Bridge ->Bar].BaseAddress = Mem32Base;
+ IoBridge->PciDev->PciBar[IoBridge->Bar].BaseAddress = IoBase;
+ Mem32Bridge->PciDev->PciBar[Mem32Bridge->Bar].BaseAddress = Mem32Base;
PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;
- Mem64Bridge ->PciDev->PciBar[Mem64Bridge ->Bar].BaseAddress = Mem64Base;
+ Mem64Bridge->PciDev->PciBar[Mem64Bridge->Bar].BaseAddress = Mem64Base;
PMem64Bridge->PciDev->PciBar[PMem64Bridge->Bar].BaseAddress = PMem64Base;
//
@@ -952,7 +980,7 @@ PciHostBridgeResourceAllocator ( Resources[3] = Mem64Bridge;
Resources[4] = PMem64Bridge;
DumpResourceMap (RootBridgeDev, Resources, ARRAY_SIZE (Resources));
- );
+ );
FreePool (AcpiConfig);
}
@@ -989,10 +1017,10 @@ PciHostBridgeResourceAllocator ( **/
EFI_STATUS
PciAllocateBusNumber (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber,
- IN UINT8 NumberOfBuses,
- OUT UINT8 *NextBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber,
+ IN UINT8 NumberOfBuses,
+ OUT UINT8 *NextBusNumber
)
{
PCI_IO_DEVICE *RootBridge;
@@ -1014,21 +1042,25 @@ PciAllocateBusNumber ( BusNumberRanges = RootBridge->BusNumberRanges;
while (BusNumberRanges->Desc != ACPI_END_TAG_DESCRIPTOR) {
MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
- if (StartBusNumber >= BusNumberRanges->AddrRangeMin && StartBusNumber <= MaxNumberInRange) {
+ if ((StartBusNumber >= BusNumberRanges->AddrRangeMin) && (StartBusNumber <= MaxNumberInRange)) {
NextNumber = (UINT8)(StartBusNumber + NumberOfBuses);
while (NextNumber > MaxNumberInRange) {
++BusNumberRanges;
if (BusNumberRanges->Desc == ACPI_END_TAG_DESCRIPTOR) {
return EFI_OUT_OF_RESOURCES;
}
- NextNumber = (UINT8)(NextNumber + (BusNumberRanges->AddrRangeMin - (MaxNumberInRange + 1)));
+
+ NextNumber = (UINT8)(NextNumber + (BusNumberRanges->AddrRangeMin - (MaxNumberInRange + 1)));
MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
}
+
*NextBusNumber = NextNumber;
return EFI_SUCCESS;
}
+
BusNumberRanges++;
}
+
return EFI_OUT_OF_RESOURCES;
}
@@ -1048,38 +1080,38 @@ PciAllocateBusNumber ( **/
EFI_STATUS
PciScanBus (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber,
- OUT UINT8 *SubBusNumber,
- OUT UINT8 *PaddedBusRange
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber,
+ OUT UINT8 *SubBusNumber,
+ OUT UINT8 *PaddedBusRange
)
{
- EFI_STATUS Status;
- PCI_TYPE00 Pci;
- UINT8 Device;
- UINT8 Func;
- UINT64 Address;
- UINT8 SecondBus;
- UINT8 PaddedSubBus;
- UINT16 Register;
- UINTN HpIndex;
- PCI_IO_DEVICE *PciDevice;
- EFI_EVENT Event;
- EFI_HPC_STATE State;
- UINT64 PciAddress;
- EFI_HPC_PADDING_ATTRIBUTES Attributes;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *NextDescriptors;
- UINT16 BusRange;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- BOOLEAN BusPadding;
- UINT32 TempReservedBusNum;
+ EFI_STATUS Status;
+ PCI_TYPE00 Pci;
+ UINT8 Device;
+ UINT8 Func;
+ UINT64 Address;
+ UINT8 SecondBus;
+ UINT8 PaddedSubBus;
+ UINT16 Register;
+ UINTN HpIndex;
+ PCI_IO_DEVICE *PciDevice;
+ EFI_EVENT Event;
+ EFI_HPC_STATE State;
+ UINT64 PciAddress;
+ EFI_HPC_PADDING_ATTRIBUTES Attributes;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *NextDescriptors;
+ UINT16 BusRange;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ BOOLEAN BusPadding;
+ UINT32 TempReservedBusNum;
PciRootBridgeIo = Bridge->PciRootBridgeIo;
SecondBus = 0;
Register = 0;
State = 0;
- Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;
+ Attributes = (EFI_HPC_PADDING_ATTRIBUTES)0;
BusRange = 0;
BusPadding = FALSE;
PciDevice = NULL;
@@ -1088,19 +1120,18 @@ PciScanBus ( for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
TempReservedBusNum = 0;
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
-
//
// Check to see whether a pci device is present
//
Status = PciDevicePresent (
- PciRootBridgeIo,
- &Pci,
- StartBusNumber,
- Device,
- Func
- );
+ PciRootBridgeIo,
+ &Pci,
+ StartBusNumber,
+ Device,
+ Func
+ );
- if (EFI_ERROR (Status) && Func == 0) {
+ if (EFI_ERROR (Status) && (Func == 0)) {
//
// go to next device if there is no Function 0
//
@@ -1115,13 +1146,13 @@ PciScanBus ( // Get the PCI device information
//
Status = PciSearchDevice (
- Bridge,
- &Pci,
- StartBusNumber,
- Device,
- Func,
- &PciDevice
- );
+ Bridge,
+ &Pci,
+ StartBusNumber,
+ Device,
+ Func,
+ &PciDevice
+ );
if (EFI_ERROR (Status)) {
continue;
@@ -1136,12 +1167,12 @@ PciScanBus ( // EfiPciBeforeChildBusEnumeration for PCI Device Node
//
PreprocessController (
- PciDevice,
- PciDevice->BusNumber,
- PciDevice->DeviceNumber,
- PciDevice->FunctionNumber,
- EfiPciBeforeChildBusEnumeration
- );
+ PciDevice,
+ PciDevice->BusNumber,
+ PciDevice->DeviceNumber,
+ PciDevice->FunctionNumber,
+ EfiPciBeforeChildBusEnumeration
+ );
}
if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
@@ -1156,7 +1187,6 @@ PciScanBus ( gPciRootHpcData[HpIndex].Found = TRUE;
if (!gPciRootHpcData[HpIndex].Initialized) {
-
Status = CreateEventForHpc (HpIndex, &Event);
ASSERT (!EFI_ERROR (Status));
@@ -1175,7 +1205,7 @@ PciScanBus ( PciDevice->DeviceNumber,
PciDevice->FunctionNumber,
EfiPciBeforeChildBusEnumeration
- );
+ );
}
}
}
@@ -1192,9 +1222,7 @@ PciScanBus ( //
BusPadding = FALSE;
if (gPciHotPlugInit != NULL) {
-
if (IsPciHotPlugBus (PciDevice)) {
-
//
// If it is initialized, get the padded bus range
//
@@ -1203,7 +1231,7 @@ PciScanBus ( PciDevice->DevicePath,
PciAddress,
&State,
- (VOID **) &Descriptors,
+ (VOID **)&Descriptors,
&Attributes
);
@@ -1211,14 +1239,14 @@ PciScanBus ( return Status;
}
- BusRange = 0;
+ BusRange = 0;
NextDescriptors = Descriptors;
- Status = PciGetBusRange (
- &NextDescriptors,
- NULL,
- NULL,
- &BusRange
- );
+ Status = PciGetBusRange (
+ &NextDescriptors,
+ NULL,
+ NULL,
+ &BusRange
+ );
FreePool (Descriptors);
@@ -1238,10 +1266,11 @@ PciScanBus ( if (EFI_ERROR (Status)) {
return Status;
}
+
SecondBus = *SubBusNumber;
- Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);
+ Register = (UINT16)((SecondBus << 8) | (UINT16)StartBusNumber);
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
@@ -1251,25 +1280,23 @@ PciScanBus ( &Register
);
-
//
// If it is PPB, resursively search down this bridge
//
if (IS_PCI_BRIDGE (&Pci)) {
-
//
// Temporarily initialize SubBusNumber to maximum bus number to ensure the
// PCI configuration transaction to go through any PPB
//
- Register = PciGetMaxBusNumber (Bridge);
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
- Status = PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- EfiPciWidthUint8,
- Address,
- 1,
- &Register
- );
+ Register = PciGetMaxBusNumber (Bridge);
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+ Status = PciRootBridgeIo->Pci.Write (
+ PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &Register
+ );
//
// Nofify EfiPciBeforeChildBusEnumeration for PCI Brige
@@ -1283,11 +1310,11 @@ PciScanBus ( );
Status = PciScanBus (
- PciDevice,
- SecondBus,
- SubBusNumber,
- PaddedBusRange
- );
+ PciDevice,
+ SecondBus,
+ SubBusNumber,
+ PaddedBusRange
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1298,17 +1325,19 @@ PciScanBus ( // Ensure the device is enabled and initialized
//
if ((Attributes == EfiPaddingPciRootBridge) &&
- (State & EFI_HPC_STATE_ENABLED) != 0 &&
- (State & EFI_HPC_STATE_INITIALIZED) != 0) {
- *PaddedBusRange = (UINT8) ((UINT8) (BusRange) + *PaddedBusRange);
+ ((State & EFI_HPC_STATE_ENABLED) != 0) &&
+ ((State & EFI_HPC_STATE_INITIALIZED) != 0))
+ {
+ *PaddedBusRange = (UINT8)((UINT8)(BusRange) + *PaddedBusRange);
} else {
//
// Reserve the larger one between the actual occupied bus number and padded bus number
//
- Status = PciAllocateBusNumber (PciDevice, SecondBus, (UINT8) (BusRange), &PaddedSubBus);
+ Status = PciAllocateBusNumber (PciDevice, SecondBus, (UINT8)(BusRange), &PaddedSubBus);
if (EFI_ERROR (Status)) {
return Status;
}
+
*SubBusNumber = MAX (PaddedSubBus, *SubBusNumber);
}
}
@@ -1325,18 +1354,18 @@ PciScanBus ( 1,
SubBusNumber
);
- } else {
+ } else {
//
// It is device. Check PCI IOV for Bus reservation
// Go through each function, just reserve the MAX ReservedBusNum for one device
//
- if (PcdGetBool (PcdSrIovSupport) && PciDevice->SrIovCapabilityOffset != 0) {
+ if (PcdGetBool (PcdSrIovSupport) && (PciDevice->SrIovCapabilityOffset != 0)) {
if (TempReservedBusNum < PciDevice->ReservedBusNum) {
-
- Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8) (PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);
+ Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);
if (EFI_ERROR (Status)) {
return Status;
}
+
TempReservedBusNum = PciDevice->ReservedBusNum;
if (Func == 0) {
@@ -1348,8 +1377,7 @@ PciScanBus ( }
}
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
-
+ if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
//
// Skip sub functions, this is not a multi function device
//
@@ -1373,25 +1401,22 @@ PciScanBus ( **/
EFI_STATUS
PciRootBridgeP2CProcess (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
)
{
- LIST_ENTRY *CurrentLink;
- PCI_IO_DEVICE *Temp;
- EFI_HPC_STATE State;
- UINT64 PciAddress;
- EFI_STATUS Status;
+ LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
+ EFI_HPC_STATE State;
+ UINT64 PciAddress;
+ EFI_STATUS Status;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
-
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {
-
- if (gPciHotPlugInit != NULL && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
-
+ if ((gPciHotPlugInit != NULL) && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
//
// Raise the EFI_IOB_PCI_HPC_INIT status code
//
@@ -1402,13 +1427,13 @@ PciRootBridgeP2CProcess ( );
PciAddress = EFI_PCI_ADDRESS (Temp->BusNumber, Temp->DeviceNumber, Temp->FunctionNumber, 0);
- Status = gPciHotPlugInit->InitializeRootHpc (
- gPciHotPlugInit,
- Temp->DevicePath,
- PciAddress,
- NULL,
- &State
- );
+ Status = gPciHotPlugInit->InitializeRootHpc (
+ gPciHotPlugInit,
+ Temp->DevicePath,
+ PciAddress,
+ NULL,
+ &State
+ );
if (!EFI_ERROR (Status)) {
Status = PciBridgeEnumerator (Temp);
@@ -1420,7 +1445,6 @@ PciRootBridgeP2CProcess ( CurrentLink = CurrentLink->ForwardLink;
continue;
-
}
}
@@ -1446,12 +1470,12 @@ PciRootBridgeP2CProcess ( **/
EFI_STATUS
PciHostBridgeP2CProcess (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
)
{
- EFI_HANDLE RootBridgeHandle;
- PCI_IO_DEVICE *RootBridgeDev;
- EFI_STATUS Status;
+ EFI_HANDLE RootBridgeHandle;
+ PCI_IO_DEVICE *RootBridgeDev;
+ EFI_STATUS Status;
if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
return EFI_SUCCESS;
@@ -1460,7 +1484,6 @@ PciHostBridgeP2CProcess ( RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
-
//
// Get RootBridg Device by handle
//
@@ -1474,7 +1497,6 @@ PciHostBridgeP2CProcess ( if (EFI_ERROR (Status)) {
return Status;
}
-
}
return EFI_SUCCESS;
@@ -1496,16 +1518,16 @@ PciHostBridgeEnumerator ( IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
)
{
- EFI_HANDLE RootBridgeHandle;
- PCI_IO_DEVICE *RootBridgeDev;
- EFI_STATUS Status;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- UINT16 MinBus;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
- UINT8 StartBusNumber;
- LIST_ENTRY RootBridgeList;
- LIST_ENTRY *Link;
+ EFI_HANDLE RootBridgeHandle;
+ PCI_IO_DEVICE *RootBridgeDev;
+ EFI_STATUS Status;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ UINT16 MinBus;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
+ UINT8 StartBusNumber;
+ LIST_ENTRY RootBridgeList;
+ LIST_ENTRY *Link;
if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
InitializeHotPlugSupport ();
@@ -1522,10 +1544,9 @@ PciHostBridgeEnumerator ( return Status;
}
- DEBUG((DEBUG_INFO, "PCI Bus First Scanning\n"));
+ DEBUG ((DEBUG_INFO, "PCI Bus First Scanning\n"));
RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
-
//
// if a root bridge instance is found, create root bridge device for it
//
@@ -1540,15 +1561,16 @@ PciHostBridgeEnumerator ( // Enumerate all the buses under this root bridge
//
Status = PciRootBridgeEnumerator (
- PciResAlloc,
- RootBridgeDev
- );
+ PciResAlloc,
+ RootBridgeDev
+ );
- if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
+ if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));
} else {
DestroyRootBridge (RootBridgeDev);
}
+
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1559,14 +1581,15 @@ PciHostBridgeEnumerator ( //
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
- if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
+ if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
//
// Reset all assigned PCI bus number in all PPB
//
RootBridgeHandle = NULL;
- Link = GetFirstNode (&RootBridgeList);
+ Link = GetFirstNode (&RootBridgeList);
while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&
- (!IsNull (&RootBridgeList, Link))) {
+ (!IsNull (&RootBridgeList, Link)))
+ {
RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);
//
// Get the Bus information
@@ -1574,7 +1597,7 @@ PciHostBridgeEnumerator ( Status = PciResAlloc->StartBusEnumeration (
PciResAlloc,
RootBridgeHandle,
- (VOID **) &Configuration
+ (VOID **)&Configuration
);
if (EFI_ERROR (Status)) {
return Status;
@@ -1583,12 +1606,12 @@ PciHostBridgeEnumerator ( //
// Get the bus number to start with
//
- StartBusNumber = (UINT8) (Configuration->AddrRangeMin);
+ StartBusNumber = (UINT8)(Configuration->AddrRangeMin);
ResetAllPpbBusNumber (
RootBridgeDev,
StartBusNumber
- );
+ );
FreePool (Configuration);
Link = RemoveEntryList (Link);
@@ -1614,10 +1637,9 @@ PciHostBridgeEnumerator ( return Status;
}
- DEBUG((DEBUG_INFO, "PCI Bus Second Scanning\n"));
+ DEBUG ((DEBUG_INFO, "PCI Bus Second Scanning\n"));
RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
-
//
// if a root bridge instance is found, create root bridge device for it
//
@@ -1631,9 +1653,9 @@ PciHostBridgeEnumerator ( // Enumerate all the buses under this root bridge
//
Status = PciRootBridgeEnumerator (
- PciResAlloc,
- RootBridgeDev
- );
+ PciResAlloc,
+ RootBridgeDev
+ );
DestroyRootBridge (RootBridgeDev);
if (EFI_ERROR (Status)) {
@@ -1658,7 +1680,6 @@ PciHostBridgeEnumerator ( RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
-
//
// if a root bridge instance is found, create root bridge device for it
//
@@ -1675,7 +1696,7 @@ PciHostBridgeEnumerator ( }
PciRootBridgeIo = RootBridgeDev->PciRootBridgeIo;
- Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
+ Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **)&Descriptors);
if (EFI_ERROR (Status)) {
return Status;
@@ -1702,9 +1723,9 @@ PciHostBridgeEnumerator ( // root bridge will then be created
//
Status = PciPciDeviceInfoCollector (
- RootBridgeDev,
- (UINT8) MinBus
- );
+ RootBridgeDev,
+ (UINT8)MinBus
+ );
if (EFI_ERROR (Status)) {
return Status;
@@ -1738,33 +1759,36 @@ PciProgramResizableBar ( IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Capabilities;
- UINT32 Index;
- UINT32 Offset;
- INTN Bit;
- UINTN ResizableBarNumber;
- EFI_STATUS Status;
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Entries[PCI_MAX_BAR];
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Capabilities;
+ UINT32 Index;
+ UINT32 Offset;
+ INTN Bit;
+ UINTN ResizableBarNumber;
+ EFI_STATUS Status;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Entries[PCI_MAX_BAR];
ASSERT (PciIoDevice->ResizableBarOffset != 0);
- DEBUG ((DEBUG_INFO, " Programs Resizable BAR register, offset: 0x%08x, number: %d\n",
- PciIoDevice->ResizableBarOffset, PciIoDevice->ResizableBarNumber));
+ DEBUG ((
+ DEBUG_INFO,
+ " Programs Resizable BAR register, offset: 0x%08x, number: %d\n",
+ PciIoDevice->ResizableBarOffset,
+ PciIoDevice->ResizableBarNumber
+ ));
ResizableBarNumber = MIN (PciIoDevice->ResizableBarNumber, PCI_MAX_BAR);
- PciIo = &PciIoDevice->PciIo;
- Status = PciIo->Pci.Read (
- PciIo,
- EfiPciIoWidthUint8,
- PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER),
- sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) * ResizableBarNumber,
- (VOID *)(&Entries)
- );
+ PciIo = &PciIoDevice->PciIo;
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER),
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) * ResizableBarNumber,
+ (VOID *)(&Entries)
+ );
ASSERT_EFI_ERROR (Status);
for (Index = 0; Index < ResizableBarNumber; Index++) {
-
//
// When the bit of Capabilities Set, indicates that the Function supports
// operating with the BAR sized to (2^Bit) MB.
@@ -1773,36 +1797,37 @@ PciProgramResizableBar ( // Bit 1 is set: supports operating with the BAR sized to 2 MB
// Bit n is set: supports operating with the BAR sized to (2^n) MB
//
- Capabilities = LShiftU64(Entries[Index].ResizableBarControl.Bits.BarSizeCapability, 28)
- | Entries[Index].ResizableBarCapability.Bits.BarSizeCapability;
+ Capabilities = LShiftU64 (Entries[Index].ResizableBarControl.Bits.BarSizeCapability, 28)
+ | Entries[Index].ResizableBarCapability.Bits.BarSizeCapability;
if (ResizableBarOp == PciResizableBarMax) {
- Bit = HighBitSet64(Capabilities);
+ Bit = HighBitSet64 (Capabilities);
} else {
ASSERT (ResizableBarOp == PciResizableBarMin);
- Bit = LowBitSet64(Capabilities);
+ Bit = LowBitSet64 (Capabilities);
}
ASSERT (Bit >= 0);
Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)
- + Index * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY)
- + OFFSET_OF (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, ResizableBarControl);
+ + Index * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY)
+ + OFFSET_OF (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, ResizableBarControl);
- Entries[Index].ResizableBarControl.Bits.BarSize = (UINT32) Bit;
+ Entries[Index].ResizableBarControl.Bits.BarSize = (UINT32)Bit;
DEBUG ((
DEBUG_INFO,
" Resizable Bar: Offset = 0x%x, Bar Size Capability = 0x%016lx, New Bar Size = 0x%lx\n",
OFFSET_OF (PCI_TYPE00, Device.Bar[Entries[Index].ResizableBarControl.Bits.BarIndex]),
- Capabilities, LShiftU64 (SIZE_1MB, Bit)
+ Capabilities,
+ LShiftU64 (SIZE_1MB, Bit)
));
PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- Offset,
- 1,
- &Entries[Index].ResizableBarControl.Uint32
- );
+ PciIo,
+ EfiPciIoWidthUint32,
+ Offset,
+ 1,
+ &Entries[Index].ResizableBarControl.Uint32
+ );
}
return EFI_SUCCESS;
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h index aeec6d6b6d..5d2551148b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h @@ -9,19 +9,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_PCI_LIB_H_
#define _EFI_PCI_LIB_H_
-
typedef struct {
- EFI_HANDLE Handle;
+ EFI_HANDLE Handle;
} EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;
typedef struct {
- UINT32 Bar;
- UINT16 DevicePathSize;
- UINT16 ReqResSize;
- UINT16 AllocResSize;
- UINT8 *DevicePath;
- UINT8 *ReqRes;
- UINT8 *AllocRes;
+ UINT32 Bar;
+ UINT16 DevicePathSize;
+ UINT16 ReqResSize;
+ UINT16 AllocResSize;
+ UINT8 *DevicePath;
+ UINT8 *ReqRes;
+ UINT8 *AllocRes;
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;
typedef enum {
@@ -37,7 +36,7 @@ typedef enum { **/
VOID
GetBackPcCardBar (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -50,8 +49,8 @@ GetBackPcCardBar ( **/
VOID
RemoveRejectedPciDevices (
- IN EFI_HANDLE RootBridgeHandle,
- IN PCI_IO_DEVICE *Bridge
+ IN EFI_HANDLE RootBridgeHandle,
+ IN PCI_IO_DEVICE *Bridge
);
/**
@@ -69,7 +68,7 @@ RemoveRejectedPciDevices ( **/
EFI_STATUS
PciHostBridgeResourceAllocator (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -87,10 +86,10 @@ PciHostBridgeResourceAllocator ( **/
EFI_STATUS
PciAllocateBusNumber (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber,
- IN UINT8 NumberOfBuses,
- OUT UINT8 *NextBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber,
+ IN UINT8 NumberOfBuses,
+ OUT UINT8 *NextBusNumber
);
/**
@@ -109,10 +108,10 @@ PciAllocateBusNumber ( **/
EFI_STATUS
PciScanBus (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber,
- OUT UINT8 *SubBusNumber,
- OUT UINT8 *PaddedBusRange
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber,
+ OUT UINT8 *SubBusNumber,
+ OUT UINT8 *PaddedBusRange
);
/**
@@ -126,7 +125,7 @@ PciScanBus ( **/
EFI_STATUS
PciRootBridgeP2CProcess (
- IN PCI_IO_DEVICE *Bridge
+ IN PCI_IO_DEVICE *Bridge
);
/**
@@ -141,7 +140,7 @@ PciRootBridgeP2CProcess ( **/
EFI_STATUS
PciHostBridgeP2CProcess (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
@@ -176,4 +175,5 @@ PciProgramResizableBar ( IN PCI_IO_DEVICE *PciIoDevice,
IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp
);
+
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c index a981f93f43..89f5f64101 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c @@ -30,26 +30,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
LocalLoadFile2 (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
- IN OUT UINTN *BufferSize,
- IN VOID *Buffer OPTIONAL
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer OPTIONAL
)
{
- EFI_STATUS Status;
- MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *EfiOpRomImageNode;
- EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
- PCI_DATA_STRUCTURE *Pcir;
- UINT32 ImageSize;
- UINT8 *ImageBuffer;
- UINT32 ImageLength;
- UINT32 DestinationSize;
- UINT32 ScratchSize;
- VOID *Scratch;
- EFI_DECOMPRESS_PROTOCOL *Decompress;
- UINT32 InitializationSize;
-
- EfiOpRomImageNode = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *) FilePath;
+ EFI_STATUS Status;
+ MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *EfiOpRomImageNode;
+ EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
+ PCI_DATA_STRUCTURE *Pcir;
+ UINT32 ImageSize;
+ UINT8 *ImageBuffer;
+ UINT32 ImageLength;
+ UINT32 DestinationSize;
+ UINT32 ScratchSize;
+ VOID *Scratch;
+ EFI_DECOMPRESS_PROTOCOL *Decompress;
+ UINT32 InitializationSize;
+
+ EfiOpRomImageNode = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *)FilePath;
if ((EfiOpRomImageNode == NULL) ||
(DevicePathType (FilePath) != MEDIA_DEVICE_PATH) ||
(DevicePathSubType (FilePath) != MEDIA_RELATIVE_OFFSET_RANGE_DP) ||
@@ -58,19 +58,19 @@ LocalLoadFile2 ( (EfiOpRomImageNode->StartingOffset > EfiOpRomImageNode->EndingOffset) ||
(EfiOpRomImageNode->EndingOffset >= PciIoDevice->RomSize) ||
(BufferSize == NULL)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
- EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) (
- (UINT8 *) PciIoDevice->PciIo.RomImage + EfiOpRomImageNode->StartingOffset
- );
+ EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *)(
+ (UINT8 *)PciIoDevice->PciIo.RomImage + EfiOpRomImageNode->StartingOffset
+ );
if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
return EFI_NOT_FOUND;
}
-
- Pcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) EfiRomHeader + EfiRomHeader->PcirOffset);
+ Pcir = (PCI_DATA_STRUCTURE *)((UINT8 *)EfiRomHeader + EfiRomHeader->PcirOffset);
ASSERT (Pcir->Signature == PCI_DATA_STRUCTURE_SIGNATURE);
if ((Pcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) &&
@@ -78,22 +78,22 @@ LocalLoadFile2 ( ((EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER) ||
(EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER)) &&
(EfiRomHeader->CompressionType <= EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED)
- ) {
-
- ImageSize = Pcir->ImageLength * 512;
- InitializationSize = (UINT32) EfiRomHeader->InitializationSize * 512;
- if (InitializationSize > ImageSize || EfiRomHeader->EfiImageHeaderOffset >= InitializationSize) {
+ )
+ {
+ ImageSize = Pcir->ImageLength * 512;
+ InitializationSize = (UINT32)EfiRomHeader->InitializationSize * 512;
+ if ((InitializationSize > ImageSize) || (EfiRomHeader->EfiImageHeaderOffset >= InitializationSize)) {
return EFI_NOT_FOUND;
}
- ImageBuffer = (UINT8 *) EfiRomHeader + EfiRomHeader->EfiImageHeaderOffset;
- ImageLength = InitializationSize - EfiRomHeader->EfiImageHeaderOffset;
+ ImageBuffer = (UINT8 *)EfiRomHeader + EfiRomHeader->EfiImageHeaderOffset;
+ ImageLength = InitializationSize - EfiRomHeader->EfiImageHeaderOffset;
if (EfiRomHeader->CompressionType != EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED) {
//
// Uncompressed: Copy the EFI Image directly to user's buffer
//
- if (Buffer == NULL || *BufferSize < ImageLength) {
+ if ((Buffer == NULL) || (*BufferSize < ImageLength)) {
*BufferSize = ImageLength;
return EFI_BUFFER_TOO_SMALL;
}
@@ -101,15 +101,15 @@ LocalLoadFile2 ( *BufferSize = ImageLength;
CopyMem (Buffer, ImageBuffer, ImageLength);
return EFI_SUCCESS;
-
} else {
//
// Compressed: Uncompress before copying
//
- Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **) &Decompress);
+ Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **)&Decompress);
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
+
Status = Decompress->GetInfo (
Decompress,
ImageBuffer,
@@ -121,13 +121,13 @@ LocalLoadFile2 ( return EFI_DEVICE_ERROR;
}
- if (Buffer == NULL || *BufferSize < DestinationSize) {
+ if ((Buffer == NULL) || (*BufferSize < DestinationSize)) {
*BufferSize = DestinationSize;
return EFI_BUFFER_TOO_SMALL;
}
*BufferSize = DestinationSize;
- Scratch = AllocatePool (ScratchSize);
+ Scratch = AllocatePool (ScratchSize);
if (Scratch == NULL) {
return EFI_DEVICE_ERROR;
}
@@ -146,6 +146,7 @@ LocalLoadFile2 ( if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
+
return EFI_SUCCESS;
}
}
@@ -161,7 +162,7 @@ LocalLoadFile2 ( **/
VOID
InitializePciLoadFile2 (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
PciIoDevice->LoadFile2.LoadFile = LoadFile2;
@@ -193,18 +194,19 @@ InitializePciLoadFile2 ( EFI_STATUS
EFIAPI
LoadFile2 (
- IN EFI_LOAD_FILE2_PROTOCOL *This,
- IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
- IN BOOLEAN BootPolicy,
- IN OUT UINTN *BufferSize,
- IN VOID *Buffer OPTIONAL
+ IN EFI_LOAD_FILE2_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN BOOLEAN BootPolicy,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer OPTIONAL
)
{
- PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *PciIoDevice;
if (BootPolicy) {
return EFI_UNSUPPORTED;
}
+
PciIoDevice = PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS (This);
return LocalLoadFile2 (
@@ -227,21 +229,21 @@ LoadFile2 ( **/
EFI_STATUS
GetOpRomInfo (
- IN OUT PCI_IO_DEVICE *PciIoDevice
+ IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
- UINT8 RomBarIndex;
- UINT32 AllOnes;
- UINT64 Address;
- EFI_STATUS Status;
- UINT8 Bus;
- UINT8 Device;
- UINT8 Function;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
-
- Bus = PciIoDevice->BusNumber;
- Device = PciIoDevice->DeviceNumber;
- Function = PciIoDevice->FunctionNumber;
+ UINT8 RomBarIndex;
+ UINT32 AllOnes;
+ UINT64 Address;
+ EFI_STATUS Status;
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+
+ Bus = PciIoDevice->BusNumber;
+ Device = PciIoDevice->DeviceNumber;
+ Function = PciIoDevice->FunctionNumber;
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
@@ -260,6 +262,7 @@ GetOpRomInfo ( //
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
+
//
// The bit0 is 0 to prevent the enabling of the Rom address decoder
//
@@ -280,7 +283,7 @@ GetOpRomInfo ( //
// Read back
//
- Status = PciRootBridgeIo->Pci.Read(
+ Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
@@ -315,8 +318,8 @@ GetOpRomInfo ( **/
BOOLEAN
ContainEfiImage (
- IN VOID *RomImage,
- IN UINT64 RomSize
+ IN VOID *RomImage,
+ IN UINT64 RomSize
)
{
PCI_EXPANSION_ROM_HEADER *RomHeader;
@@ -331,20 +334,21 @@ ContainEfiImage ( do {
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
- RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + 512);
+ RomHeader = (PCI_EXPANSION_ROM_HEADER *)((UINT8 *)RomHeader + 512);
continue;
}
//
// The PCI Data Structure must be DWORD aligned.
//
- if (RomHeader->PcirOffset == 0 ||
- (RomHeader->PcirOffset & 3) != 0 ||
- (UINT8 *) RomHeader + RomHeader->PcirOffset + sizeof (PCI_DATA_STRUCTURE) > (UINT8 *) RomImage + RomSize) {
+ if ((RomHeader->PcirOffset == 0) ||
+ ((RomHeader->PcirOffset & 3) != 0) ||
+ ((UINT8 *)RomHeader + RomHeader->PcirOffset + sizeof (PCI_DATA_STRUCTURE) > (UINT8 *)RomImage + RomSize))
+ {
break;
}
- RomPcir = (PCI_DATA_STRUCTURE *) ((UINT8 *) RomHeader + RomHeader->PcirOffset);
+ RomPcir = (PCI_DATA_STRUCTURE *)((UINT8 *)RomHeader + RomHeader->PcirOffset);
if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
@@ -354,8 +358,8 @@ ContainEfiImage ( }
Indicator = RomPcir->Indicator;
- RomHeader = (PCI_EXPANSION_ROM_HEADER *) ((UINT8 *) RomHeader + RomPcir->ImageLength * 512);
- } while (((UINT8 *) RomHeader < (UINT8 *) RomImage + RomSize) && ((Indicator & 0x80) == 0x00));
+ RomHeader = (PCI_EXPANSION_ROM_HEADER *)((UINT8 *)RomHeader + RomPcir->ImageLength * 512);
+ } while (((UINT8 *)RomHeader < (UINT8 *)RomImage + RomSize) && ((Indicator & 0x80) == 0x00));
return FALSE;
}
@@ -372,8 +376,8 @@ ContainEfiImage ( **/
EFI_STATUS
LoadOpRomImage (
- IN PCI_IO_DEVICE *PciDevice,
- IN UINT64 RomBase
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINT64 RomBase
)
{
UINT8 RomBarIndex;
@@ -392,12 +396,12 @@ LoadOpRomImage ( UINT8 *RomInMemory;
UINT8 CodeType;
- RomSize = PciDevice->RomSize;
+ RomSize = PciDevice->RomSize;
- Indicator = 0;
- RomImageSize = 0;
- RomInMemory = NULL;
- CodeType = 0xFF;
+ Indicator = 0;
+ RomImageSize = 0;
+ RomInMemory = NULL;
+ CodeType = 0xFF;
//
// Get the RomBarIndex
@@ -417,6 +421,7 @@ LoadOpRomImage ( //
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
+
//
// Allocate memory for Rom header and PCIR
//
@@ -431,16 +436,16 @@ LoadOpRomImage ( return EFI_OUT_OF_RESOURCES;
}
- RomBar = (UINT32) RomBase;
+ RomBar = (UINT32)RomBase;
//
// Enable RomBar
//
RomDecode (PciDevice, RomBarIndex, RomBar, TRUE);
- RomBarOffset = RomBar;
- RetStatus = EFI_NOT_FOUND;
- FirstCheck = TRUE;
+ RomBarOffset = RomBar;
+ RetStatus = EFI_NOT_FOUND;
+ FirstCheck = TRUE;
LegacyImageLength = 0;
do {
@@ -449,7 +454,7 @@ LoadOpRomImage ( EfiPciWidthUint8,
RomBarOffset,
sizeof (PCI_EXPANSION_ROM_HEADER),
- (UINT8 *) RomHeader
+ (UINT8 *)RomHeader
);
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
@@ -462,23 +467,25 @@ LoadOpRomImage ( }
}
- FirstCheck = FALSE;
- OffsetPcir = RomHeader->PcirOffset;
+ FirstCheck = FALSE;
+ OffsetPcir = RomHeader->PcirOffset;
//
// If the pointer to the PCI Data Structure is invalid, no further images can be located.
// The PCI Data Structure must be DWORD aligned.
//
- if (OffsetPcir == 0 ||
- (OffsetPcir & 3) != 0 ||
- RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > RomSize) {
+ if ((OffsetPcir == 0) ||
+ ((OffsetPcir & 3) != 0) ||
+ (RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > RomSize))
+ {
break;
}
+
PciDevice->PciRootBridgeIo->Mem.Read (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint8,
RomBarOffset + OffsetPcir,
sizeof (PCI_DATA_STRUCTURE),
- (UINT8 *) RomPcir
+ (UINT8 *)RomPcir
);
//
// If a valid signature is not present in the PCI Data Structure, no further images can be located.
@@ -486,16 +493,19 @@ LoadOpRomImage ( if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
+
if (RomImageSize + RomPcir->ImageLength * 512 > RomSize) {
break;
}
+
if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
- CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
+ CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
LegacyImageLength = ((UINT32)((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512) * 512;
}
- Indicator = RomPcir->Indicator;
- RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
- RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
+
+ Indicator = RomPcir->Indicator;
+ RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
+ RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
} while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));
//
@@ -508,7 +518,7 @@ LoadOpRomImage ( if (RomImageSize > 0) {
RetStatus = EFI_SUCCESS;
- Image = AllocatePool ((UINT32) RomImageSize);
+ Image = AllocatePool ((UINT32)RomImageSize);
if (Image == NULL) {
RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
FreePool (RomHeader);
@@ -523,7 +533,7 @@ LoadOpRomImage ( PciDevice->PciRootBridgeIo,
EfiPciWidthUint32,
RomBar,
- (UINT32) RomImageSize/sizeof(UINT32),
+ (UINT32)RomImageSize/sizeof (UINT32),
Image
);
RomInMemory = Image;
@@ -570,18 +580,17 @@ LoadOpRomImage ( **/
VOID
RomDecode (
- IN PCI_IO_DEVICE *PciDevice,
- IN UINT8 RomBarIndex,
- IN UINT32 RomBar,
- IN BOOLEAN Enable
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINT8 RomBarIndex,
+ IN UINT32 RomBar,
+ IN BOOLEAN Enable
)
{
- UINT32 Value32;
- EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 Value32;
+ EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = &PciDevice->PciIo;
if (Enable) {
-
//
// set the Rom base address: now is hardcode
// enable its decoder
@@ -589,7 +598,7 @@ RomDecode ( Value32 = RomBar | 0x1;
PciIo->Pci.Write (
PciIo,
- (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
+ (EFI_PCI_IO_PROTOCOL_WIDTH)EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
@@ -603,14 +612,12 @@ RomDecode ( //
// Setting the memory space bit in the function's command register
//
- PCI_ENABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
-
+ PCI_ENABLE_COMMAND_REGISTER (PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
} else {
-
//
// disable command register decode to memory
//
- PCI_DISABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
+ PCI_DISABLE_COMMAND_REGISTER (PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
//
// Destroy the programmed bar in all the upstream bridge.
@@ -623,12 +630,11 @@ RomDecode ( Value32 = 0xFFFFFFFE;
PciIo->Pci.Write (
PciIo,
- (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
+ (EFI_PCI_IO_PROTOCOL_WIDTH)EfiPciWidthUint32,
RomBarIndex,
1,
&Value32
);
-
}
}
@@ -643,7 +649,7 @@ RomDecode ( **/
EFI_STATUS
ProcessOpRomImage (
- IN PCI_IO_DEVICE *PciDevice
+ IN PCI_IO_DEVICE *PciDevice
)
{
UINT8 Indicator;
@@ -665,26 +671,27 @@ ProcessOpRomImage ( //
// Get the Address of the Option Rom image
//
- RomBar = PciDevice->PciIo.RomImage;
- RomBarOffset = (UINT8 *) RomBar;
- RetStatus = EFI_NOT_FOUND;
+ RomBar = PciDevice->PciIo.RomImage;
+ RomBarOffset = (UINT8 *)RomBar;
+ RetStatus = EFI_NOT_FOUND;
if (RomBar == NULL) {
return RetStatus;
}
- ASSERT (((EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset)->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE);
+
+ ASSERT (((EFI_PCI_EXPANSION_ROM_HEADER *)RomBarOffset)->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE);
do {
- EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset;
+ EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *)RomBarOffset;
if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
RomBarOffset += 512;
continue;
}
- Pcir = (PCI_DATA_STRUCTURE *) (RomBarOffset + EfiRomHeader->PcirOffset);
+ Pcir = (PCI_DATA_STRUCTURE *)(RomBarOffset + EfiRomHeader->PcirOffset);
ASSERT (Pcir->Signature == PCI_DATA_STRUCTURE_SIGNATURE);
- ImageSize = (UINT32) (Pcir->ImageLength * 512);
- Indicator = Pcir->Indicator;
+ ImageSize = (UINT32)(Pcir->ImageLength * 512);
+ Indicator = Pcir->Indicator;
//
// Skip the image if it is not an EFI PCI Option ROM image
@@ -703,11 +710,11 @@ ProcessOpRomImage ( //
// Create Pci Option Rom Image device path header
//
- EfiOpRomImageNode.Header.Type = MEDIA_DEVICE_PATH;
- EfiOpRomImageNode.Header.SubType = MEDIA_RELATIVE_OFFSET_RANGE_DP;
+ EfiOpRomImageNode.Header.Type = MEDIA_DEVICE_PATH;
+ EfiOpRomImageNode.Header.SubType = MEDIA_RELATIVE_OFFSET_RANGE_DP;
SetDevicePathNodeLength (&EfiOpRomImageNode.Header, sizeof (EfiOpRomImageNode));
- EfiOpRomImageNode.StartingOffset = (UINTN) RomBarOffset - (UINTN) RomBar;
- EfiOpRomImageNode.EndingOffset = (UINTN) RomBarOffset + ImageSize - 1 - (UINTN) RomBar;
+ EfiOpRomImageNode.StartingOffset = (UINTN)RomBarOffset - (UINTN)RomBar;
+ EfiOpRomImageNode.EndingOffset = (UINTN)RomBarOffset + ImageSize - 1 - (UINTN)RomBar;
PciOptionRomImageDevicePath = AppendDevicePathNode (PciDevice->DevicePath, &EfiOpRomImageNode.Header);
ASSERT (PciOptionRomImageDevicePath != NULL);
@@ -752,13 +759,12 @@ ProcessOpRomImage ( RetStatus = EFI_SUCCESS;
}
}
+
FreePool (PciOptionRomImageDevicePath);
NextImage:
RomBarOffset += ImageSize;
-
- } while (((Indicator & 0x80) == 0x00) && (((UINTN) RomBarOffset - (UINTN) RomBar) < PciDevice->RomSize));
+ } while (((Indicator & 0x80) == 0x00) && (((UINTN)RomBarOffset - (UINTN)RomBar) < PciDevice->RomSize));
return RetStatus;
}
-
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h index 5c4e9fa3b6..16998a422e 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h @@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_PCI_OPTION_ROM_SUPPORT_H_
#define _EFI_PCI_OPTION_ROM_SUPPORT_H_
-
/**
Initialize a PCI LoadFile2 instance.
@@ -18,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
InitializePciLoadFile2 (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -47,11 +46,11 @@ InitializePciLoadFile2 ( EFI_STATUS
EFIAPI
LoadFile2 (
- IN EFI_LOAD_FILE2_PROTOCOL *This,
- IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
- IN BOOLEAN BootPolicy,
- IN OUT UINTN *BufferSize,
- IN VOID *Buffer OPTIONAL
+ IN EFI_LOAD_FILE2_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN BOOLEAN BootPolicy,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer OPTIONAL
);
/**
@@ -66,8 +65,8 @@ LoadFile2 ( **/
BOOLEAN
ContainEfiImage (
- IN VOID *RomImage,
- IN UINT64 RomSize
+ IN VOID *RomImage,
+ IN UINT64 RomSize
);
/**
@@ -82,7 +81,7 @@ ContainEfiImage ( **/
EFI_STATUS
GetOpRomInfo (
- IN OUT PCI_IO_DEVICE *PciIoDevice
+ IN OUT PCI_IO_DEVICE *PciIoDevice
);
/**
@@ -97,8 +96,8 @@ GetOpRomInfo ( **/
EFI_STATUS
LoadOpRomImage (
- IN PCI_IO_DEVICE *PciDevice,
- IN UINT64 RomBase
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINT64 RomBase
);
/**
@@ -113,10 +112,10 @@ LoadOpRomImage ( **/
VOID
RomDecode (
- IN PCI_IO_DEVICE *PciDevice,
- IN UINT8 RomBarIndex,
- IN UINT32 RomBar,
- IN BOOLEAN Enable
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINT8 RomBarIndex,
+ IN UINT32 RomBar,
+ IN BOOLEAN Enable
);
/**
@@ -130,7 +129,7 @@ RomDecode ( **/
EFI_STATUS
ProcessOpRomImage (
- IN PCI_IO_DEVICE *PciDevice
+ IN PCI_IO_DEVICE *PciDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c index c7f3ea5099..ce23964e50 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c @@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
ResetPowerManagementFeature (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
@@ -31,11 +31,11 @@ ResetPowerManagementFeature ( PowerManagementRegBlock = 0;
Status = LocateCapabilityRegBlock (
- PciIoDevice,
- EFI_PCI_CAPABILITY_ID_PMI,
- &PowerManagementRegBlock,
- NULL
- );
+ PciIoDevice,
+ EFI_PCI_CAPABILITY_ID_PMI,
+ &PowerManagementRegBlock,
+ NULL
+ );
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
@@ -77,6 +77,6 @@ ResetPowerManagementFeature ( &PowerManagementCSR
);
}
+
return Status;
}
-
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h index b5018dcf11..d11a8fdc68 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h @@ -22,7 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
ResetPowerManagementFeature (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 4969ee0f64..8ffd05f327 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -11,9 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// The default policy for the PCI bus driver is NOT to reserve I/O ranges for both ISA aliases and VGA aliases.
//
-BOOLEAN mReserveIsaAliases = FALSE;
-BOOLEAN mReserveVgaAliases = FALSE;
-BOOLEAN mPolicyDetermined = FALSE;
+BOOLEAN mReserveIsaAliases = FALSE;
+BOOLEAN mReserveVgaAliases = FALSE;
+BOOLEAN mPolicyDetermined = FALSE;
/**
The function is used to skip VGA range.
@@ -24,8 +24,8 @@ BOOLEAN mPolicyDetermined = FALSE; **/
VOID
SkipVGAAperture (
- OUT UINT64 *Start,
- IN UINT64 Length
+ OUT UINT64 *Start,
+ IN UINT64 Length
)
{
UINT64 Original;
@@ -37,7 +37,7 @@ SkipVGAAperture ( //
// For legacy VGA, bit 10 to bit 15 is not decoded
//
- Mask = 0x3FF;
+ Mask = 0x3FF;
Original = *Start;
StartOffset = Original & Mask;
@@ -56,11 +56,10 @@ SkipVGAAperture ( **/
VOID
SkipIsaAliasAperture (
- OUT UINT64 *Start,
- IN UINT64 Length
+ OUT UINT64 *Start,
+ IN UINT64 Length
)
{
-
UINT64 Original;
UINT64 Mask;
UINT64 StartOffset;
@@ -71,7 +70,7 @@ SkipIsaAliasAperture ( //
// For legacy ISA, bit 10 to bit 15 is not decoded
//
- Mask = 0x3FF;
+ Mask = 0x3FF;
Original = *Start;
StartOffset = Original & Mask;
@@ -92,14 +91,14 @@ SkipIsaAliasAperture ( **/
VOID
InsertResourceNode (
- IN OUT PCI_RESOURCE_NODE *Bridge,
- IN PCI_RESOURCE_NODE *ResNode
+ IN OUT PCI_RESOURCE_NODE *Bridge,
+ IN PCI_RESOURCE_NODE *ResNode
)
{
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Temp;
- UINT64 ResNodeAlignRest;
- UINT64 TempAlignRest;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Temp;
+ UINT64 ResNodeAlignRest;
+ UINT64 TempAlignRest;
ASSERT (Bridge != NULL);
ASSERT (ResNode != NULL);
@@ -113,8 +112,8 @@ InsertResourceNode ( if (ResNode->Alignment > Temp->Alignment) {
break;
} else if (ResNode->Alignment == Temp->Alignment) {
- ResNodeAlignRest = ResNode->Length & ResNode->Alignment;
- TempAlignRest = Temp->Length & Temp->Alignment;
+ ResNodeAlignRest = ResNode->Length & ResNode->Alignment;
+ TempAlignRest = Temp->Length & Temp->Alignment;
if ((ResNodeAlignRest == 0) || (ResNodeAlignRest >= TempAlignRest)) {
break;
}
@@ -146,14 +145,13 @@ InsertResourceNode ( **/
VOID
MergeResourceTree (
- IN PCI_RESOURCE_NODE *Dst,
- IN PCI_RESOURCE_NODE *Res,
- IN BOOLEAN TypeMerge
+ IN PCI_RESOURCE_NODE *Dst,
+ IN PCI_RESOURCE_NODE *Res,
+ IN BOOLEAN TypeMerge
)
{
-
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Temp;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Temp;
ASSERT (Dst != NULL);
ASSERT (Res != NULL);
@@ -161,7 +159,7 @@ MergeResourceTree ( while (!IsListEmpty (&Res->ChildList)) {
CurrentLink = Res->ChildList.ForwardLink;
- Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
+ Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (TypeMerge) {
Temp->ResType = Dst->ResType;
@@ -181,22 +179,22 @@ MergeResourceTree ( **/
VOID
CalculateApertureIo16 (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- EFI_STATUS Status;
- UINT64 Aperture;
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Node;
- UINT64 Offset;
- EFI_PCI_PLATFORM_POLICY PciPolicy;
- UINT64 PaddingAperture;
+ EFI_STATUS Status;
+ UINT64 Aperture;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Node;
+ UINT64 Offset;
+ EFI_PCI_PLATFORM_POLICY PciPolicy;
+ UINT64 PaddingAperture;
if (!mPolicyDetermined) {
//
// Check PciPlatform policy
//
- Status = EFI_NOT_FOUND;
+ Status = EFI_NOT_FOUND;
PciPolicy = 0;
if (gPciPlatformProtocol != NULL) {
Status = gPciPlatformProtocol->GetPlatformPolicy (
@@ -205,7 +203,7 @@ CalculateApertureIo16 ( );
}
- if (EFI_ERROR (Status) && gPciOverrideProtocol != NULL) {
+ if (EFI_ERROR (Status) && (gPciOverrideProtocol != NULL)) {
Status = gPciOverrideProtocol->GetPlatformPolicy (
gPciOverrideProtocol,
&PciPolicy
@@ -216,10 +214,12 @@ CalculateApertureIo16 ( if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {
mReserveIsaAliases = TRUE;
}
+
if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {
mReserveVgaAliases = TRUE;
}
}
+
mPolicyDetermined = TRUE;
}
@@ -227,32 +227,31 @@ CalculateApertureIo16 ( PaddingAperture = 0;
if (Bridge == NULL) {
- return ;
+ return;
}
//
// Assume the bridge is aligned
//
for ( CurrentLink = GetFirstNode (&Bridge->ChildList)
- ; !IsNull (&Bridge->ChildList, CurrentLink)
- ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
- ) {
-
+ ; !IsNull (&Bridge->ChildList, CurrentLink)
+ ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
+ )
+ {
Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (Node->ResourceUsage == PciResUsagePadding) {
ASSERT (PaddingAperture == 0);
PaddingAperture = Node->Length;
continue;
}
+
//
// Consider the aperture alignment
//
Offset = Aperture & (Node->Alignment);
if (Offset != 0) {
-
Aperture = Aperture + (Node->Alignment + 1) - Offset;
-
}
//
@@ -334,21 +333,20 @@ CalculateApertureIo16 ( **/
VOID
CalculateResourceAperture (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- UINT64 Aperture[2];
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Node;
+ UINT64 Aperture[2];
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Node;
if (Bridge == NULL) {
- return ;
+ return;
}
if (Bridge->ResType == PciBarTypeIo16) {
-
CalculateApertureIo16 (Bridge);
- return ;
+ return;
}
Aperture[PciResUsageTypical] = 0;
@@ -357,17 +355,20 @@ CalculateResourceAperture ( // Assume the bridge is aligned
//
for ( CurrentLink = GetFirstNode (&Bridge->ChildList)
- ; !IsNull (&Bridge->ChildList, CurrentLink)
- ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
- ) {
+ ; !IsNull (&Bridge->ChildList, CurrentLink)
+ ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
+ )
+ {
Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
//
// It's possible for a bridge to contain multiple padding resource
// nodes due to DegradeResource().
//
- ASSERT ((Node->ResourceUsage == PciResUsageTypical) ||
- (Node->ResourceUsage == PciResUsagePadding));
+ ASSERT (
+ (Node->ResourceUsage == PciResUsageTypical) ||
+ (Node->ResourceUsage == PciResUsagePadding)
+ );
ASSERT (Node->ResourceUsage < ARRAY_SIZE (Aperture));
//
// Recode current aperture as a offset
@@ -419,126 +420,123 @@ CalculateResourceAperture ( **/
VOID
GetResourceFromDevice (
- IN PCI_IO_DEVICE *PciDev,
- IN OUT PCI_RESOURCE_NODE *IoNode,
- IN OUT PCI_RESOURCE_NODE *Mem32Node,
- IN OUT PCI_RESOURCE_NODE *PMem32Node,
- IN OUT PCI_RESOURCE_NODE *Mem64Node,
- IN OUT PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN OUT PCI_RESOURCE_NODE *IoNode,
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,
+ IN OUT PCI_RESOURCE_NODE *PMem64Node
)
{
-
- UINT8 Index;
- PCI_RESOURCE_NODE *Node;
- BOOLEAN ResourceRequested;
+ UINT8 Index;
+ PCI_RESOURCE_NODE *Node;
+ BOOLEAN ResourceRequested;
Node = NULL;
ResourceRequested = FALSE;
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
-
switch ((PciDev->PciBar)[Index].BarType) {
+ case PciBarTypeMem32:
+ case PciBarTypeOpRom:
- case PciBarTypeMem32:
- case PciBarTypeOpRom:
-
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- (PciDev->PciBar)[Index].BarType,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ (PciDev->PciBar)[Index].BarType,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem32Node,
- Node
- );
+ InsertResourceNode (
+ Mem32Node,
+ Node
+ );
- ResourceRequested = TRUE;
- break;
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypeMem64:
+ case PciBarTypeMem64:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypeMem64,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypeMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem64Node,
- Node
- );
+ InsertResourceNode (
+ Mem64Node,
+ Node
+ );
- ResourceRequested = TRUE;
- break;
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypePMem64:
+ case PciBarTypePMem64:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypePMem64,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem64Node,
- Node
- );
+ InsertResourceNode (
+ PMem64Node,
+ Node
+ );
- ResourceRequested = TRUE;
- break;
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypePMem32:
+ case PciBarTypePMem32:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypePMem32,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem32,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem32Node,
- Node
- );
- ResourceRequested = TRUE;
- break;
+ InsertResourceNode (
+ PMem32Node,
+ Node
+ );
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypeIo16,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypeIo16,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- IoNode,
- Node
- );
- ResourceRequested = TRUE;
- break;
+ InsertResourceNode (
+ IoNode,
+ Node
+ );
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypeUnknown:
- break;
+ case PciBarTypeUnknown:
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -546,91 +544,90 @@ GetResourceFromDevice ( // Add VF resource
//
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
-
switch ((PciDev->VfPciBar)[Index].BarType) {
+ case PciBarTypeMem32:
- case PciBarTypeMem32:
-
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypeMem32,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypeMem32,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem32Node,
- Node
- );
+ InsertResourceNode (
+ Mem32Node,
+ Node
+ );
- break;
+ break;
- case PciBarTypeMem64:
+ case PciBarTypeMem64:
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypeMem64,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypeMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem64Node,
- Node
- );
+ InsertResourceNode (
+ Mem64Node,
+ Node
+ );
- break;
+ break;
- case PciBarTypePMem64:
+ case PciBarTypePMem64:
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypePMem64,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem64Node,
- Node
- );
+ InsertResourceNode (
+ PMem64Node,
+ Node
+ );
- break;
+ break;
- case PciBarTypePMem32:
+ case PciBarTypePMem32:
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypePMem32,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem32,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem32Node,
- Node
- );
- break;
+ InsertResourceNode (
+ PMem32Node,
+ Node
+ );
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- break;
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ break;
- case PciBarTypeUnknown:
- break;
+ case PciBarTypeUnknown:
+ break;
- default:
- break;
+ default:
+ break;
}
}
+
// If there is no resource requested from this device,
// then we indicate this device has been allocated naturally.
//
@@ -655,19 +652,19 @@ GetResourceFromDevice ( **/
PCI_RESOURCE_NODE *
CreateResourceNode (
- IN PCI_IO_DEVICE *PciDev,
- IN UINT64 Length,
- IN UINT64 Alignment,
- IN UINT8 Bar,
- IN PCI_BAR_TYPE ResType,
- IN PCI_RESOURCE_USAGE ResUsage
+ IN PCI_IO_DEVICE *PciDev,
+ IN UINT64 Length,
+ IN UINT64 Alignment,
+ IN UINT8 Bar,
+ IN PCI_BAR_TYPE ResType,
+ IN PCI_RESOURCE_USAGE ResUsage
)
{
- PCI_RESOURCE_NODE *Node;
+ PCI_RESOURCE_NODE *Node;
- Node = NULL;
+ Node = NULL;
- Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));
+ Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));
ASSERT (Node != NULL);
if (Node == NULL) {
return NULL;
@@ -702,15 +699,15 @@ CreateResourceNode ( **/
PCI_RESOURCE_NODE *
CreateVfResourceNode (
- IN PCI_IO_DEVICE *PciDev,
- IN UINT64 Length,
- IN UINT64 Alignment,
- IN UINT8 Bar,
- IN PCI_BAR_TYPE ResType,
- IN PCI_RESOURCE_USAGE ResUsage
+ IN PCI_IO_DEVICE *PciDev,
+ IN UINT64 Length,
+ IN UINT64 Alignment,
+ IN UINT8 Bar,
+ IN PCI_BAR_TYPE ResType,
+ IN PCI_RESOURCE_USAGE ResUsage
)
{
- PCI_RESOURCE_NODE *Node;
+ PCI_RESOURCE_NODE *Node;
Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);
if (Node == NULL) {
@@ -736,26 +733,25 @@ CreateVfResourceNode ( **/
VOID
CreateResourceMap (
- IN PCI_IO_DEVICE *Bridge,
- IN OUT PCI_RESOURCE_NODE *IoNode,
- IN OUT PCI_RESOURCE_NODE *Mem32Node,
- IN OUT PCI_RESOURCE_NODE *PMem32Node,
- IN OUT PCI_RESOURCE_NODE *Mem64Node,
- IN OUT PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *Bridge,
+ IN OUT PCI_RESOURCE_NODE *IoNode,
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,
+ IN OUT PCI_RESOURCE_NODE *PMem64Node
)
{
- PCI_IO_DEVICE *Temp;
- PCI_RESOURCE_NODE *IoBridge;
- PCI_RESOURCE_NODE *Mem32Bridge;
- PCI_RESOURCE_NODE *PMem32Bridge;
- PCI_RESOURCE_NODE *Mem64Bridge;
- PCI_RESOURCE_NODE *PMem64Bridge;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
+ PCI_RESOURCE_NODE *IoBridge;
+ PCI_RESOURCE_NODE *Mem32Bridge;
+ PCI_RESOURCE_NODE *PMem32Bridge;
+ PCI_RESOURCE_NODE *Mem64Bridge;
+ PCI_RESOURCE_NODE *PMem64Bridge;
+ LIST_ENTRY *CurrentLink;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
-
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
//
@@ -774,7 +770,6 @@ CreateResourceMap ( );
if (IS_PCI_BRIDGE (&Temp->Pci)) {
-
//
// If the device has children, create a bridge resource node for this PPB
// Note: For PPB, memory aperture is aligned with 1MB and IO aperture
@@ -910,7 +905,6 @@ CreateResourceMap ( FreePool (PMem64Bridge);
PMem64Bridge = NULL;
}
-
}
//
@@ -976,12 +970,12 @@ CreateResourceMap ( **/
VOID
ResourcePaddingPolicy (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
//
@@ -1015,18 +1009,18 @@ ResourcePaddingPolicy ( **/
VOID
DegradeResource (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
- PCI_IO_DEVICE *PciIoDevice;
- LIST_ENTRY *ChildDeviceLink;
- LIST_ENTRY *ChildNodeLink;
- LIST_ENTRY *NextChildNodeLink;
- PCI_RESOURCE_NODE *ResourceNode;
+ PCI_IO_DEVICE *PciIoDevice;
+ LIST_ENTRY *ChildDeviceLink;
+ LIST_ENTRY *ChildNodeLink;
+ LIST_ENTRY *NextChildNodeLink;
+ PCI_RESOURCE_NODE *ResourceNode;
if (FeaturePcdGet (PcdPciDegradeResourceForOptionRom)) {
//
@@ -1040,15 +1034,17 @@ DegradeResource ( if (!IsListEmpty (&Mem64Node->ChildList)) {
ChildNodeLink = Mem64Node->ChildList.ForwardLink;
while (ChildNodeLink != &Mem64Node->ChildList) {
- ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
+ ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
NextChildNodeLink = ChildNodeLink->ForwardLink;
if ((ResourceNode->PciDev == PciIoDevice) &&
(ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)
- ) {
+ )
+ {
RemoveEntryList (ChildNodeLink);
InsertResourceNode (Mem32Node, ResourceNode);
}
+
ChildNodeLink = NextChildNodeLink;
}
}
@@ -1056,20 +1052,22 @@ DegradeResource ( if (!IsListEmpty (&PMem64Node->ChildList)) {
ChildNodeLink = PMem64Node->ChildList.ForwardLink;
while (ChildNodeLink != &PMem64Node->ChildList) {
- ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
+ ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
NextChildNodeLink = ChildNodeLink->ForwardLink;
if ((ResourceNode->PciDev == PciIoDevice) &&
(ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)
- ) {
+ )
+ {
RemoveEntryList (ChildNodeLink);
InsertResourceNode (PMem32Node, ResourceNode);
}
+
ChildNodeLink = NextChildNodeLink;
}
}
-
}
+
ChildDeviceLink = ChildDeviceLink->ForwardLink;
}
}
@@ -1095,11 +1093,11 @@ DegradeResource ( // if the bridge does not support MEM64, degrade MEM64 to MEM32
//
if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_MEM64_DECODE_SUPPORTED)) {
- MergeResourceTree (
- Mem32Node,
- Mem64Node,
- TRUE
- );
+ MergeResourceTree (
+ Mem32Node,
+ Mem64Node,
+ TRUE
+ );
}
//
@@ -1117,7 +1115,7 @@ DegradeResource ( // if both PMEM64 and PMEM32 requests from child devices, which can not be satisfied
// by a P2P bridge simultaneously, keep PMEM64 and degrade PMEM32 to MEM32.
//
- if (!IsListEmpty (&PMem64Node->ChildList) && Bridge->Parent != NULL) {
+ if (!IsListEmpty (&PMem64Node->ChildList) && (Bridge->Parent != NULL)) {
MergeResourceTree (
Mem32Node,
PMem32Node,
@@ -1174,8 +1172,8 @@ DegradeResource ( **/
BOOLEAN
BridgeSupportResourceDecode (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT32 Decode
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT32 Decode
)
{
if (((Bridge->Decodes) & Decode) != 0) {
@@ -1199,13 +1197,13 @@ BridgeSupportResourceDecode ( **/
EFI_STATUS
ProgramResource (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Bridge
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Node;
- EFI_STATUS Status;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Node;
+ EFI_STATUS Status;
if (Base == gAllOne) {
return EFI_OUT_OF_RESOURCES;
@@ -1214,11 +1212,9 @@ ProgramResource ( CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != &Bridge->ChildList) {
-
Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {
-
if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {
//
// Program the PCI Card Bus device
@@ -1257,13 +1253,13 @@ ProgramResource ( **/
VOID
ProgramBar (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT32 Address32;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT32 Address32;
ASSERT (Node->Bar < PCI_MAX_BAR);
@@ -1289,59 +1285,58 @@ ProgramBar ( Node->PciDev->Allocated = TRUE;
switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ case PciBarTypeMem32:
+ case PciBarTypePMem32:
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- case PciBarTypeMem32:
- case PciBarTypePMem32:
-
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
- //
- // Continue to the case PciBarTypeOpRom to set the BaseAddress.
- // PciBarTypeOpRom is a virtual BAR only in root bridge, to capture
- // the MEM32 resource requirement for Option ROM shadow.
- //
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address
+ );
+ //
+ // Continue to the case PciBarTypeOpRom to set the BaseAddress.
+ // PciBarTypeOpRom is a virtual BAR only in root bridge, to capture
+ // the MEM32 resource requirement for Option ROM shadow.
+ //
- case PciBarTypeOpRom:
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ case PciBarTypeOpRom:
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- break;
+ break;
- case PciBarTypeMem64:
- case PciBarTypePMem64:
+ case PciBarTypeMem64:
+ case PciBarTypePMem64:
- Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
+ Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 (Address, 32);
+ Address32 = (UINT32)RShiftU64 (Address, 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (UINT8)((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- break;
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -1354,13 +1349,13 @@ ProgramBar ( **/
EFI_STATUS
ProgramVfBar (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT32 Address32;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT32 Address32;
ASSERT (Node->Bar < PCI_MAX_BAR);
ASSERT (Node->Virtual);
@@ -1379,53 +1374,52 @@ ProgramVfBar ( Node->PciDev->Allocated = TRUE;
switch ((Node->PciDev->VfPciBar[Node->Bar]).BarType) {
+ case PciBarTypeMem32:
+ case PciBarTypePMem32:
- case PciBarTypeMem32:
- case PciBarTypePMem32:
-
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->VfPciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->VfPciBar[Node->Bar]).Offset,
+ 1,
+ &Address
+ );
- Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
- break;
+ Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
+ break;
- case PciBarTypeMem64:
- case PciBarTypePMem64:
+ case PciBarTypeMem64:
+ case PciBarTypePMem64:
- Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
+ Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->VfPciBar[Node->Bar]).Offset,
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->VfPciBar[Node->Bar]).Offset,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 (Address, 32);
+ Address32 = (UINT32)RShiftU64 (Address, 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- ((Node->PciDev->VfPciBar[Node->Bar]).Offset + 4),
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ ((Node->PciDev->VfPciBar[Node->Bar]).Offset + 4),
+ 1,
+ &Address32
+ );
- Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
- break;
+ Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- break;
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ break;
- default:
- break;
+ default:
+ break;
}
return EFI_SUCCESS;
@@ -1440,24 +1434,24 @@ ProgramVfBar ( **/
VOID
ProgramPpbApperture (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT32 Address32;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT32 Address32;
Address = 0;
//
// If no device resource of this PPB, return anyway
// Aperture is set default in the initialization code
//
- if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {
+ if ((Node->Length == 0) || (Node->ResourceUsage == PciResUsagePadding)) {
//
// For padding resource node, just ignore when programming
//
- return ;
+ return;
}
PciIo = &(Node->PciDev->PciIo);
@@ -1469,174 +1463,173 @@ ProgramPpbApperture ( Node->PciDev->Allocated = TRUE;
switch (Node->Bar) {
+ case PPB_BAR_0:
+ case PPB_BAR_1:
+ switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ case PciBarTypeMem32:
+ case PciBarTypePMem32:
+
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address
+ );
- case PPB_BAR_0:
- case PPB_BAR_1:
- switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- case PciBarTypeMem32:
- case PciBarTypePMem32:
+ case PciBarTypeMem64:
+ case PciBarTypePMem64:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);
- case PciBarTypeMem64:
- case PciBarTypePMem64:
-
- Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address32
+ );
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address32
- );
+ Address32 = (UINT32)RShiftU64 (Address, 32);
- Address32 = (UINT32) RShiftU64 (Address, 32);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (UINT8)((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
+ 1,
+ &Address32
+ );
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
- 1,
- &Address32
- );
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ default:
+ break;
+ }
- default:
- break;
- }
- break;
+ break;
- case PPB_IO_RANGE:
+ case PPB_IO_RANGE:
- Address32 = ((UINT32) (Address)) >> 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint8,
- 0x1C,
- 1,
- &Address32
- );
+ Address32 = ((UINT32)(Address)) >> 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ 0x1C,
+ 1,
+ &Address32
+ );
- Address32 >>= 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x30,
- 1,
- &Address32
- );
+ Address32 >>= 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x30,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) (Address + Node->Length - 1);
- Address32 = ((UINT32) (Address32)) >> 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint8,
- 0x1D,
- 1,
- &Address32
- );
+ Address32 = (UINT32)(Address + Node->Length - 1);
+ Address32 = ((UINT32)(Address32)) >> 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ 0x1D,
+ 1,
+ &Address32
+ );
- Address32 >>= 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x32,
- 1,
- &Address32
- );
+ Address32 >>= 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x32,
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- case PPB_MEM32_RANGE:
+ case PPB_MEM32_RANGE:
- Address32 = ((UINT32) (Address)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x20,
- 1,
- &Address32
- );
+ Address32 = ((UINT32)(Address)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x20,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) (Address + Node->Length - 1);
- Address32 = ((UINT32) (Address32)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x22,
- 1,
- &Address32
- );
+ Address32 = (UINT32)(Address + Node->Length - 1);
+ Address32 = ((UINT32)(Address32)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x22,
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- case PPB_PMEM32_RANGE:
- case PPB_PMEM64_RANGE:
+ case PPB_PMEM32_RANGE:
+ case PPB_PMEM64_RANGE:
- Address32 = ((UINT32) (Address)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x24,
- 1,
- &Address32
- );
+ Address32 = ((UINT32)(Address)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x24,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) (Address + Node->Length - 1);
- Address32 = ((UINT32) (Address32)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x26,
- 1,
- &Address32
- );
+ Address32 = (UINT32)(Address + Node->Length - 1);
+ Address32 = ((UINT32)(Address32)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x26,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 (Address, 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- 0x28,
- 1,
- &Address32
- );
+ Address32 = (UINT32)RShiftU64 (Address, 32);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0x28,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- 0x2C,
- 1,
- &Address32
- );
+ Address32 = (UINT32)RShiftU64 ((Address + Node->Length - 1), 32);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0x2C,
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -1650,15 +1643,16 @@ ProgramPpbApperture ( **/
VOID
ProgramUpstreamBridgeForRom (
- IN PCI_IO_DEVICE *PciDevice,
- IN UINT32 OptionRomBase,
- IN BOOLEAN Enable
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINT32 OptionRomBase,
+ IN BOOLEAN Enable
)
{
- PCI_IO_DEVICE *Parent;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 Base;
- UINT16 Limit;
+ PCI_IO_DEVICE *Parent;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 Base;
+ UINT16 Limit;
+
//
// For root bridge, just return.
//
@@ -1677,9 +1671,9 @@ ProgramUpstreamBridgeForRom ( //
// Only cover MMIO for Option ROM.
//
- Base = (UINT16) (OptionRomBase >> 16);
- Limit = (UINT16) ((OptionRomBase + PciDevice->RomSize - 1) >> 16);
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
+ Base = (UINT16)(OptionRomBase >> 16);
+ Limit = (UINT16)((OptionRomBase + PciDevice->RomSize - 1) >> 16);
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), 1, &Limit);
PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);
@@ -1691,14 +1685,15 @@ ProgramUpstreamBridgeForRom ( //
// When devices under the bridge contains Option ROM and doesn't require 32bit MMIO.
//
- Base = (UINT16) gAllOne;
- Limit = (UINT16) gAllZero;
+ Base = (UINT16)gAllOne;
+ Limit = (UINT16)gAllZero;
} else {
- Base = (UINT16) ((UINT32) Parent->PciBar[PPB_MEM32_RANGE].BaseAddress >> 16);
- Limit = (UINT16) ((UINT32) (Parent->PciBar[PPB_MEM32_RANGE].BaseAddress
- + Parent->PciBar[PPB_MEM32_RANGE].Length - 1) >> 16);
+ Base = (UINT16)((UINT32)Parent->PciBar[PPB_MEM32_RANGE].BaseAddress >> 16);
+ Limit = (UINT16)((UINT32)(Parent->PciBar[PPB_MEM32_RANGE].BaseAddress
+ + Parent->PciBar[PPB_MEM32_RANGE].Length - 1) >> 16);
}
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
+
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), 1, &Limit);
PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);
@@ -1719,11 +1714,11 @@ ProgramUpstreamBridgeForRom ( **/
BOOLEAN
ResourceRequestExisted (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
if (Bridge != NULL) {
- if (!IsListEmpty (&Bridge->ChildList) || Bridge->Length != 0) {
+ if (!IsListEmpty (&Bridge->ChildList) || (Bridge->Length != 0)) {
return TRUE;
}
}
@@ -1741,8 +1736,8 @@ ResourceRequestExisted ( **/
VOID
InitializeResourcePool (
- IN OUT PCI_RESOURCE_NODE *ResourcePool,
- IN PCI_BAR_TYPE ResourceType
+ IN OUT PCI_RESOURCE_NODE *ResourcePool,
+ IN PCI_BAR_TYPE ResourceType
)
{
ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));
@@ -1759,17 +1754,16 @@ InitializeResourcePool ( **/
VOID
DestroyResourceTree (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- PCI_RESOURCE_NODE *Temp;
- LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Temp;
+ LIST_ENTRY *CurrentLink;
while (!IsListEmpty (&Bridge->ChildList)) {
-
CurrentLink = Bridge->ChildList.ForwardLink;
- Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
+ Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
ASSERT (Temp);
RemoveEntryList (CurrentLink);
@@ -1795,15 +1789,15 @@ DestroyResourceTree ( **/
VOID
ResourcePaddingForCardBusBridge (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
- PCI_RESOURCE_NODE *Node;
+ PCI_RESOURCE_NODE *Node;
Node = NULL;
@@ -1889,14 +1883,14 @@ ResourcePaddingForCardBusBridge ( **/
VOID
ProgramP2C (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT64 TempAddress;
- UINT16 BridgeControl;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT64 TempAddress;
+ UINT16 BridgeControl;
Address = 0;
PciIo = &(Node->PciDev->PciIo);
@@ -1912,205 +1906,200 @@ ProgramP2C ( Node->PciDev->Allocated = TRUE;
switch (Node->Bar) {
-
- case P2C_BAR_0:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
-
- case P2C_MEM_1:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_BASE_0,
- 1,
- &Address
- );
-
- TempAddress = Address + Node->Length - 1;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_LIMIT_0,
- 1,
- &TempAddress
- );
-
- if (Node->ResType == PciBarTypeMem32) {
- //
- // Set non-prefetchable bit
- //
- PciIo->Pci.Read (
+ case P2C_BAR_0:
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
1,
- &BridgeControl
+ &Address
);
- BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
+
+ case P2C_MEM_1:
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_BASE_0,
1,
- &BridgeControl
+ &Address
);
- } else {
- //
- // Set prefetchable bit
- //
- PciIo->Pci.Read (
+ TempAddress = Address + Node->Length - 1;
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_LIMIT_0,
1,
- &BridgeControl
+ &TempAddress
);
- BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ if (Node->ResType == PciBarTypeMem32) {
+ //
+ // Set non-prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ } else {
+ //
+ // Set prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ }
+
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
+
+ break;
+
+ case P2C_MEM_2:
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_BASE_1,
1,
- &BridgeControl
+ &Address
);
- }
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- break;
+ TempAddress = Address + Node->Length - 1;
- case P2C_MEM_2:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_BASE_1,
- 1,
- &Address
- );
-
- TempAddress = Address + Node->Length - 1;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_LIMIT_1,
+ 1,
+ &TempAddress
+ );
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_LIMIT_1,
- 1,
- &TempAddress
- );
+ if (Node->ResType == PciBarTypeMem32) {
+ //
+ // Set non-prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ } else {
+ //
+ // Set prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ }
- if (Node->ResType == PciBarTypeMem32) {
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
+ break;
- //
- // Set non-prefetchable bit
- //
- PciIo->Pci.Read (
+ case P2C_IO_1:
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_BASE_0_LOWER,
1,
- &BridgeControl
+ &Address
);
- BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);
+ TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_LIMIT_0_LOWER,
1,
- &BridgeControl
+ &TempAddress
);
- } else {
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- //
- // Set prefetchable bit
- //
- PciIo->Pci.Read (
+ break;
+
+ case P2C_IO_2:
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_BASE_1_LOWER,
1,
- &BridgeControl
+ &Address
);
- BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;
+ TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_LIMIT_1_LOWER,
1,
- &BridgeControl
+ &TempAddress
);
- }
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- break;
-
- case P2C_IO_1:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_BASE_0_LOWER,
- 1,
- &Address
- );
-
- TempAddress = Address + Node->Length - 1;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_LIMIT_0_LOWER,
- 1,
- &TempAddress
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
-
- break;
-
- case P2C_IO_2:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_BASE_1_LOWER,
- 1,
- &Address
- );
- TempAddress = Address + Node->Length - 1;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_LIMIT_1_LOWER,
- 1,
- &TempAddress
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -2127,34 +2116,32 @@ ProgramP2C ( **/
VOID
ApplyResourcePadding (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- PCI_RESOURCE_NODE *Node;
- UINT8 DummyBarIndex;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ PCI_RESOURCE_NODE *Node;
+ UINT8 DummyBarIndex;
DummyBarIndex = 0;
Ptr = PciDev->ResourcePaddingDescriptors;
- while (((EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr)->Desc != ACPI_END_TAG_DESCRIPTOR) {
-
- if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) {
+ while (((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Desc != ACPI_END_TAG_DESCRIPTOR) {
+ if ((Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_IO)) {
if (Ptr->AddrLen != 0) {
-
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypeIo16,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypeIo16,
+ PciResUsagePadding
+ );
InsertResourceNode (
IoNode,
Node
@@ -2165,23 +2152,21 @@ ApplyResourcePadding ( continue;
}
- if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
-
+ if ((Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM)) {
if (Ptr->AddrSpaceGranularity == 32) {
-
//
// prefetchable
//
if (Ptr->SpecificFlag == 0x6) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypePMem32,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypePMem32,
+ PciResUsagePadding
+ );
InsertResourceNode (
PMem32Node,
Node
@@ -2198,13 +2183,13 @@ ApplyResourcePadding ( if (Ptr->SpecificFlag == 0) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypeMem32,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypeMem32,
+ PciResUsagePadding
+ );
InsertResourceNode (
Mem32Node,
Node
@@ -2217,20 +2202,19 @@ ApplyResourcePadding ( }
if (Ptr->AddrSpaceGranularity == 64) {
-
//
// prefetchable
//
if (Ptr->SpecificFlag == 0x6) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypePMem64,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypePMem64,
+ PciResUsagePadding
+ );
InsertResourceNode (
PMem64Node,
Node
@@ -2247,13 +2231,13 @@ ApplyResourcePadding ( if (Ptr->SpecificFlag == 0) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypeMem64,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypeMem64,
+ PciResUsagePadding
+ );
InsertResourceNode (
Mem64Node,
Node
@@ -2280,13 +2264,12 @@ ApplyResourcePadding ( **/
VOID
GetResourcePaddingPpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
+ if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
if (PciIoDevice->ResourcePaddingDescriptors == NULL) {
GetResourcePaddingForHpb (PciIoDevice);
}
}
}
-
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h index 9f2de291ba..1527d4eafa 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h @@ -17,18 +17,18 @@ typedef enum { #define PCI_RESOURCE_SIGNATURE SIGNATURE_32 ('p', 'c', 'r', 'c')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- LIST_ENTRY ChildList;
- PCI_IO_DEVICE *PciDev;
- UINT64 Alignment;
- UINT64 Offset;
- UINT8 Bar;
- PCI_BAR_TYPE ResType;
- UINT64 Length;
- BOOLEAN Reserved;
- PCI_RESOURCE_USAGE ResourceUsage;
- BOOLEAN Virtual;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ LIST_ENTRY ChildList;
+ PCI_IO_DEVICE *PciDev;
+ UINT64 Alignment;
+ UINT64 Offset;
+ UINT8 Bar;
+ PCI_BAR_TYPE ResType;
+ UINT64 Length;
+ BOOLEAN Reserved;
+ PCI_RESOURCE_USAGE ResourceUsage;
+ BOOLEAN Virtual;
} PCI_RESOURCE_NODE;
#define RESOURCE_NODE_FROM_LINK(a) \
@@ -43,8 +43,8 @@ typedef struct { **/
VOID
SkipVGAAperture (
- OUT UINT64 *Start,
- IN UINT64 Length
+ OUT UINT64 *Start,
+ IN UINT64 Length
);
/**
@@ -56,8 +56,8 @@ SkipVGAAperture ( **/
VOID
SkipIsaAliasAperture (
- OUT UINT64 *Start,
- IN UINT64 Length
+ OUT UINT64 *Start,
+ IN UINT64 Length
);
/**
@@ -70,8 +70,8 @@ SkipIsaAliasAperture ( **/
VOID
InsertResourceNode (
- IN OUT PCI_RESOURCE_NODE *Bridge,
- IN PCI_RESOURCE_NODE *ResNode
+ IN OUT PCI_RESOURCE_NODE *Bridge,
+ IN PCI_RESOURCE_NODE *ResNode
);
/**
@@ -94,9 +94,9 @@ InsertResourceNode ( **/
VOID
MergeResourceTree (
- IN PCI_RESOURCE_NODE *Dst,
- IN PCI_RESOURCE_NODE *Res,
- IN BOOLEAN TypeMerge
+ IN PCI_RESOURCE_NODE *Dst,
+ IN PCI_RESOURCE_NODE *Res,
+ IN BOOLEAN TypeMerge
);
/**
@@ -108,7 +108,7 @@ MergeResourceTree ( **/
VOID
CalculateApertureIo16 (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -120,7 +120,7 @@ CalculateApertureIo16 ( **/
VOID
CalculateResourceAperture (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -136,12 +136,12 @@ CalculateResourceAperture ( **/
VOID
GetResourceFromDevice (
- IN PCI_IO_DEVICE *PciDev,
- IN OUT PCI_RESOURCE_NODE *IoNode,
- IN OUT PCI_RESOURCE_NODE *Mem32Node,
- IN OUT PCI_RESOURCE_NODE *PMem32Node,
- IN OUT PCI_RESOURCE_NODE *Mem64Node,
- IN OUT PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN OUT PCI_RESOURCE_NODE *IoNode,
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,
+ IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -160,12 +160,12 @@ GetResourceFromDevice ( **/
PCI_RESOURCE_NODE *
CreateResourceNode (
- IN PCI_IO_DEVICE *PciDev,
- IN UINT64 Length,
- IN UINT64 Alignment,
- IN UINT8 Bar,
- IN PCI_BAR_TYPE ResType,
- IN PCI_RESOURCE_USAGE ResUsage
+ IN PCI_IO_DEVICE *PciDev,
+ IN UINT64 Length,
+ IN UINT64 Alignment,
+ IN UINT8 Bar,
+ IN PCI_BAR_TYPE ResType,
+ IN PCI_RESOURCE_USAGE ResUsage
);
/**
@@ -184,12 +184,12 @@ CreateResourceNode ( **/
PCI_RESOURCE_NODE *
CreateVfResourceNode (
- IN PCI_IO_DEVICE *PciDev,
- IN UINT64 Length,
- IN UINT64 Alignment,
- IN UINT8 Bar,
- IN PCI_BAR_TYPE ResType,
- IN PCI_RESOURCE_USAGE ResUsage
+ IN PCI_IO_DEVICE *PciDev,
+ IN UINT64 Length,
+ IN UINT64 Alignment,
+ IN UINT8 Bar,
+ IN PCI_BAR_TYPE ResType,
+ IN PCI_RESOURCE_USAGE ResUsage
);
/**
@@ -206,12 +206,12 @@ CreateVfResourceNode ( **/
VOID
CreateResourceMap (
- IN PCI_IO_DEVICE *Bridge,
- IN OUT PCI_RESOURCE_NODE *IoNode,
- IN OUT PCI_RESOURCE_NODE *Mem32Node,
- IN OUT PCI_RESOURCE_NODE *PMem32Node,
- IN OUT PCI_RESOURCE_NODE *Mem64Node,
- IN OUT PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *Bridge,
+ IN OUT PCI_RESOURCE_NODE *IoNode,
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,
+ IN OUT PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -227,12 +227,12 @@ CreateResourceMap ( **/
VOID
ResourcePaddingPolicy (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -251,11 +251,11 @@ ResourcePaddingPolicy ( **/
VOID
DegradeResource (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -270,8 +270,8 @@ DegradeResource ( **/
BOOLEAN
BridgeSupportResourceDecode (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT32 Decode
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT32 Decode
);
/**
@@ -288,8 +288,8 @@ BridgeSupportResourceDecode ( **/
EFI_STATUS
ProgramResource (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Bridge
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -301,8 +301,8 @@ ProgramResource ( **/
VOID
ProgramBar (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
);
/**
@@ -314,8 +314,8 @@ ProgramBar ( **/
EFI_STATUS
ProgramVfBar (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
);
/**
@@ -327,8 +327,8 @@ ProgramVfBar ( **/
VOID
ProgramPpbApperture (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
);
/**
@@ -341,9 +341,9 @@ ProgramPpbApperture ( **/
VOID
ProgramUpstreamBridgeForRom (
- IN PCI_IO_DEVICE *PciDevice,
- IN UINT32 OptionRomBase,
- IN BOOLEAN Enable
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINT32 OptionRomBase,
+ IN BOOLEAN Enable
);
/**
@@ -357,7 +357,7 @@ ProgramUpstreamBridgeForRom ( **/
BOOLEAN
ResourceRequestExisted (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -370,8 +370,8 @@ ResourceRequestExisted ( **/
VOID
InitializeResourcePool (
- IN OUT PCI_RESOURCE_NODE *ResourcePool,
- IN PCI_BAR_TYPE ResourceType
+ IN OUT PCI_RESOURCE_NODE *ResourcePool,
+ IN PCI_BAR_TYPE ResourceType
);
/**
@@ -382,7 +382,7 @@ InitializeResourcePool ( **/
VOID
DestroyResourceTree (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
);
/**
@@ -398,12 +398,12 @@ DestroyResourceTree ( **/
VOID
ResourcePaddingForCardBusBridge (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -415,8 +415,8 @@ ResourcePaddingForCardBusBridge ( **/
VOID
ProgramP2C (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
);
/**
@@ -432,12 +432,12 @@ ProgramP2C ( **/
VOID
ApplyResourcePadding (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
);
/**
@@ -450,7 +450,7 @@ ApplyResourcePadding ( **/
VOID
GetResourcePaddingPpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c index 5575a364a1..5535bd3013 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c @@ -12,18 +12,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // PCI ROM image information
//
typedef struct {
- EFI_HANDLE ImageHandle;
- UINTN Seg;
- UINT8 Bus;
- UINT8 Dev;
- UINT8 Func;
- VOID *RomImage;
- UINT64 RomSize;
+ EFI_HANDLE ImageHandle;
+ UINTN Seg;
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Func;
+ VOID *RomImage;
+ UINT64 RomSize;
} PCI_ROM_IMAGE;
-UINTN mNumberOfPciRomImages = 0;
-UINTN mMaxNumberOfPciRomImages = 0;
-PCI_ROM_IMAGE *mRomImageTable = NULL;
+UINTN mNumberOfPciRomImages = 0;
+UINTN mMaxNumberOfPciRomImages = 0;
+PCI_ROM_IMAGE *mRomImageTable = NULL;
/**
Add the Rom Image to internal database for later PCI light enumeration.
@@ -47,20 +47,21 @@ PciRomAddImageMapping ( IN UINT64 RomSize
)
{
- UINTN Index;
- PCI_ROM_IMAGE *NewTable;
+ UINTN Index;
+ PCI_ROM_IMAGE *NewTable;
for (Index = 0; Index < mNumberOfPciRomImages; Index++) {
- if (mRomImageTable[Index].Seg == Seg &&
- mRomImageTable[Index].Bus == Bus &&
- mRomImageTable[Index].Dev == Dev &&
- mRomImageTable[Index].Func == Func) {
+ if ((mRomImageTable[Index].Seg == Seg) &&
+ (mRomImageTable[Index].Bus == Bus) &&
+ (mRomImageTable[Index].Dev == Dev) &&
+ (mRomImageTable[Index].Func == Func))
+ {
//
// Expect once RomImage and RomSize are recorded, they will be passed in
// later when updating ImageHandle
//
ASSERT ((mRomImageTable[Index].RomImage == NULL) || (RomImage == mRomImageTable[Index].RomImage));
- ASSERT ((mRomImageTable[Index].RomSize == 0 ) || (RomSize == mRomImageTable[Index].RomSize ));
+ ASSERT ((mRomImageTable[Index].RomSize == 0) || (RomSize == mRomImageTable[Index].RomSize));
break;
}
}
@@ -76,12 +77,13 @@ PciRomAddImageMapping ( mRomImageTable
);
if (NewTable == NULL) {
- return ;
+ return;
}
mRomImageTable = NewTable;
mMaxNumberOfPciRomImages += 0x20;
}
+
//
// Record the new PCI device
//
@@ -108,23 +110,24 @@ PciRomAddImageMapping ( **/
BOOLEAN
PciRomGetImageMapping (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- UINTN Index;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ UINTN Index;
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
for (Index = 0; Index < mNumberOfPciRomImages; Index++) {
- if (mRomImageTable[Index].Seg == PciRootBridgeIo->SegmentNumber &&
- mRomImageTable[Index].Bus == PciIoDevice->BusNumber &&
- mRomImageTable[Index].Dev == PciIoDevice->DeviceNumber &&
- mRomImageTable[Index].Func == PciIoDevice->FunctionNumber ) {
-
+ if ((mRomImageTable[Index].Seg == PciRootBridgeIo->SegmentNumber) &&
+ (mRomImageTable[Index].Bus == PciIoDevice->BusNumber) &&
+ (mRomImageTable[Index].Dev == PciIoDevice->DeviceNumber) &&
+ (mRomImageTable[Index].Func == PciIoDevice->FunctionNumber))
+ {
if (mRomImageTable[Index].ImageHandle != NULL) {
AddDriver (PciIoDevice, mRomImageTable[Index].ImageHandle, NULL);
}
+
PciIoDevice->PciIo.RomImage = mRomImageTable[Index].RomImage;
PciIoDevice->PciIo.RomSize = mRomImageTable[Index].RomSize;
return TRUE;
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h index 4c2a4e1988..f90b13a2a9 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h @@ -42,7 +42,7 @@ PciRomAddImageMapping ( **/
BOOLEAN
PciRomGetImageMapping (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 5c8f0f46a1..b20bcd310a 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -11,18 +11,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciRootBridge.h"
#include "PciHostResource.h"
-EFI_CPU_IO2_PROTOCOL *mCpuIo;
+EFI_CPU_IO2_PROTOCOL *mCpuIo;
-GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mAcpiAddressSpaceTypeStr[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mAcpiAddressSpaceTypeStr[] = {
L"Mem", L"I/O", L"Bus"
};
-GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] = {
L"I/O", L"Mem", L"PMem", L"Mem64", L"PMem64", L"Bus"
};
-EDKII_IOMMU_PROTOCOL *mIoMmu;
-EFI_EVENT mIoMmuEvent;
-VOID *mIoMmuRegistration;
+EDKII_IOMMU_PROTOCOL *mIoMmu;
+EFI_EVENT mIoMmuEvent;
+VOID *mIoMmuRegistration;
/**
This routine gets translation offset from a root bridge instance by resource type.
@@ -34,8 +34,8 @@ VOID *mIoMmuRegistration; **/
UINT64
GetTranslationByResourceType (
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
- IN PCI_RESOURCE_TYPE ResourceType
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
+ IN PCI_RESOURCE_TYPE ResourceType
)
{
switch (ResourceType) {
@@ -92,22 +92,24 @@ GetTranslationByResourceType ( **/
EFI_STATUS
IntersectIoDescriptor (
- IN UINT64 Base,
- IN UINT64 Length,
- IN CONST EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor
+ IN UINT64 Base,
+ IN UINT64 Length,
+ IN CONST EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor
)
{
- UINT64 IntersectionBase;
- UINT64 IntersectionEnd;
- EFI_STATUS Status;
+ UINT64 IntersectionBase;
+ UINT64 IntersectionEnd;
+ EFI_STATUS Status;
if (Descriptor->GcdIoType == EfiGcdIoTypeIo) {
return EFI_SUCCESS;
}
IntersectionBase = MAX (Base, Descriptor->BaseAddress);
- IntersectionEnd = MIN (Base + Length,
- Descriptor->BaseAddress + Descriptor->Length);
+ IntersectionEnd = MIN (
+ Base + Length,
+ Descriptor->BaseAddress + Descriptor->Length
+ );
if (IntersectionBase >= IntersectionEnd) {
//
// The descriptor and the aperture don't overlap.
@@ -116,19 +118,36 @@ IntersectIoDescriptor ( }
if (Descriptor->GcdIoType == EfiGcdIoTypeNonExistent) {
- Status = gDS->AddIoSpace (EfiGcdIoTypeIo, IntersectionBase,
- IntersectionEnd - IntersectionBase);
+ Status = gDS->AddIoSpace (
+ EfiGcdIoTypeIo,
+ IntersectionBase,
+ IntersectionEnd - IntersectionBase
+ );
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
- "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
- IntersectionBase, IntersectionEnd, Status));
+ DEBUG ((
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
+ "%a: %a: add [%Lx, %Lx): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ IntersectionBase,
+ IntersectionEnd,
+ Status
+ ));
return Status;
}
- DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u conflicts with "
- "aperture [%Lx, %Lx)\n", gEfiCallerBaseName, __FUNCTION__,
- Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
- (UINT32)Descriptor->GcdIoType, Base, Base + Length));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: desc [%Lx, %Lx) type %u conflicts with "
+ "aperture [%Lx, %Lx)\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Descriptor->BaseAddress,
+ Descriptor->BaseAddress + Descriptor->Length,
+ (UINT32)Descriptor->GcdIoType,
+ Base,
+ Base + Length
+ ));
return EFI_INVALID_PARAMETER;
}
@@ -144,19 +163,24 @@ IntersectIoDescriptor ( **/
EFI_STATUS
AddIoSpace (
- IN UINT64 Base,
- IN UINT64 Length
+ IN UINT64 Base,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINTN NumberOfDescriptors;
- EFI_GCD_IO_SPACE_DESCRIPTOR *IoSpaceMap;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_IO_SPACE_DESCRIPTOR *IoSpaceMap;
Status = gDS->GetIoSpaceMap (&NumberOfDescriptors, &IoSpaceMap);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %a: GetIoSpaceMap(): %r\n",
- gEfiCallerBaseName, __FUNCTION__, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: GetIoSpaceMap(): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Status
+ ));
return Status;
}
@@ -167,24 +191,26 @@ AddIoSpace ( }
}
- DEBUG_CODE_BEGIN ();
- //
- // Make sure there are adjacent descriptors covering [Base, Base + Length).
- // It is possible that they have not been merged; merging can be prevented
- // by allocation.
- //
- UINT64 CheckBase;
- EFI_STATUS CheckStatus;
- EFI_GCD_IO_SPACE_DESCRIPTOR Descriptor;
-
- for (CheckBase = Base;
- CheckBase < Base + Length;
- CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
- CheckStatus = gDS->GetIoSpaceDescriptor (CheckBase, &Descriptor);
- ASSERT_EFI_ERROR (CheckStatus);
- ASSERT (Descriptor.GcdIoType == EfiGcdIoTypeIo);
- }
- DEBUG_CODE_END ();
+ DEBUG_CODE_BEGIN ();
+ //
+ // Make sure there are adjacent descriptors covering [Base, Base + Length).
+ // It is possible that they have not been merged; merging can be prevented
+ // by allocation.
+ //
+ UINT64 CheckBase;
+ EFI_STATUS CheckStatus;
+ EFI_GCD_IO_SPACE_DESCRIPTOR Descriptor;
+
+ for (CheckBase = Base;
+ CheckBase < Base + Length;
+ CheckBase = Descriptor.BaseAddress + Descriptor.Length)
+ {
+ CheckStatus = gDS->GetIoSpaceDescriptor (CheckBase, &Descriptor);
+ ASSERT_EFI_ERROR (CheckStatus);
+ ASSERT (Descriptor.GcdIoType == EfiGcdIoTypeIo);
+ }
+
+ DEBUG_CODE_END ();
FreeIoSpaceMap:
FreePool (IoSpaceMap);
@@ -233,24 +259,27 @@ FreeIoSpaceMap: **/
EFI_STATUS
IntersectMemoryDescriptor (
- IN UINT64 Base,
- IN UINT64 Length,
- IN UINT64 Capabilities,
- IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
+ IN UINT64 Base,
+ IN UINT64 Length,
+ IN UINT64 Capabilities,
+ IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
)
{
- UINT64 IntersectionBase;
- UINT64 IntersectionEnd;
- EFI_STATUS Status;
+ UINT64 IntersectionBase;
+ UINT64 IntersectionEnd;
+ EFI_STATUS Status;
- if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&
- (Descriptor->Capabilities & Capabilities) == Capabilities) {
+ if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&
+ ((Descriptor->Capabilities & Capabilities) == Capabilities))
+ {
return EFI_SUCCESS;
}
IntersectionBase = MAX (Base, Descriptor->BaseAddress);
- IntersectionEnd = MIN (Base + Length,
- Descriptor->BaseAddress + Descriptor->Length);
+ IntersectionEnd = MIN (
+ Base + Length,
+ Descriptor->BaseAddress + Descriptor->Length
+ );
if (IntersectionBase >= IntersectionEnd) {
//
// The descriptor and the aperture don't overlap.
@@ -259,21 +288,39 @@ IntersectMemoryDescriptor ( }
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
- Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
- IntersectionBase, IntersectionEnd - IntersectionBase,
- Capabilities);
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ IntersectionBase,
+ IntersectionEnd - IntersectionBase,
+ Capabilities
+ );
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
- "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
- IntersectionBase, IntersectionEnd, Status));
+ DEBUG ((
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
+ "%a: %a: add [%Lx, %Lx): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ IntersectionBase,
+ IntersectionEnd,
+ Status
+ ));
return Status;
}
- DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
- "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,
- Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
- (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,
- Base, Base + Length, Capabilities));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
+ "with aperture [%Lx, %Lx) cap %Lx\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Descriptor->BaseAddress,
+ Descriptor->BaseAddress + Descriptor->Length,
+ (UINT32)Descriptor->GcdMemoryType,
+ Descriptor->Capabilities,
+ Base,
+ Base + Length,
+ Capabilities
+ ));
return EFI_INVALID_PARAMETER;
}
@@ -290,49 +337,60 @@ IntersectMemoryDescriptor ( **/
EFI_STATUS
AddMemoryMappedIoSpace (
- IN UINT64 Base,
- IN UINT64 Length,
- IN UINT64 Capabilities
+ IN UINT64 Base,
+ IN UINT64 Length,
+ IN UINT64 Capabilities
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINTN NumberOfDescriptors;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
- gEfiCallerBaseName, __FUNCTION__, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %a: GetMemorySpaceMap(): %r\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Status
+ ));
return Status;
}
for (Index = 0; Index < NumberOfDescriptors; Index++) {
- Status = IntersectMemoryDescriptor (Base, Length, Capabilities,
- &MemorySpaceMap[Index]);
+ Status = IntersectMemoryDescriptor (
+ Base,
+ Length,
+ Capabilities,
+ &MemorySpaceMap[Index]
+ );
if (EFI_ERROR (Status)) {
goto FreeMemorySpaceMap;
}
}
DEBUG_CODE_BEGIN ();
- //
- // Make sure there are adjacent descriptors covering [Base, Base + Length).
- // It is possible that they have not been merged; merging can be prevented
- // by allocation and different capabilities.
- //
- UINT64 CheckBase;
- EFI_STATUS CheckStatus;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
-
- for (CheckBase = Base;
- CheckBase < Base + Length;
- CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
- CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
- ASSERT_EFI_ERROR (CheckStatus);
- ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
- ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
- }
+ //
+ // Make sure there are adjacent descriptors covering [Base, Base + Length).
+ // It is possible that they have not been merged; merging can be prevented
+ // by allocation and different capabilities.
+ //
+ UINT64 CheckBase;
+ EFI_STATUS CheckStatus;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
+
+ for (CheckBase = Base;
+ CheckBase < Base + Length;
+ CheckBase = Descriptor.BaseAddress + Descriptor.Length)
+ {
+ CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
+ ASSERT_EFI_ERROR (CheckStatus);
+ ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
+ ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
+ }
+
DEBUG_CODE_END ();
FreeMemorySpaceMap:
@@ -351,14 +409,14 @@ FreeMemorySpaceMap: VOID
EFIAPI
IoMmuProtocolCallback (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
gBS->CloseEvent (mIoMmuEvent);
}
}
@@ -377,28 +435,28 @@ IoMmuProtocolCallback ( EFI_STATUS
EFIAPI
InitializePciHostBridge (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- PCI_ROOT_BRIDGE *RootBridges;
- UINTN RootBridgeCount;
- UINTN Index;
- PCI_ROOT_BRIDGE_APERTURE *MemApertures[4];
- UINTN MemApertureIndex;
- BOOLEAN ResourceAssigned;
- LIST_ENTRY *Link;
- UINT64 HostAddress;
+ EFI_STATUS Status;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_ROOT_BRIDGE *RootBridges;
+ UINTN RootBridgeCount;
+ UINTN Index;
+ PCI_ROOT_BRIDGE_APERTURE *MemApertures[4];
+ UINTN MemApertureIndex;
+ BOOLEAN ResourceAssigned;
+ LIST_ENTRY *Link;
+ UINT64 HostAddress;
RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount);
if ((RootBridges == NULL) || (RootBridgeCount == 0)) {
return EFI_UNSUPPORTED;
}
- Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) &mCpuIo);
+ Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&mCpuIo);
ASSERT_EFI_ERROR (Status);
//
@@ -407,10 +465,10 @@ InitializePciHostBridge ( HostBridge = AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE));
ASSERT (HostBridge != NULL);
- HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;
- HostBridge->CanRestarted = TRUE;
+ HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;
+ HostBridge->CanRestarted = TRUE;
InitializeListHead (&HostBridge->RootBridges);
- ResourceAssigned = FALSE;
+ ResourceAssigned = FALSE;
//
// Create Root Bridge Device Handle in this Host Bridge
@@ -439,8 +497,10 @@ InitializePciHostBridge ( // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
// For GCD resource manipulation, we need to use host address.
//
- HostAddress = TO_HOST_ADDRESS (RootBridges[Index].Io.Base,
- RootBridges[Index].Io.Translation);
+ HostAddress = TO_HOST_ADDRESS (
+ RootBridges[Index].Io.Base,
+ RootBridges[Index].Io.Translation
+ );
Status = AddIoSpace (
HostAddress,
@@ -478,8 +538,10 @@ InitializePciHostBridge ( // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
// For GCD resource manipulation, we need to use host address.
//
- HostAddress = TO_HOST_ADDRESS (MemApertures[MemApertureIndex]->Base,
- MemApertures[MemApertureIndex]->Translation);
+ HostAddress = TO_HOST_ADDRESS (
+ MemApertures[MemApertureIndex]->Base,
+ MemApertures[MemApertureIndex]->Translation
+ );
Status = AddMemoryMappedIoSpace (
HostAddress,
MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,
@@ -494,6 +556,7 @@ InitializePciHostBridge ( if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set EFI_MEMORY_UC to MMIO aperture - %r.\n", Status));
}
+
if (ResourceAssigned) {
Status = gDS->AllocateMemorySpace (
EfiGcdAllocateAddress,
@@ -508,6 +571,7 @@ InitializePciHostBridge ( }
}
}
+
//
// Insert Root Bridge Handle Instance
//
@@ -519,18 +583,19 @@ InitializePciHostBridge ( // PciHostBridgeResourceAllocation protocol.
//
if (!ResourceAssigned) {
- HostBridge->ResAlloc.NotifyPhase = NotifyPhase;
- HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;
- HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;
- HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;
- HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;
- HostBridge->ResAlloc.SubmitResources = SubmitResources;
+ HostBridge->ResAlloc.NotifyPhase = NotifyPhase;
+ HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;
+ HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;
+ HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;
+ HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;
+ HostBridge->ResAlloc.SubmitResources = SubmitResources;
HostBridge->ResAlloc.GetProposedResources = GetProposedResources;
HostBridge->ResAlloc.PreprocessController = PreprocessController;
Status = gBS->InstallMultipleProtocolInterfaces (
&HostBridge->Handle,
- &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid,
+ &HostBridge->ResAlloc,
NULL
);
ASSERT_EFI_ERROR (Status);
@@ -539,18 +604,22 @@ InitializePciHostBridge ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
RootBridge->RootBridgeIo.ParentHandle = HostBridge->Handle;
Status = gBS->InstallMultipleProtocolInterfaces (
&RootBridge->Handle,
- &gEfiDevicePathProtocolGuid, RootBridge->DevicePath,
- &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->RootBridgeIo,
+ &gEfiDevicePathProtocolGuid,
+ RootBridge->DevicePath,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ &RootBridge->RootBridgeIo,
NULL
);
ASSERT_EFI_ERROR (Status);
}
+
PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);
if (!EFI_ERROR (Status)) {
@@ -573,23 +642,24 @@ InitializePciHostBridge ( **/
VOID
ResourceConflict (
- IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- LIST_ENTRY *Link;
- UINTN RootBridgeCount;
- PCI_RESOURCE_TYPE Index;
- PCI_RES_NODE *ResAllocNode;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ LIST_ENTRY *Link;
+ UINTN RootBridgeCount;
+ PCI_RESOURCE_TYPE Index;
+ PCI_RES_NODE *ResAllocNode;
RootBridgeCount = 0;
for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridgeCount++;
}
@@ -602,61 +672,63 @@ ResourceConflict ( for (Link = GetFirstNode (&HostBridge->RootBridges), Descriptor = Resources
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
for (Index = TypeIo; Index < TypeMax; Index++) {
ResAllocNode = &RootBridge->ResAllocNode[Index];
- Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
Descriptor->AddrRangeMin = ResAllocNode->Base;
Descriptor->AddrRangeMax = ResAllocNode->Alignment;
Descriptor->AddrLen = ResAllocNode->Length;
Descriptor->SpecificFlag = 0;
switch (ResAllocNode->Type) {
+ case TypeIo:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ break;
+
+ case TypePMem32:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem32:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 32;
+ break;
+
+ case TypePMem64:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem64:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 64;
+ break;
+
+ case TypeBus:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
+ break;
- case TypeIo:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
- break;
-
- case TypePMem32:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem32:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 32;
- break;
-
- case TypePMem64:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem64:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 64;
- break;
-
- case TypeBus:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
- break;
-
- default:
- break;
+ default:
+ break;
}
Descriptor++;
}
+
//
// Terminate the root bridge resources.
//
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (End + 1);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(End + 1);
}
+
//
// Terminate the host bridge resources.
//
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
DEBUG ((DEBUG_ERROR, "Call PciHostBridgeResourceConflict().\n"));
@@ -679,14 +751,14 @@ ResourceConflict ( **/
UINT64
AllocateResource (
- BOOLEAN Mmio,
- UINT64 Length,
- UINTN BitsOfAlignment,
- UINT64 BaseAddress,
- UINT64 Limit
+ BOOLEAN Mmio,
+ UINT64 Length,
+ UINTN BitsOfAlignment,
+ UINT64 BaseAddress,
+ UINT64 Limit
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (BaseAddress < Limit) {
//
@@ -725,9 +797,11 @@ AllocateResource ( if (!EFI_ERROR (Status)) {
return BaseAddress;
}
+
BaseAddress += LShiftU64 (1, BitsOfAlignment);
}
}
+
return MAX_UINT64;
}
@@ -746,331 +820,374 @@ AllocateResource ( EFI_STATUS
EFIAPI
NotifyPhase (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
)
{
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- LIST_ENTRY *Link;
- EFI_PHYSICAL_ADDRESS BaseAddress;
- UINTN BitsOfAlignment;
- UINT64 Alignment;
- EFI_STATUS Status;
- EFI_STATUS ReturnStatus;
- PCI_RESOURCE_TYPE Index;
- PCI_RESOURCE_TYPE Index1;
- PCI_RESOURCE_TYPE Index2;
- BOOLEAN ResNodeHandled[TypeMax];
- UINT64 MaxAlignment;
- UINT64 Translation;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ LIST_ENTRY *Link;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINTN BitsOfAlignment;
+ UINT64 Alignment;
+ EFI_STATUS Status;
+ EFI_STATUS ReturnStatus;
+ PCI_RESOURCE_TYPE Index;
+ PCI_RESOURCE_TYPE Index1;
+ PCI_RESOURCE_TYPE Index2;
+ BOOLEAN ResNodeHandled[TypeMax];
+ UINT64 MaxAlignment;
+ UINT64 Translation;
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
switch (Phase) {
- case EfiPciHostBridgeBeginEnumeration:
- if (!HostBridge->CanRestarted) {
- return EFI_NOT_READY;
- }
- //
- // Reset Root Bridge
- //
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- for (Index = TypeIo; Index < TypeMax; Index++) {
- RootBridge->ResAllocNode[Index].Type = Index;
- RootBridge->ResAllocNode[Index].Base = 0;
- RootBridge->ResAllocNode[Index].Length = 0;
- RootBridge->ResAllocNode[Index].Status = ResNone;
-
- RootBridge->ResourceSubmitted = FALSE;
+ case EfiPciHostBridgeBeginEnumeration:
+ if (!HostBridge->CanRestarted) {
+ return EFI_NOT_READY;
}
- }
- HostBridge->CanRestarted = TRUE;
- break;
+ //
+ // Reset Root Bridge
+ //
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ for (Index = TypeIo; Index < TypeMax; Index++) {
+ RootBridge->ResAllocNode[Index].Type = Index;
+ RootBridge->ResAllocNode[Index].Base = 0;
+ RootBridge->ResAllocNode[Index].Length = 0;
+ RootBridge->ResAllocNode[Index].Status = ResNone;
+
+ RootBridge->ResourceSubmitted = FALSE;
+ }
+ }
- case EfiPciHostBridgeBeginBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- HostBridge->CanRestarted = FALSE;
- break;
+ HostBridge->CanRestarted = TRUE;
+ break;
- case EfiPciHostBridgeEndBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- break;
+ case EfiPciHostBridgeBeginBusAllocation:
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ HostBridge->CanRestarted = FALSE;
+ break;
- case EfiPciHostBridgeBeginResourceAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- break;
+ case EfiPciHostBridgeEndBusAllocation:
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ break;
- case EfiPciHostBridgeAllocateResources:
- ReturnStatus = EFI_SUCCESS;
+ case EfiPciHostBridgeBeginResourceAllocation:
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ break;
- //
- // Make sure the resource for all root bridges has been submitted.
- //
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- if (!RootBridge->ResourceSubmitted) {
- return EFI_NOT_READY;
- }
- }
+ case EfiPciHostBridgeAllocateResources:
+ ReturnStatus = EFI_SUCCESS;
- DEBUG ((DEBUG_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- for (Index = TypeIo; Index < TypeBus; Index++) {
- ResNodeHandled[Index] = FALSE;
+ //
+ // Make sure the resource for all root bridges has been submitted.
+ //
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ if (!RootBridge->ResourceSubmitted) {
+ return EFI_NOT_READY;
+ }
}
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- DEBUG ((DEBUG_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));
-
- for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {
- if (RootBridge->ResAllocNode[Index1].Status == ResNone) {
- ResNodeHandled[Index1] = TRUE;
- } else {
- //
- // Allocate the resource node with max alignment at first
- //
- MaxAlignment = 0;
- Index = TypeMax;
- for (Index2 = TypeIo; Index2 < TypeBus; Index2++) {
- if (ResNodeHandled[Index2]) {
- continue;
- }
- if (MaxAlignment <= RootBridge->ResAllocNode[Index2].Alignment) {
- MaxAlignment = RootBridge->ResAllocNode[Index2].Alignment;
- Index = Index2;
- }
- }
+ DEBUG ((DEBUG_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ ResNodeHandled[Index] = FALSE;
+ }
- ASSERT (Index < TypeMax);
- ResNodeHandled[Index] = TRUE;
- Alignment = RootBridge->ResAllocNode[Index].Alignment;
- BitsOfAlignment = LowBitSet64 (Alignment + 1);
- BaseAddress = MAX_UINT64;
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ DEBUG ((DEBUG_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));
- //
- // RESTRICTION: To simplify the situation, we require the alignment of
- // Translation must be larger than any BAR alignment in the same root
- // bridge, so that resource allocation alignment can be applied to
- // both device address and host address.
- //
- Translation = GetTranslationByResourceType (RootBridge, Index);
- if ((Translation & Alignment) != 0) {
- DEBUG ((DEBUG_ERROR, "[%a:%d] Translation %lx is not aligned to %lx!\n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Translation, Alignment
- ));
- ASSERT ((Translation & Alignment) == 0);
+ for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {
+ if (RootBridge->ResAllocNode[Index1].Status == ResNone) {
+ ResNodeHandled[Index1] = TRUE;
+ } else {
//
- // This may be caused by too large alignment or too small
- // Translation; pick the 1st possibility and return out of resource,
- // which can also go thru the same process for out of resource
- // outside the loop.
+ // Allocate the resource node with max alignment at first
//
- ReturnStatus = EFI_OUT_OF_RESOURCES;
- continue;
- }
+ MaxAlignment = 0;
+ Index = TypeMax;
+ for (Index2 = TypeIo; Index2 < TypeBus; Index2++) {
+ if (ResNodeHandled[Index2]) {
+ continue;
+ }
+
+ if (MaxAlignment <= RootBridge->ResAllocNode[Index2].Alignment) {
+ MaxAlignment = RootBridge->ResAllocNode[Index2].Alignment;
+ Index = Index2;
+ }
+ }
- switch (Index) {
- case TypeIo:
- //
- // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
- // For AllocateResource is manipulating GCD resource, we need to use
- // host address here.
- //
- BaseAddress = AllocateResource (
- FALSE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (15, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),
- RootBridge->Io.Translation),
- TO_HOST_ADDRESS (RootBridge->Io.Limit,
- RootBridge->Io.Translation)
- );
- break;
+ ASSERT (Index < TypeMax);
+ ResNodeHandled[Index] = TRUE;
+ Alignment = RootBridge->ResAllocNode[Index].Alignment;
+ BitsOfAlignment = LowBitSet64 (Alignment + 1);
+ BaseAddress = MAX_UINT64;
- case TypeMem64:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (63, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),
- RootBridge->MemAbove4G.Translation),
- TO_HOST_ADDRESS (RootBridge->MemAbove4G.Limit,
- RootBridge->MemAbove4G.Translation)
- );
- if (BaseAddress != MAX_UINT64) {
- break;
- }
//
- // If memory above 4GB is not available, try memory below 4GB
+ // RESTRICTION: To simplify the situation, we require the alignment of
+ // Translation must be larger than any BAR alignment in the same root
+ // bridge, so that resource allocation alignment can be applied to
+ // both device address and host address.
//
+ Translation = GetTranslationByResourceType (RootBridge, Index);
+ if ((Translation & Alignment) != 0) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a:%d] Translation %lx is not aligned to %lx!\n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Translation,
+ Alignment
+ ));
+ ASSERT ((Translation & Alignment) == 0);
+ //
+ // This may be caused by too large alignment or too small
+ // Translation; pick the 1st possibility and return out of resource,
+ // which can also go thru the same process for out of resource
+ // outside the loop.
+ //
+ ReturnStatus = EFI_OUT_OF_RESOURCES;
+ continue;
+ }
- case TypeMem32:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (31, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),
- RootBridge->Mem.Translation),
- TO_HOST_ADDRESS (RootBridge->Mem.Limit,
- RootBridge->Mem.Translation)
- );
- break;
+ switch (Index) {
+ case TypeIo:
+ //
+ // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
+ // For AllocateResource is manipulating GCD resource, we need to use
+ // host address here.
+ //
+ BaseAddress = AllocateResource (
+ FALSE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (15, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),
+ RootBridge->Io.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->Io.Limit,
+ RootBridge->Io.Translation
+ )
+ );
+ break;
+
+ case TypeMem64:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (63, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),
+ RootBridge->MemAbove4G.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->MemAbove4G.Limit,
+ RootBridge->MemAbove4G.Translation
+ )
+ );
+ if (BaseAddress != MAX_UINT64) {
+ break;
+ }
+
+ //
+ // If memory above 4GB is not available, try memory below 4GB
+ //
+
+ case TypeMem32:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (31, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),
+ RootBridge->Mem.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->Mem.Limit,
+ RootBridge->Mem.Translation
+ )
+ );
+ break;
+
+ case TypePMem64:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (63, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),
+ RootBridge->PMemAbove4G.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->PMemAbove4G.Limit,
+ RootBridge->PMemAbove4G.Translation
+ )
+ );
+ if (BaseAddress != MAX_UINT64) {
+ break;
+ }
+
+ //
+ // If memory above 4GB is not available, try memory below 4GB
+ //
+ case TypePMem32:
+ BaseAddress = AllocateResource (
+ TRUE,
+ RootBridge->ResAllocNode[Index].Length,
+ MIN (31, BitsOfAlignment),
+ TO_HOST_ADDRESS (
+ ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),
+ RootBridge->PMem.Translation
+ ),
+ TO_HOST_ADDRESS (
+ RootBridge->PMem.Limit,
+ RootBridge->PMem.Translation
+ )
+ );
+ break;
+
+ default:
+ ASSERT (FALSE);
+ break;
+ }
- case TypePMem64:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (63, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),
- RootBridge->PMemAbove4G.Translation),
- TO_HOST_ADDRESS (RootBridge->PMemAbove4G.Limit,
- RootBridge->PMemAbove4G.Translation)
- );
+ DEBUG ((
+ DEBUG_INFO,
+ " %s: Base/Length/Alignment = %lx/%lx/%lx - ",
+ mPciResourceTypeStr[Index],
+ BaseAddress,
+ RootBridge->ResAllocNode[Index].Length,
+ Alignment
+ ));
if (BaseAddress != MAX_UINT64) {
- break;
+ RootBridge->ResAllocNode[Index].Base = BaseAddress;
+ RootBridge->ResAllocNode[Index].Status = ResAllocated;
+ DEBUG ((DEBUG_INFO, "Success\n"));
+ } else {
+ ReturnStatus = EFI_OUT_OF_RESOURCES;
+ DEBUG ((DEBUG_ERROR, "Out Of Resource!\n"));
}
- //
- // If memory above 4GB is not available, try memory below 4GB
- //
- case TypePMem32:
- BaseAddress = AllocateResource (
- TRUE,
- RootBridge->ResAllocNode[Index].Length,
- MIN (31, BitsOfAlignment),
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),
- RootBridge->PMem.Translation),
- TO_HOST_ADDRESS (RootBridge->PMem.Limit,
- RootBridge->PMem.Translation)
- );
- break;
-
- default:
- ASSERT (FALSE);
- break;
- }
-
- DEBUG ((DEBUG_INFO, " %s: Base/Length/Alignment = %lx/%lx/%lx - ",
- mPciResourceTypeStr[Index], BaseAddress, RootBridge->ResAllocNode[Index].Length, Alignment));
- if (BaseAddress != MAX_UINT64) {
- RootBridge->ResAllocNode[Index].Base = BaseAddress;
- RootBridge->ResAllocNode[Index].Status = ResAllocated;
- DEBUG ((DEBUG_INFO, "Success\n"));
- } else {
- ReturnStatus = EFI_OUT_OF_RESOURCES;
- DEBUG ((DEBUG_ERROR, "Out Of Resource!\n"));
}
}
}
- }
- if (ReturnStatus == EFI_OUT_OF_RESOURCES) {
- ResourceConflict (HostBridge);
- }
+ if (ReturnStatus == EFI_OUT_OF_RESOURCES) {
+ ResourceConflict (HostBridge);
+ }
- //
- // Set resource to zero for nodes where allocation fails
- //
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridge->ResAllocNode[Index].Status != ResAllocated) {
- RootBridge->ResAllocNode[Index].Length = 0;
+ //
+ // Set resource to zero for nodes where allocation fails
+ //
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ if (RootBridge->ResAllocNode[Index].Status != ResAllocated) {
+ RootBridge->ResAllocNode[Index].Length = 0;
+ }
}
}
- }
- return ReturnStatus;
- case EfiPciHostBridgeSetResources:
- //
- // HostBridgeInstance->CanRestarted = FALSE;
- //
- break;
+ return ReturnStatus;
- case EfiPciHostBridgeFreeResources:
- //
- // HostBridgeInstance->CanRestarted = FALSE;
- //
- ReturnStatus = EFI_SUCCESS;
- for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridge->ResAllocNode[Index].Status == ResAllocated) {
- switch (Index) {
- case TypeIo:
- Status = gDS->FreeIoSpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
- }
- break;
+ case EfiPciHostBridgeSetResources:
+ //
+ // HostBridgeInstance->CanRestarted = FALSE;
+ //
+ break;
- case TypeMem32:
- case TypePMem32:
- case TypeMem64:
- case TypePMem64:
- Status = gDS->FreeMemorySpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
+ case EfiPciHostBridgeFreeResources:
+ //
+ // HostBridgeInstance->CanRestarted = FALSE;
+ //
+ ReturnStatus = EFI_SUCCESS;
+ for (Link = GetFirstNode (&HostBridge->RootBridges)
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ if (RootBridge->ResAllocNode[Index].Status == ResAllocated) {
+ switch (Index) {
+ case TypeIo:
+ Status = gDS->FreeIoSpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
+ if (EFI_ERROR (Status)) {
+ ReturnStatus = Status;
+ }
+
+ break;
+
+ case TypeMem32:
+ case TypePMem32:
+ case TypeMem64:
+ case TypePMem64:
+ Status = gDS->FreeMemorySpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);
+ if (EFI_ERROR (Status)) {
+ ReturnStatus = Status;
+ }
+
+ break;
+
+ default:
+ ASSERT (FALSE);
+ break;
}
- break;
- default:
- ASSERT (FALSE);
- break;
+ RootBridge->ResAllocNode[Index].Type = Index;
+ RootBridge->ResAllocNode[Index].Base = 0;
+ RootBridge->ResAllocNode[Index].Length = 0;
+ RootBridge->ResAllocNode[Index].Status = ResNone;
}
-
- RootBridge->ResAllocNode[Index].Type = Index;
- RootBridge->ResAllocNode[Index].Base = 0;
- RootBridge->ResAllocNode[Index].Length = 0;
- RootBridge->ResAllocNode[Index].Status = ResNone;
}
- }
- RootBridge->ResourceSubmitted = FALSE;
- }
+ RootBridge->ResourceSubmitted = FALSE;
+ }
- HostBridge->CanRestarted = TRUE;
- return ReturnStatus;
+ HostBridge->CanRestarted = TRUE;
+ return ReturnStatus;
- case EfiPciHostBridgeEndResourceAllocation:
- //
- // The resource allocation phase is completed. No specific action is required
- // here. This notification can be used to perform any chipset specific programming.
- //
- break;
+ case EfiPciHostBridgeEndResourceAllocation:
+ //
+ // The resource allocation phase is completed. No specific action is required
+ // here. This notification can be used to perform any chipset specific programming.
+ //
+ break;
- case EfiPciHostBridgeEndEnumeration:
- //
- // The Host Bridge Enumeration is completed. No specific action is required here.
- // This notification can be used to perform any chipset specific programming.
- //
- break;
+ case EfiPciHostBridgeEndEnumeration:
+ //
+ // The Host Bridge Enumeration is completed. No specific action is required here.
+ // This notification can be used to perform any chipset specific programming.
+ //
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
@@ -1095,8 +1212,8 @@ NotifyPhase ( EFI_STATUS
EFIAPI
GetNextRootBridge (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN OUT EFI_HANDLE *RootBridgeHandle
)
{
BOOLEAN ReturnNext;
@@ -1109,19 +1226,20 @@ GetNextRootBridge ( }
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
- ReturnNext = (BOOLEAN) (*RootBridgeHandle == NULL);
+ ReturnNext = (BOOLEAN)(*RootBridgeHandle == NULL);
for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (ReturnNext) {
*RootBridgeHandle = RootBridge->Handle;
return EFI_SUCCESS;
}
- ReturnNext = (BOOLEAN) (*RootBridgeHandle == RootBridge->Handle);
+ ReturnNext = (BOOLEAN)(*RootBridgeHandle == RootBridge->Handle);
}
if (ReturnNext) {
@@ -1151,9 +1269,9 @@ GetNextRootBridge ( EFI_STATUS
EFIAPI
GetAttributes (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT UINT64 *Attributes
)
{
LIST_ENTRY *Link;
@@ -1166,9 +1284,10 @@ GetAttributes ( HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
*Attributes = RootBridge->AllocationAttributes;
@@ -1196,16 +1315,16 @@ GetAttributes ( EFI_STATUS
EFIAPI
StartBusEnumeration (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
if (Configuration == NULL) {
return EFI_INVALID_PARAMETER;
@@ -1215,7 +1334,8 @@ StartBusEnumeration ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
*Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
@@ -1223,7 +1343,7 @@ StartBusEnumeration ( return EFI_OUT_OF_RESOURCES;
}
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) *Configuration;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)*Configuration;
Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
@@ -1235,8 +1355,8 @@ StartBusEnumeration ( Descriptor->AddrTranslationOffset = 0;
Descriptor->AddrLen = RootBridge->Bus.Limit - RootBridge->Bus.Base + 1;
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
return EFI_SUCCESS;
@@ -1262,23 +1382,23 @@ StartBusEnumeration ( EFI_STATUS
EFIAPI
SetBusNumbers (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
if (Configuration == NULL) {
return EFI_INVALID_PARAMETER;
}
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);
//
// Check the Configuration is valid
@@ -1286,7 +1406,8 @@ SetBusNumbers ( if ((Descriptor->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) ||
(Descriptor->ResType != ACPI_ADDRESS_SPACE_TYPE_BUS) ||
(End->Desc != ACPI_END_TAG_DESCRIPTOR)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1294,25 +1415,27 @@ SetBusNumbers ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
-
if (Descriptor->AddrLen == 0) {
return EFI_INVALID_PARAMETER;
}
if ((Descriptor->AddrRangeMin < RootBridge->Bus.Base) ||
(Descriptor->AddrRangeMin + Descriptor->AddrLen - 1 > RootBridge->Bus.Limit)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
+
//
// Update the Bus Range
//
- RootBridge->ResAllocNode[TypeBus].Base = Descriptor->AddrRangeMin;
- RootBridge->ResAllocNode[TypeBus].Length = Descriptor->AddrLen;
- RootBridge->ResAllocNode[TypeBus].Status = ResAllocated;
+ RootBridge->ResAllocNode[TypeBus].Base = Descriptor->AddrRangeMin;
+ RootBridge->ResAllocNode[TypeBus].Length = Descriptor->AddrLen;
+ RootBridge->ResAllocNode[TypeBus].Status = ResAllocated;
return EFI_SUCCESS;
}
}
@@ -1335,16 +1458,16 @@ SetBusNumbers ( EFI_STATUS
EFIAPI
SubmitResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- PCI_RESOURCE_TYPE Type;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ PCI_RESOURCE_TYPE Type;
//
// Check the input parameter: Configuration
@@ -1357,7 +1480,8 @@ SubmitResources ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
DEBUG ((DEBUG_INFO, "PciHostBridge: SubmitResources for %s\n", RootBridge->DevicePathStr));
@@ -1366,52 +1490,62 @@ SubmitResources ( // If the Configuration includes one or more invalid resource descriptors, all the resource
// descriptors are ignored and the function returns EFI_INVALID_PARAMETER.
//
- for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
if (Descriptor->ResType > ACPI_ADDRESS_SPACE_TYPE_BUS) {
return EFI_INVALID_PARAMETER;
}
- DEBUG ((DEBUG_INFO, " %s: Granularity/SpecificFlag = %ld / %02x%s\n",
- mAcpiAddressSpaceTypeStr[Descriptor->ResType], Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
- (Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0 ? L" (Prefetchable)" : L""
- ));
+ DEBUG ((
+ DEBUG_INFO,
+ " %s: Granularity/SpecificFlag = %ld / %02x%s\n",
+ mAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrSpaceGranularity,
+ Descriptor->SpecificFlag,
+ (Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0 ? L" (Prefetchable)" : L""
+ ));
DEBUG ((DEBUG_INFO, " Length/Alignment = 0x%lx / 0x%lx\n", Descriptor->AddrLen, Descriptor->AddrRangeMax));
switch (Descriptor->ResType) {
- case ACPI_ADDRESS_SPACE_TYPE_MEM:
- if (Descriptor->AddrSpaceGranularity != 32 && Descriptor->AddrSpaceGranularity != 64) {
- return EFI_INVALID_PARAMETER;
- }
- if (Descriptor->AddrSpaceGranularity == 32 && Descriptor->AddrLen >= SIZE_4GB) {
- return EFI_INVALID_PARAMETER;
- }
- //
- // If the PCI root bridge does not support separate windows for nonprefetchable and
- // prefetchable memory, then the PCI bus driver needs to include requests for
- // prefetchable memory in the nonprefetchable memory pool.
- //
- if (((RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) &&
- ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0)
- ) {
- return EFI_INVALID_PARAMETER;
- }
- case ACPI_ADDRESS_SPACE_TYPE_IO:
- //
- // Check aligment, it should be of the form 2^n-1
- //
- if (GetPowerOfTwo64 (Descriptor->AddrRangeMax + 1) != (Descriptor->AddrRangeMax + 1)) {
- return EFI_INVALID_PARAMETER;
- }
- break;
- default:
- ASSERT (FALSE);
- break;
+ case ACPI_ADDRESS_SPACE_TYPE_MEM:
+ if ((Descriptor->AddrSpaceGranularity != 32) && (Descriptor->AddrSpaceGranularity != 64)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Descriptor->AddrSpaceGranularity == 32) && (Descriptor->AddrLen >= SIZE_4GB)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // If the PCI root bridge does not support separate windows for nonprefetchable and
+ // prefetchable memory, then the PCI bus driver needs to include requests for
+ // prefetchable memory in the nonprefetchable memory pool.
+ //
+ if (((RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) &&
+ ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0)
+ )
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ case ACPI_ADDRESS_SPACE_TYPE_IO:
+ //
+ // Check aligment, it should be of the form 2^n-1
+ //
+ if (GetPowerOfTwo64 (Descriptor->AddrRangeMax + 1) != (Descriptor->AddrRangeMax + 1)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ break;
+ default:
+ ASSERT (FALSE);
+ break;
}
}
+
if (Descriptor->Desc != ACPI_END_TAG_DESCRIPTOR) {
return EFI_INVALID_PARAMETER;
}
- for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
if (Descriptor->AddrSpaceGranularity == 32) {
if ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0) {
@@ -1431,10 +1565,12 @@ SubmitResources ( ASSERT (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_IO);
Type = TypeIo;
}
+
RootBridge->ResAllocNode[Type].Length = Descriptor->AddrLen;
RootBridge->ResAllocNode[Type].Alignment = Descriptor->AddrRangeMax;
RootBridge->ResAllocNode[Type].Status = ResSubmitted;
}
+
RootBridge->ResourceSubmitted = TRUE;
return EFI_SUCCESS;
}
@@ -1461,26 +1597,27 @@ SubmitResources ( EFI_STATUS
EFIAPI
GetProposedResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
)
{
- LIST_ENTRY *Link;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- UINTN Index;
- UINTN Number;
- VOID *Buffer;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
- UINT64 ResStatus;
+ LIST_ENTRY *Link;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ UINTN Index;
+ UINTN Number;
+ VOID *Buffer;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ UINT64 ResStatus;
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
for (Link = GetFirstNode (&HostBridge->RootBridges)
- ; !IsNull (&HostBridge->RootBridges, Link)
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ ; !IsNull (&HostBridge->RootBridges, Link)
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
for (Index = 0, Number = 0; Index < TypeBus; Index++) {
@@ -1494,52 +1631,54 @@ GetProposedResources ( return EFI_OUT_OF_RESOURCES;
}
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Buffer;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Buffer;
for (Index = 0; Index < TypeBus; Index++) {
ResStatus = RootBridge->ResAllocNode[Index].Status;
if (ResStatus != ResNone) {
- Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
- Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;;
- Descriptor->GenFlag = 0;
+ Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ Descriptor->GenFlag = 0;
//
// AddrRangeMin in Resource Descriptor here should be device address
// instead of host address, or else PCI bus driver cannot set correct
// address into PCI BAR registers.
// Base in ResAllocNode is a host address, so conversion is needed.
//
- Descriptor->AddrRangeMin = TO_DEVICE_ADDRESS (RootBridge->ResAllocNode[Index].Base,
- GetTranslationByResourceType (RootBridge, Index));
+ Descriptor->AddrRangeMin = TO_DEVICE_ADDRESS (
+ RootBridge->ResAllocNode[Index].Base,
+ GetTranslationByResourceType (RootBridge, Index)
+ );
Descriptor->AddrRangeMax = 0;
Descriptor->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS;
Descriptor->AddrLen = RootBridge->ResAllocNode[Index].Length;
switch (Index) {
+ case TypeIo:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ break;
- case TypeIo:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
- break;
-
- case TypePMem32:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem32:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 32;
- break;
+ case TypePMem32:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem32:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 32;
+ break;
- case TypePMem64:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem64:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 64;
- break;
+ case TypePMem64:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem64:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 64;
+ break;
}
Descriptor++;
}
}
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
- End->Checksum = 0;
+
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;
+ End->Checksum = 0;
*Configuration = Buffer;
@@ -1567,17 +1706,17 @@ GetProposedResources ( EFI_STATUS
EFIAPI
PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
)
{
LIST_ENTRY *Link;
PCI_HOST_BRIDGE_INSTANCE *HostBridge;
PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- if ((UINT32) Phase > EfiPciBeforeResourceCollection) {
+ if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
return EFI_INVALID_PARAMETER;
}
@@ -1585,7 +1724,8 @@ PreprocessController ( for (Link = GetFirstNode (&HostBridge->RootBridges)
; !IsNull (&HostBridge->RootBridges, Link)
; Link = GetNextNode (&HostBridge->RootBridges, Link)
- ) {
+ )
+ {
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);
if (RootBridgeHandle == RootBridge->Handle) {
return EFI_SUCCESS;
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h index 755ab75b19..e7a30fd909 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_HOST_BRIDGE_H_
#define _PCI_HOST_BRIDGE_H_
-
#include <PiDxe.h>
#include <IndustryStandard/Acpi.h>
#include <Library/UefiDriverEntryPoint.h>
@@ -21,27 +20,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciRootBridge.h"
-#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('p', 'h', 'b', 'g')
+#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('p', 'h', 'b', 'g')
typedef struct {
- UINTN Signature;
- EFI_HANDLE Handle;
- LIST_ENTRY RootBridges;
- BOOLEAN CanRestarted;
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ LIST_ENTRY RootBridges;
+ BOOLEAN CanRestarted;
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
} PCI_HOST_BRIDGE_INSTANCE;
-#define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
+#define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
//
// Macros to translate device address to host address and vice versa. According
// to UEFI 2.7, device address = host address + translation offset.
//
-#define TO_HOST_ADDRESS(DeviceAddress,TranslationOffset) ((DeviceAddress) - (TranslationOffset))
-#define TO_DEVICE_ADDRESS(HostAddress,TranslationOffset) ((HostAddress) + (TranslationOffset))
+#define TO_HOST_ADDRESS(DeviceAddress, TranslationOffset) ((DeviceAddress) - (TranslationOffset))
+#define TO_DEVICE_ADDRESS(HostAddress, TranslationOffset) ((HostAddress) + (TranslationOffset))
//
// Driver Entry Point
//
+
/**
Entry point of this driver.
@@ -56,13 +56,14 @@ typedef struct { EFI_STATUS
EFIAPI
InitializePciHostBridge (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
);
//
// HostBridge Resource Allocation interface
//
+
/**
Enter a certain phase of the PCI enumeration process.
@@ -78,8 +79,8 @@ InitializePciHostBridge ( EFI_STATUS
EFIAPI
NotifyPhase (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -101,8 +102,8 @@ NotifyPhase ( EFI_STATUS
EFIAPI
GetNextRootBridge (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN OUT EFI_HANDLE *RootBridgeHandle
);
/**
@@ -124,9 +125,9 @@ GetNextRootBridge ( EFI_STATUS
EFIAPI
GetAttributes (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT UINT64 *Attributes
);
/**
@@ -146,9 +147,9 @@ GetAttributes ( EFI_STATUS
EFIAPI
StartBusEnumeration (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
);
/**
@@ -167,9 +168,9 @@ StartBusEnumeration ( EFI_STATUS
EFIAPI
SetBusNumbers (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
);
/**
@@ -188,9 +189,9 @@ SetBusNumbers ( EFI_STATUS
EFIAPI
SubmitResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
);
/**
@@ -211,9 +212,9 @@ SubmitResources ( EFI_STATUS
EFIAPI
GetProposedResources (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
);
/**
@@ -233,10 +234,10 @@ GetProposedResources ( EFI_STATUS
EFIAPI
PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
);
/**
@@ -246,7 +247,7 @@ PreprocessController ( **/
VOID
ResourceConflict (
- IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridge
);
/**
@@ -259,11 +260,11 @@ ResourceConflict ( **/
UINT64
GetTranslationByResourceType (
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
- IN PCI_RESOURCE_TYPE ResourceType
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
+ IN PCI_RESOURCE_TYPE ResourceType
);
-extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
-extern EDKII_IOMMU_PROTOCOL *mIoMmu;
+extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
+extern EDKII_IOMMU_PROTOCOL *mIoMmu;
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h index 0f5a17d55a..772f4b513f 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h @@ -6,15 +6,16 @@ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef _PCI_HOST_RESOURCE_H_
#define _PCI_HOST_RESOURCE_H_
#include <PiDxe.h>
-#define PCI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define PCI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
typedef enum {
- TypeIo = 0,
+ TypeIo = 0,
TypeMem32,
TypePMem32,
TypeMem64,
@@ -31,14 +32,14 @@ typedef enum { } RES_STATUS;
typedef struct {
- PCI_RESOURCE_TYPE Type;
+ PCI_RESOURCE_TYPE Type;
//
// Base is a host address
//
- UINT64 Base;
- UINT64 Length;
- UINT64 Alignment;
- RES_STATUS Status;
+ UINT64 Base;
+ UINT64 Length;
+ UINT64 Alignment;
+ RES_STATUS Status;
} PCI_RES_NODE;
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h index caa3faf00a..10a6200719 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h @@ -31,7 +31,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/TimerLib.h>
#include "PciHostResource.h"
-
typedef enum {
IoOperation,
MemOperation,
@@ -40,46 +39,46 @@ typedef enum { #define MAP_INFO_SIGNATURE SIGNATURE_32 ('_', 'm', 'a', 'p')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
- UINTN NumberOfBytes;
- UINTN NumberOfPages;
- EFI_PHYSICAL_ADDRESS HostAddress;
- EFI_PHYSICAL_ADDRESS MappedHostAddress;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
+ UINTN NumberOfBytes;
+ UINTN NumberOfPages;
+ EFI_PHYSICAL_ADDRESS HostAddress;
+ EFI_PHYSICAL_ADDRESS MappedHostAddress;
} MAP_INFO;
-#define MAP_INFO_FROM_LINK(a) CR (a, MAP_INFO, Link, MAP_INFO_SIGNATURE)
+#define MAP_INFO_FROM_LINK(a) CR (a, MAP_INFO, Link, MAP_INFO_SIGNATURE)
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('_', 'p', 'r', 'b')
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('_', 'p', 'r', 'b')
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- EFI_HANDLE Handle;
- UINT64 AllocationAttributes;
- UINT64 Attributes;
- UINT64 Supports;
- PCI_RES_NODE ResAllocNode[TypeMax];
- PCI_ROOT_BRIDGE_APERTURE Bus;
- PCI_ROOT_BRIDGE_APERTURE Io;
- PCI_ROOT_BRIDGE_APERTURE Mem;
- PCI_ROOT_BRIDGE_APERTURE PMem;
- PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
- PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
- BOOLEAN DmaAbove4G;
- BOOLEAN NoExtendedConfigSpace;
- VOID *ConfigBuffer;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- CHAR16 *DevicePathStr;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL RootBridgeIo;
-
- BOOLEAN ResourceSubmitted;
- LIST_ENTRY Maps;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ EFI_HANDLE Handle;
+ UINT64 AllocationAttributes;
+ UINT64 Attributes;
+ UINT64 Supports;
+ PCI_RES_NODE ResAllocNode[TypeMax];
+ PCI_ROOT_BRIDGE_APERTURE Bus;
+ PCI_ROOT_BRIDGE_APERTURE Io;
+ PCI_ROOT_BRIDGE_APERTURE Mem;
+ PCI_ROOT_BRIDGE_APERTURE PMem;
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
+ BOOLEAN DmaAbove4G;
+ BOOLEAN NoExtendedConfigSpace;
+ VOID *ConfigBuffer;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ CHAR16 *DevicePathStr;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL RootBridgeIo;
+
+ BOOLEAN ResourceSubmitted;
+ LIST_ENTRY Maps;
} PCI_ROOT_BRIDGE_INSTANCE;
-#define ROOT_BRIDGE_FROM_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, RootBridgeIo, PCI_ROOT_BRIDGE_SIGNATURE)
+#define ROOT_BRIDGE_FROM_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, RootBridgeIo, PCI_ROOT_BRIDGE_SIGNATURE)
-#define ROOT_BRIDGE_FROM_LINK(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
+#define ROOT_BRIDGE_FROM_LINK(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
/**
Construct the Pci Root Bridge instance.
@@ -91,12 +90,13 @@ typedef struct { **/
PCI_ROOT_BRIDGE_INSTANCE *
CreateRootBridge (
- IN PCI_ROOT_BRIDGE *Bridge
+ IN PCI_ROOT_BRIDGE *Bridge
);
//
// Protocol Member Function Prototypes
//
+
/**
Poll an address in memory mapped space until an exit condition is met
@@ -286,11 +286,11 @@ RootBridgeIoIoWrite ( EFI_STATUS
EFIAPI
RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
)
;
@@ -567,5 +567,5 @@ RootBridgeIoConfiguration ( )
;
-extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
+extern EFI_CPU_IO2_PROTOCOL *mCpuIo;
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 2f1bed853d..157a0ada80 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -13,12 +13,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define NO_MAPPING (VOID *) (UINTN) -1
-#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
+#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
//
// Lookup table for increment values based on transfer widths
//
-UINT8 mInStride[] = {
+UINT8 mInStride[] = {
1, // EfiPciWidthUint8
2, // EfiPciWidthUint16
4, // EfiPciWidthUint32
@@ -36,7 +36,7 @@ UINT8 mInStride[] = { //
// Lookup table for increment values based on transfer widths
//
-UINT8 mOutStride[] = {
+UINT8 mOutStride[] = {
1, // EfiPciWidthUint8
2, // EfiPciWidthUint16
4, // EfiPciWidthUint32
@@ -61,13 +61,13 @@ UINT8 mOutStride[] = { **/
PCI_ROOT_BRIDGE_INSTANCE *
CreateRootBridge (
- IN PCI_ROOT_BRIDGE *Bridge
+ IN PCI_ROOT_BRIDGE *Bridge
)
{
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- PCI_RESOURCE_TYPE Index;
- CHAR16 *DevicePathStr;
- PCI_ROOT_BRIDGE_APERTURE *Aperture;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_RESOURCE_TYPE Index;
+ CHAR16 *DevicePathStr;
+ PCI_ROOT_BRIDGE_APERTURE *Aperture;
DevicePathStr = NULL;
@@ -76,13 +76,19 @@ CreateRootBridge ( DEBUG ((DEBUG_INFO, " Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
DEBUG ((DEBUG_INFO, " DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
DEBUG ((DEBUG_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
- DEBUG ((DEBUG_INFO, " AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,
- (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
- (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
- ));
DEBUG ((
- DEBUG_INFO, " Bus: %lx - %lx Translation=%lx\n",
- Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation
+ DEBUG_INFO,
+ " AllocAttr: %lx (%s%s)\n",
+ Bridge->AllocationAttributes,
+ (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
+ (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
+ ));
+ DEBUG ((
+ DEBUG_INFO,
+ " Bus: %lx - %lx Translation=%lx\n",
+ Bridge->Bus.Base,
+ Bridge->Bus.Limit,
+ Bridge->Bus.Translation
));
//
// Translation for bus is not supported.
@@ -93,24 +99,39 @@ CreateRootBridge ( }
DEBUG ((
- DEBUG_INFO, " Io: %lx - %lx Translation=%lx\n",
- Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation
+ DEBUG_INFO,
+ " Io: %lx - %lx Translation=%lx\n",
+ Bridge->Io.Base,
+ Bridge->Io.Limit,
+ Bridge->Io.Translation
));
DEBUG ((
- DEBUG_INFO, " Mem: %lx - %lx Translation=%lx\n",
- Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation
+ DEBUG_INFO,
+ " Mem: %lx - %lx Translation=%lx\n",
+ Bridge->Mem.Base,
+ Bridge->Mem.Limit,
+ Bridge->Mem.Translation
));
DEBUG ((
- DEBUG_INFO, " MemAbove4G: %lx - %lx Translation=%lx\n",
- Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation
+ DEBUG_INFO,
+ " MemAbove4G: %lx - %lx Translation=%lx\n",
+ Bridge->MemAbove4G.Base,
+ Bridge->MemAbove4G.Limit,
+ Bridge->MemAbove4G.Translation
));
DEBUG ((
- DEBUG_INFO, " PMem: %lx - %lx Translation=%lx\n",
- Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation
+ DEBUG_INFO,
+ " PMem: %lx - %lx Translation=%lx\n",
+ Bridge->PMem.Base,
+ Bridge->PMem.Limit,
+ Bridge->PMem.Translation
));
DEBUG ((
- DEBUG_INFO, " PMemAbove4G: %lx - %lx Translation=%lx\n",
- Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation
+ DEBUG_INFO,
+ " PMemAbove4G: %lx - %lx Translation=%lx\n",
+ Bridge->PMemAbove4G.Base,
+ Bridge->PMemAbove4G.Limit,
+ Bridge->PMemAbove4G.Translation
));
//
@@ -122,18 +143,21 @@ CreateRootBridge ( return NULL;
}
}
+
if (RESOURCE_VALID (&Bridge->MemAbove4G)) {
ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
if (Bridge->MemAbove4G.Base < SIZE_4GB) {
return NULL;
}
}
+
if (RESOURCE_VALID (&Bridge->PMem)) {
ASSERT (Bridge->PMem.Limit < SIZE_4GB);
if (Bridge->PMem.Limit >= SIZE_4GB) {
return NULL;
}
}
+
if (RESOURCE_VALID (&Bridge->PMemAbove4G)) {
ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
@@ -174,17 +198,17 @@ CreateRootBridge ( RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));
ASSERT (RootBridge != NULL);
- RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
- RootBridge->Supports = Bridge->Supports;
- RootBridge->Attributes = Bridge->Attributes;
- RootBridge->DmaAbove4G = Bridge->DmaAbove4G;
+ RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
+ RootBridge->Supports = Bridge->Supports;
+ RootBridge->Attributes = Bridge->Attributes;
+ RootBridge->DmaAbove4G = Bridge->DmaAbove4G;
RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;
- RootBridge->AllocationAttributes = Bridge->AllocationAttributes;
- RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);
- RootBridge->DevicePathStr = DevicePathStr;
- RootBridge->ConfigBuffer = AllocatePool (
- TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
- );
+ RootBridge->AllocationAttributes = Bridge->AllocationAttributes;
+ RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);
+ RootBridge->DevicePathStr = DevicePathStr;
+ RootBridge->ConfigBuffer = AllocatePool (
+ TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
+ );
ASSERT (RootBridge->ConfigBuffer != NULL);
InitializeListHead (&RootBridge->Maps);
@@ -197,37 +221,40 @@ CreateRootBridge ( for (Index = TypeIo; Index < TypeMax; Index++) {
switch (Index) {
- case TypeBus:
- Aperture = &RootBridge->Bus;
- break;
- case TypeIo:
- Aperture = &RootBridge->Io;
- break;
- case TypeMem32:
- Aperture = &RootBridge->Mem;
- break;
- case TypeMem64:
- Aperture = &RootBridge->MemAbove4G;
- break;
- case TypePMem32:
- Aperture = &RootBridge->PMem;
- break;
- case TypePMem64:
- Aperture = &RootBridge->PMemAbove4G;
- break;
- default:
- ASSERT (FALSE);
- Aperture = NULL;
- break;
+ case TypeBus:
+ Aperture = &RootBridge->Bus;
+ break;
+ case TypeIo:
+ Aperture = &RootBridge->Io;
+ break;
+ case TypeMem32:
+ Aperture = &RootBridge->Mem;
+ break;
+ case TypeMem64:
+ Aperture = &RootBridge->MemAbove4G;
+ break;
+ case TypePMem32:
+ Aperture = &RootBridge->PMem;
+ break;
+ case TypePMem64:
+ Aperture = &RootBridge->PMemAbove4G;
+ break;
+ default:
+ ASSERT (FALSE);
+ Aperture = NULL;
+ break;
}
- RootBridge->ResAllocNode[Index].Type = Index;
+
+ RootBridge->ResAllocNode[Index].Type = Index;
if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {
//
// Base in ResAllocNode is a host address, while Base in Aperture is a
// device address.
//
- RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (Aperture->Base,
- Aperture->Translation);
+ RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (
+ Aperture->Base,
+ Aperture->Translation
+ );
RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;
RootBridge->ResAllocNode[Index].Status = ResAllocated;
} else {
@@ -325,7 +352,7 @@ RootBridgeIoCheckParameter ( //
// Check to see if Width is in the valid range
//
- if ((UINT32) Width >= EfiPciWidthMaximum) {
+ if ((UINT32)Width >= EfiPciWidthMaximum) {
return EFI_INVALID_PARAMETER;
}
@@ -333,11 +360,11 @@ RootBridgeIoCheckParameter ( // For FIFO type, the device address won't increase during the access,
// so treat Count as 1
//
- if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+ if ((Width >= EfiPciWidthFifoUint8) && (Width <= EfiPciWidthFifoUint64)) {
Count = 1;
}
- Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);
Size = 1 << Width;
//
@@ -382,23 +409,26 @@ RootBridgeIoCheckParameter ( //
if (Address + Length <= 0x1000) {
if ((RootBridge->Attributes & (
- EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
- EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
- EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0) {
+ EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
+ EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0)
+ {
return EFI_SUCCESS;
}
}
- Base = RootBridge->Io.Base;
+
+ Base = RootBridge->Io.Base;
Limit = RootBridge->Io.Limit;
} else if (OperationType == MemOperation) {
//
// Allow Legacy MMIO access
//
- if ((Address >= 0xA0000) && (Address + Length) <= 0xC0000) {
+ if ((Address >= 0xA0000) && ((Address + Length) <= 0xC0000)) {
if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
return EFI_SUCCESS;
}
}
+
//
// By comparing the Address against Limit we know which range to be used
// for checking
@@ -417,14 +447,16 @@ RootBridgeIoCheckParameter ( Limit = RootBridge->PMemAbove4G.Limit;
}
} else {
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
- if (PciRbAddr->Bus < RootBridge->Bus.Base ||
- PciRbAddr->Bus > RootBridge->Bus.Limit) {
+ PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&Address;
+ if ((PciRbAddr->Bus < RootBridge->Bus.Base) ||
+ (PciRbAddr->Bus > RootBridge->Bus.Limit))
+ {
return EFI_INVALID_PARAMETER;
}
- if (PciRbAddr->Device > PCI_MAX_DEVICE ||
- PciRbAddr->Function > PCI_MAX_FUNC) {
+ if ((PciRbAddr->Device > PCI_MAX_DEVICE) ||
+ (PciRbAddr->Function > PCI_MAX_FUNC))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -433,12 +465,13 @@ RootBridgeIoCheckParameter ( } else {
Address = PciRbAddr->Register;
}
- Base = 0;
+
+ Base = 0;
Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;
}
if (Address < Base) {
- return EFI_INVALID_PARAMETER;
+ return EFI_INVALID_PARAMETER;
}
if (Address + Length > Limit + 1) {
@@ -462,18 +495,18 @@ RootBridgeIoCheckParameter ( **/
EFI_STATUS
RootBridgeIoGetMemTranslationByAddress (
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
- IN UINT64 Address,
- IN OUT UINT64 *Translation
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,
+ IN UINT64 Address,
+ IN OUT UINT64 *Translation
)
{
- if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) {
+ if ((Address >= RootBridge->Mem.Base) && (Address <= RootBridge->Mem.Limit)) {
*Translation = RootBridge->Mem.Translation;
- } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) {
+ } else if ((Address >= RootBridge->PMem.Base) && (Address <= RootBridge->PMem.Limit)) {
*Translation = RootBridge->PMem.Translation;
- } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) {
+ } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address <= RootBridge->MemAbove4G.Limit)) {
*Translation = RootBridge->MemAbove4G.Translation;
- } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) {
+ } else if ((Address >= RootBridge->PMemAbove4G.Base) && (Address <= RootBridge->PMemAbove4G.Limit)) {
*Translation = RootBridge->PMemAbove4G.Translation;
} else {
return EFI_INVALID_PARAMETER;
@@ -495,15 +528,16 @@ RootBridgeIoGetMemTranslationByAddress ( **/
UINT64
MultThenDivU64x64x32 (
- IN UINT64 Multiplicand,
- IN UINT64 Multiplier,
- IN UINT32 Divisor,
- OUT UINT32 *Remainder OPTIONAL
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
)
{
- UINT64 Uint64;
- UINT32 LocalRemainder;
- UINT32 Uint32;
+ UINT64 Uint64;
+ UINT32 LocalRemainder;
+ UINT32 Uint32;
+
if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) {
//
// Make sure Multiplicand is the bigger one.
@@ -513,6 +547,7 @@ MultThenDivU64x64x32 ( Multiplicand = Multiplier;
Multiplier = Uint64;
}
+
//
// Because Multiplicand * Multiplier overflows,
// Multiplicand * Multiplier / Divisor
@@ -525,6 +560,7 @@ MultThenDivU64x64x32 ( if ((Multiplicand & 0x1) == 1) {
Uint64 += DivU64x32Remainder (Multiplier, Divisor, &Uint32);
}
+
return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder, 1), Divisor, Remainder);
} else {
return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divisor, Remainder);
@@ -553,7 +589,7 @@ GetElapsedTick ( UINT64 PreviousTick;
PreviousTick = *CurrentTick;
- *CurrentTick = GetPerformanceCounter();
+ *CurrentTick = GetPerformanceCounter ();
if (StartTick < EndTick) {
return *CurrentTick - PreviousTick;
} else {
@@ -638,20 +674,21 @@ RootBridgeIoPollMem ( if (Delay == 0) {
return EFI_SUCCESS;
-
} else {
//
// NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
//
Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);
- NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
- if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
+ NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);
+ if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {
NumberOfTicks++;
}
- for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
- ; ElapsedTick <= NumberOfTicks
- ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
- ) {
+
+ for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()
+ ; ElapsedTick <= NumberOfTicks
+ ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
+ )
+ {
Status = This->Mem.Read (This, Width, Address, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
@@ -662,6 +699,7 @@ RootBridgeIoPollMem ( }
}
}
+
return EFI_TIMEOUT;
}
@@ -734,26 +772,28 @@ RootBridgeIoPollIo ( if (EFI_ERROR (Status)) {
return Status;
}
+
if ((*Result & Mask) == Value) {
return EFI_SUCCESS;
}
if (Delay == 0) {
return EFI_SUCCESS;
-
} else {
//
// NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
//
Frequency = GetPerformanceCounterProperties (&StartTick, &EndTick);
- NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
- if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
+ NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);
+ if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {
NumberOfTicks++;
}
- for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
- ; ElapsedTick <= NumberOfTicks
- ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
- ) {
+
+ for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()
+ ; ElapsedTick <= NumberOfTicks
+ ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
+ )
+ {
Status = This->Io.Read (This, Width, Address, 1, Result);
if (EFI_ERROR (Status)) {
return Status;
@@ -764,6 +804,7 @@ RootBridgeIoPollIo ( }
}
}
+
return EFI_TIMEOUT;
}
@@ -804,26 +845,37 @@ RootBridgeIoMemRead ( OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- UINT64 Translation;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ UINT64 Translation;
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
- Count, Buffer);
+ Status = RootBridgeIoCheckParameter (
+ This,
+ MemOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
+ );
if (EFI_ERROR (Status)) {
return Status;
}
RootBridge = ROOT_BRIDGE_FROM_THIS (This);
- Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
+ Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
if (EFI_ERROR (Status)) {
return Status;
}
// Address passed to CpuIo->Mem.Read needs to be a host address instead of
// device address.
- return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
+ return mCpuIo->Mem.Read (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -863,26 +915,37 @@ RootBridgeIoMemWrite ( IN VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- UINT64 Translation;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ UINT64 Translation;
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
- Count, Buffer);
+ Status = RootBridgeIoCheckParameter (
+ This,
+ MemOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
+ );
if (EFI_ERROR (Status)) {
return Status;
}
RootBridge = ROOT_BRIDGE_FROM_THIS (This);
- Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
+ Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
if (EFI_ERROR (Status)) {
return Status;
}
// Address passed to CpuIo->Mem.Write needs to be a host address instead of
// device address.
- return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
+ return mCpuIo->Mem.Write (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -916,12 +979,16 @@ RootBridgeIoIoRead ( OUT VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
Status = RootBridgeIoCheckParameter (
- This, IoOperation, Width,
- Address, Count, Buffer
+ This,
+ IoOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
);
if (EFI_ERROR (Status)) {
return Status;
@@ -931,8 +998,13 @@ RootBridgeIoIoRead ( // Address passed to CpuIo->Io.Read needs to be a host address instead of
// device address.
- return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
+ return mCpuIo->Io.Read (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -959,19 +1031,23 @@ RootBridgeIoIoRead ( EFI_STATUS
EFIAPI
RootBridgeIoIoWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
Status = RootBridgeIoCheckParameter (
- This, IoOperation, Width,
- Address, Count, Buffer
+ This,
+ IoOperation,
+ Width,
+ Address,
+ Count,
+ Buffer
);
if (EFI_ERROR (Status)) {
return Status;
@@ -981,8 +1057,13 @@ RootBridgeIoIoWrite ( // Address passed to CpuIo->Io.Write needs to be a host address instead of
// device address.
- return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
- TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
+ return mCpuIo->Io.Write (
+ mCpuIo,
+ (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
+ TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),
+ Count,
+ Buffer
+ );
}
/**
@@ -1019,11 +1100,11 @@ RootBridgeIoIoWrite ( EFI_STATUS
EFIAPI
RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
)
{
EFI_STATUS Status;
@@ -1032,7 +1113,7 @@ RootBridgeIoCopyMem ( UINTN Index;
UINT64 Result;
- if ((UINT32) Width > EfiPciWidthUint64) {
+ if ((UINT32)Width > EfiPciWidthUint64) {
return EFI_INVALID_PARAMETER;
}
@@ -1040,13 +1121,14 @@ RootBridgeIoCopyMem ( return EFI_SUCCESS;
}
- Stride = (UINTN) (1 << Width);
+ Stride = (UINTN)(1 << Width);
Forward = TRUE;
if ((DestAddress > SrcAddress) &&
- (DestAddress < (SrcAddress + Count * Stride))) {
- Forward = FALSE;
- SrcAddress = SrcAddress + (Count - 1) * Stride;
+ (DestAddress < (SrcAddress + Count * Stride)))
+ {
+ Forward = FALSE;
+ SrcAddress = SrcAddress + (Count - 1) * Stride;
DestAddress = DestAddress + (Count - 1) * Stride;
}
@@ -1061,6 +1143,7 @@ RootBridgeIoCopyMem ( if (EFI_ERROR (Status)) {
return Status;
}
+
Status = RootBridgeIoMemWrite (
This,
Width,
@@ -1071,18 +1154,19 @@ RootBridgeIoCopyMem ( if (EFI_ERROR (Status)) {
return Status;
}
+
if (Forward) {
- SrcAddress += Stride;
+ SrcAddress += Stride;
DestAddress += Stride;
} else {
- SrcAddress -= Stride;
+ SrcAddress -= Stride;
DestAddress -= Stride;
}
}
+
return EFI_SUCCESS;
}
-
/**
PCI configuration space access.
@@ -1101,12 +1185,12 @@ RootBridgeIoCopyMem ( EFI_STATUS
EFIAPI
RootBridgeIoPciAccess (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Read,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN BOOLEAN Read,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
@@ -1145,7 +1229,7 @@ RootBridgeIoPciAccess ( //
InStride = mInStride[Width];
OutStride = mOutStride[Width];
- Size = (UINTN) (1 << (Width & 0x03));
+ Size = (UINTN)(1 << (Width & 0x03));
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (Read) {
PciSegmentReadBuffer (Address, Size, Uint8Buffer);
@@ -1153,6 +1237,7 @@ RootBridgeIoPciAccess ( PciSegmentWriteBuffer (Address, Size, Uint8Buffer);
}
}
+
return EFI_SUCCESS;
}
@@ -1173,11 +1258,11 @@ RootBridgeIoPciAccess ( EFI_STATUS
EFIAPI
RootBridgeIoPciRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);
@@ -1200,11 +1285,11 @@ RootBridgeIoPciRead ( EFI_STATUS
EFIAPI
RootBridgeIoPciWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
)
{
return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);
@@ -1242,20 +1327,21 @@ RootBridgeIoMap ( OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
- MAP_INFO *MapInfo;
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;
+ MAP_INFO *MapInfo;
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
- Mapping == NULL) {
+ if ((HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) ||
+ (Mapping == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
//
// Make sure that Operation is valid
//
- if ((UINT32) Operation >= EfiPciOperationMaximum) {
+ if ((UINT32)Operation >= EfiPciOperationMaximum) {
return EFI_INVALID_PARAMETER;
}
@@ -1267,12 +1353,13 @@ RootBridgeIoMap ( // Clear 64bit support
//
if (Operation > EfiPciOperationBusMasterCommonBuffer) {
- Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - EfiPciOperationBusMasterRead64);
+ Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation - EfiPciOperationBusMasterRead64);
}
}
+
Status = mIoMmu->Map (
mIoMmu,
- (EDKII_IOMMU_OPERATION) Operation,
+ (EDKII_IOMMU_OPERATION)Operation,
HostAddress,
NumberOfBytes,
DeviceAddress,
@@ -1281,21 +1368,22 @@ RootBridgeIoMap ( return Status;
}
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
+ PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
if ((!RootBridge->DmaAbove4G ||
- (Operation != EfiPciOperationBusMasterRead64 &&
- Operation != EfiPciOperationBusMasterWrite64 &&
- Operation != EfiPciOperationBusMasterCommonBuffer64)) &&
- ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) {
-
+ ((Operation != EfiPciOperationBusMasterRead64) &&
+ (Operation != EfiPciOperationBusMasterWrite64) &&
+ (Operation != EfiPciOperationBusMasterCommonBuffer64))) &&
+ ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB))
+ {
//
// If the root bridge or the device cannot handle performing DMA above
// 4GB but any part of the DMA transfer being mapped is above 4GB, then
// map the DMA transfer to a buffer below 4GB.
//
- if (Operation == EfiPciOperationBusMasterCommonBuffer ||
- Operation == EfiPciOperationBusMasterCommonBuffer64) {
+ if ((Operation == EfiPciOperationBusMasterCommonBuffer) ||
+ (Operation == EfiPciOperationBusMasterCommonBuffer64))
+ {
//
// Common Buffer operations can not be remapped. If the common buffer
// if above 4GB, then it is not possible to generate a mapping, so return
@@ -1344,11 +1432,12 @@ RootBridgeIoMap ( // then copy the contents of the real buffer into the mapped buffer
// so the Bus Master can read the contents of the real buffer.
//
- if (Operation == EfiPciOperationBusMasterRead ||
- Operation == EfiPciOperationBusMasterRead64) {
+ if ((Operation == EfiPciOperationBusMasterRead) ||
+ (Operation == EfiPciOperationBusMasterRead64))
+ {
CopyMem (
- (VOID *) (UINTN) MapInfo->MappedHostAddress,
- (VOID *) (UINTN) MapInfo->HostAddress,
+ (VOID *)(UINTN)MapInfo->MappedHostAddress,
+ (VOID *)(UINTN)MapInfo->HostAddress,
MapInfo->NumberOfBytes
);
}
@@ -1362,7 +1451,7 @@ RootBridgeIoMap ( //
// Return a pointer to the MAP_INFO structure in Mapping
//
- *Mapping = MapInfo;
+ *Mapping = MapInfo;
} else {
//
// If the root bridge CAN handle performing DMA above 4GB or
@@ -1400,9 +1489,9 @@ RootBridgeIoUnmap ( IN VOID *Mapping
)
{
- MAP_INFO *MapInfo;
- LIST_ENTRY *Link;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ MAP_INFO *MapInfo;
+ LIST_ENTRY *Link;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
EFI_STATUS Status;
if (mIoMmu != NULL) {
@@ -1428,18 +1517,21 @@ RootBridgeIoUnmap ( for (Link = GetFirstNode (&RootBridge->Maps)
; !IsNull (&RootBridge->Maps, Link)
; Link = GetNextNode (&RootBridge->Maps, Link)
- ) {
+ )
+ {
MapInfo = MAP_INFO_FROM_LINK (Link);
if (MapInfo == Mapping) {
break;
}
}
+
//
// Mapping is not a valid value returned by Map()
//
if (MapInfo != Mapping) {
return EFI_INVALID_PARAMETER;
}
+
RemoveEntryList (&MapInfo->Link);
//
@@ -1447,11 +1539,12 @@ RootBridgeIoUnmap ( // then copy the contents of the mapped buffer into the real buffer
// so the processor can read the contents of the real buffer.
//
- if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
- MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
+ if ((MapInfo->Operation == EfiPciOperationBusMasterWrite) ||
+ (MapInfo->Operation == EfiPciOperationBusMasterWrite64))
+ {
CopyMem (
- (VOID *) (UINTN) MapInfo->HostAddress,
- (VOID *) (UINTN) MapInfo->MappedHostAddress,
+ (VOID *)(UINTN)MapInfo->HostAddress,
+ (VOID *)(UINTN)MapInfo->MappedHostAddress,
MapInfo->NumberOfBytes
);
}
@@ -1524,8 +1617,9 @@ RootBridgeIoAllocateBuffer ( // The only valid memory types are EfiBootServicesData and
// EfiRuntimeServicesData
//
- if (MemoryType != EfiBootServicesData &&
- MemoryType != EfiRuntimeServicesData) {
+ if ((MemoryType != EfiBootServicesData) &&
+ (MemoryType != EfiRuntimeServicesData))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1536,8 +1630,9 @@ RootBridgeIoAllocateBuffer ( //
// Clear DUAL_ADDRESS_CYCLE
//
- Attributes &= ~((UINT64) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
+ Attributes &= ~((UINT64)EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
}
+
Status = mIoMmu->AllocateBuffer (
mIoMmu,
Type,
@@ -1551,13 +1646,15 @@ RootBridgeIoAllocateBuffer ( AllocateType = AllocateAnyPages;
if (!RootBridge->DmaAbove4G ||
- (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
+ ((Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0))
+ {
//
// Limit allocations to memory below 4GB
//
AllocateType = AllocateMaxAddress;
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (SIZE_4GB - 1);
+ PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(SIZE_4GB - 1);
}
+
Status = gBS->AllocatePages (
AllocateType,
MemoryType,
@@ -1565,7 +1662,7 @@ RootBridgeIoAllocateBuffer ( &PhysicalAddress
);
if (!EFI_ERROR (Status)) {
- *HostAddress = (VOID *) (UINTN) PhysicalAddress;
+ *HostAddress = (VOID *)(UINTN)PhysicalAddress;
}
return Status;
@@ -1593,7 +1690,7 @@ RootBridgeIoFreeBuffer ( OUT VOID *HostAddress
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (mIoMmu != NULL) {
Status = mIoMmu->FreeBuffer (
@@ -1604,7 +1701,7 @@ RootBridgeIoFreeBuffer ( return Status;
}
- return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
+ return gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, Pages);
}
/**
@@ -1631,7 +1728,7 @@ RootBridgeIoFreeBuffer ( EFI_STATUS
EFIAPI
RootBridgeIoFlush (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
)
{
return EFI_SUCCESS;
@@ -1667,9 +1764,9 @@ RootBridgeIoGetAttributes ( OUT UINT64 *Attributes
)
{
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- if (Attributes == NULL && Supported == NULL) {
+ if ((Attributes == NULL) && (Supported == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -1678,7 +1775,7 @@ RootBridgeIoGetAttributes ( // Set the return value for Supported and Attributes
//
if (Supported != NULL) {
- *Supported = RootBridge->Supports;
+ *Supported = RootBridge->Supports;
}
if (Attributes != NULL) {
@@ -1733,7 +1830,7 @@ RootBridgeIoSetAttributes ( IN OUT UINT64 *ResourceLength
)
{
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
RootBridge = ROOT_BRIDGE_FROM_THIS (This);
@@ -1773,15 +1870,15 @@ RootBridgeIoSetAttributes ( EFI_STATUS
EFIAPI
RootBridgeIoConfiguration (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT VOID **Resources
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
)
{
- PCI_RESOURCE_TYPE Index;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
- PCI_RES_NODE *ResAllocNode;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
+ PCI_RESOURCE_TYPE Index;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
+ PCI_RES_NODE *ResAllocNode;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;
//
// Get this instance of the Root Bridge.
@@ -1793,7 +1890,6 @@ RootBridgeIoConfiguration ( );
Descriptor = RootBridge->ConfigBuffer;
for (Index = TypeIo; Index < TypeMax; Index++) {
-
ResAllocNode = &RootBridge->ResAllocNode[Index];
if (ResAllocNode->Status != ResAllocated) {
@@ -1805,48 +1901,48 @@ RootBridgeIoConfiguration ( // According to UEFI 2.7, RootBridgeIo->Configuration should return address
// range in CPU view (host address), and ResAllocNode->Base is already a CPU
// view address (host address).
- Descriptor->AddrRangeMin = ResAllocNode->Base;
- Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;
- Descriptor->AddrLen = ResAllocNode->Length;
+ Descriptor->AddrRangeMin = ResAllocNode->Base;
+ Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;
+ Descriptor->AddrLen = ResAllocNode->Length;
Descriptor->AddrTranslationOffset = GetTranslationByResourceType (
- RootBridge,
- ResAllocNode->Type
- );
+ RootBridge,
+ ResAllocNode->Type
+ );
switch (ResAllocNode->Type) {
-
- case TypeIo:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
- break;
-
- case TypePMem32:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem32:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 32;
- break;
-
- case TypePMem64:
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
- case TypeMem64:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
- Descriptor->AddrSpaceGranularity = 64;
- break;
-
- case TypeBus:
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
- break;
-
- default:
- break;
+ case TypeIo:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ break;
+
+ case TypePMem32:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem32:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 32;
+ break;
+
+ case TypePMem64:
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
+ case TypeMem64:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ Descriptor->AddrSpaceGranularity = 64;
+ break;
+
+ case TypeBus:
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
+ break;
+
+ default:
+ break;
}
Descriptor++;
}
+
//
// Terminate the entries.
//
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
End->Desc = ACPI_END_TAG_DESCRIPTOR;
End->Checksum = 0x0;
diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/ComponentName.c index 68b0de8edb..eca2adb246 100644 --- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/ComponentName.c @@ -20,14 +20,13 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponen //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SerialComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SerialComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)SerialComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)SerialComponentNameGetControllerName,
"en"
};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSerialDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSerialDriverNameTable[] = {
{
"eng;en",
L"PCI SIO Serial Driver"
@@ -165,11 +164,11 @@ SerialComponentNameGetDriverName ( EFI_STATUS
EFIAPI
SerialComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
@@ -182,18 +181,18 @@ SerialComponentNameGetControllerName ( // Make sure this driver is currently managing ControllerHandle
//
IoProtocolGuid = &gEfiSioProtocolGuid;
- Status = EfiTestManagedDevice (
- ControllerHandle,
- gSerialControllerDriver.DriverBindingHandle,
- IoProtocolGuid
- );
+ Status = EfiTestManagedDevice (
+ ControllerHandle,
+ gSerialControllerDriver.DriverBindingHandle,
+ IoProtocolGuid
+ );
if (EFI_ERROR (Status)) {
IoProtocolGuid = &gEfiPciIoProtocolGuid;
- Status = EfiTestManagedDevice (
- ControllerHandle,
- gSerialControllerDriver.DriverBindingHandle,
- IoProtocolGuid
- );
+ Status = EfiTestManagedDevice (
+ ControllerHandle,
+ gSerialControllerDriver.DriverBindingHandle,
+ IoProtocolGuid
+ );
}
if (EFI_ERROR (Status)) {
@@ -217,7 +216,7 @@ SerialComponentNameGetControllerName ( Status = gBS->OpenProtocol (
ChildHandle,
&gEfiSerialIoProtocolGuid,
- (VOID **) &SerialIo,
+ (VOID **)&SerialIo,
gSerialControllerDriver.DriverBindingHandle,
ChildHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -229,7 +228,7 @@ SerialComponentNameGetControllerName ( //
// Get the Serial Controller's Device structure
//
- SerialDevice = SERIAL_DEV_FROM_THIS (SerialIo);
+ SerialDevice = SERIAL_DEV_FROM_THIS (SerialIo);
ControllerNameTable = SerialDevice->ControllerNameTable;
}
@@ -250,11 +249,12 @@ SerialComponentNameGetControllerName ( **/
VOID
AddName (
- IN SERIAL_DEV *SerialDevice,
- IN UINT32 Instance
+ IN SERIAL_DEV *SerialDevice,
+ IN UINT32 Instance
)
{
- CHAR16 SerialPortName[SERIAL_PORT_NAME_LEN];
+ CHAR16 SerialPortName[SERIAL_PORT_NAME_LEN];
+
UnicodeSPrint (
SerialPortName,
sizeof (SerialPortName),
@@ -275,5 +275,4 @@ AddName ( SerialPortName,
FALSE
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c index 7ce2e06afe..2b5ff0a37a 100644 --- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c +++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // ISA Serial Driver Global Variables
//
-EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver = {
+EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver = {
SerialControllerDriverSupported,
SerialControllerDriverStart,
SerialControllerDriverStop,
@@ -21,13 +21,13 @@ EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver = { NULL
};
-CONTROLLER_DEVICE_PATH mControllerDevicePathTemplate = {
+CONTROLLER_DEVICE_PATH mControllerDevicePathTemplate = {
{
HARDWARE_DEVICE_PATH,
HW_CONTROLLER_DP,
{
- (UINT8) (sizeof (CONTROLLER_DEVICE_PATH)),
- (UINT8) ((sizeof (CONTROLLER_DEVICE_PATH)) >> 8)
+ (UINT8)(sizeof (CONTROLLER_DEVICE_PATH)),
+ (UINT8)((sizeof (CONTROLLER_DEVICE_PATH)) >> 8)
}
},
0
@@ -62,26 +62,26 @@ SERIAL_DEV gSerialDevTemplate = { MESSAGING_DEVICE_PATH,
MSG_UART_DP,
{
- (UINT8) (sizeof (UART_DEVICE_PATH)),
- (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8)
+ (UINT8)(sizeof (UART_DEVICE_PATH)),
+ (UINT8)((sizeof (UART_DEVICE_PATH)) >> 8)
}
},
- 0, 0, 0, 0, 0
- }, // UartDevicePath
- 0, // BaseAddress
- FALSE, // MmioAccess
- 1, // RegisterStride
- 0, // ClockRate
- 16, // ReceiveFifoDepth
- { 0, 0 }, // Receive;
- 16, // TransmitFifoDepth
- { 0, 0 }, // Transmit;
- FALSE, // SoftwareLoopbackEnable;
- FALSE, // HardwareFlowControl;
- NULL, // *ControllerNameTable;
- FALSE, // ContainsControllerNode;
- 0, // Instance;
- NULL // *PciDeviceInfo;
+ 0, 0,0, 0, 0
+ }, // UartDevicePath
+ 0, // BaseAddress
+ FALSE, // MmioAccess
+ 1, // RegisterStride
+ 0, // ClockRate
+ 16, // ReceiveFifoDepth
+ { 0, 0 }, // Receive;
+ 16, // TransmitFifoDepth
+ { 0, 0 }, // Transmit;
+ FALSE, // SoftwareLoopbackEnable;
+ FALSE, // HardwareFlowControl;
+ NULL, // *ControllerNameTable;
+ FALSE, // ContainsControllerNode;
+ 0, // Instance;
+ NULL // *PciDeviceInfo;
};
/**
@@ -95,14 +95,14 @@ SERIAL_DEV gSerialDevTemplate = { **/
BOOLEAN
IsUartFlowControlDevicePathNode (
- IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
+ IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
)
{
- return (BOOLEAN) (
- (DevicePathType (FlowControl) == MESSAGING_DEVICE_PATH) &&
- (DevicePathSubType (FlowControl) == MSG_VENDOR_DP) &&
- (CompareGuid (&FlowControl->Guid, &gEfiUartDevicePathGuid))
- );
+ return (BOOLEAN)(
+ (DevicePathType (FlowControl) == MESSAGING_DEVICE_PATH) &&
+ (DevicePathSubType (FlowControl) == MSG_VENDOR_DP) &&
+ (CompareGuid (&FlowControl->Guid, &gEfiUartDevicePathGuid))
+ );
}
/**
@@ -118,11 +118,11 @@ IsUartFlowControlDevicePathNode ( EFI_STATUS
EFIAPI
InitializePciSioSerial (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Install driver model protocol(s).
@@ -140,15 +140,15 @@ InitializePciSioSerial ( //
// Initialize UART default setting in gSerialDevTempate
//
- gSerialDevTemplate.SerialMode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
- gSerialDevTemplate.SerialMode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
- gSerialDevTemplate.SerialMode.Parity = PcdGet8 (PcdUartDefaultParity);
- gSerialDevTemplate.SerialMode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
+ gSerialDevTemplate.SerialMode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
+ gSerialDevTemplate.SerialMode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
+ gSerialDevTemplate.SerialMode.Parity = PcdGet8 (PcdUartDefaultParity);
+ gSerialDevTemplate.SerialMode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
gSerialDevTemplate.UartDevicePath.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
gSerialDevTemplate.UartDevicePath.DataBits = PcdGet8 (PcdUartDefaultDataBits);
gSerialDevTemplate.UartDevicePath.Parity = PcdGet8 (PcdUartDefaultParity);
gSerialDevTemplate.UartDevicePath.StopBits = PcdGet8 (PcdUartDefaultStopBits);
- gSerialDevTemplate.ClockRate = PcdGet32 (PcdSerialClockRate);
+ gSerialDevTemplate.ClockRate = PcdGet32 (PcdSerialClockRate);
return Status;
}
@@ -163,13 +163,13 @@ InitializePciSioSerial ( **/
EFI_STATUS
IsSioSerialController (
- EFI_HANDLE Controller
+ EFI_HANDLE Controller
)
{
- EFI_STATUS Status;
- EFI_SIO_PROTOCOL *Sio;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- ACPI_HID_DEVICE_PATH *Acpi;
+ EFI_STATUS Status;
+ EFI_SIO_PROTOCOL *Sio;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ ACPI_HID_DEVICE_PATH *Acpi;
//
// Open the IO Abstraction(s) needed to perform the supported test
@@ -177,7 +177,7 @@ IsSioSerialController ( Status = gBS->OpenProtocol (
Controller,
&gEfiSioProtocolGuid,
- (VOID **) &Sio,
+ (VOID **)&Sio,
gSerialControllerDriver.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -198,25 +198,26 @@ IsSioSerialController ( );
Status = gBS->OpenProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- (VOID **) &DevicePath,
- gSerialControllerDriver.DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_BY_DRIVER
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&DevicePath,
+ gSerialControllerDriver.DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
ASSERT (Status != EFI_ALREADY_STARTED);
if (!EFI_ERROR (Status)) {
do {
- Acpi = (ACPI_HID_DEVICE_PATH *) DevicePath;
+ Acpi = (ACPI_HID_DEVICE_PATH *)DevicePath;
DevicePath = NextDevicePathNode (DevicePath);
} while (!IsDevicePathEnd (DevicePath));
- if (DevicePathType (Acpi) != ACPI_DEVICE_PATH ||
- (DevicePathSubType (Acpi) != ACPI_DP && DevicePathSubType (Acpi) != ACPI_EXTENDED_DP) ||
- Acpi->HID != EISA_PNP_ID (0x501)
- ) {
+ if ((DevicePathType (Acpi) != ACPI_DEVICE_PATH) ||
+ ((DevicePathSubType (Acpi) != ACPI_DP) && (DevicePathSubType (Acpi) != ACPI_EXTENDED_DP)) ||
+ (Acpi->HID != EISA_PNP_ID (0x501))
+ )
+ {
Status = EFI_UNSUPPORTED;
}
}
@@ -225,12 +226,13 @@ IsSioSerialController ( // Close protocol, don't use device path protocol in the Support() function
//
gBS->CloseProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- gSerialControllerDriver.DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ gSerialControllerDriver.DriverBindingHandle,
+ Controller
+ );
}
+
return Status;
}
@@ -244,26 +246,26 @@ IsSioSerialController ( **/
EFI_STATUS
IsPciSerialController (
- EFI_HANDLE Controller
+ EFI_HANDLE Controller
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- PCI_TYPE00 Pci;
- PCI_SERIAL_PARAMETER *PciSerialParameter;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ PCI_TYPE00 Pci;
+ PCI_SERIAL_PARAMETER *PciSerialParameter;
//
// Open the IO Abstraction(s) needed to perform the supported test
//
Status = gBS->OpenProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
- gSerialControllerDriver.DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_BY_DRIVER
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ (VOID **)&PciIo,
+ gSerialControllerDriver.DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
if (Status == EFI_ALREADY_STARTED) {
return EFI_SUCCESS;
}
@@ -272,16 +274,19 @@ IsPciSerialController ( Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0, sizeof (Pci), &Pci);
if (!EFI_ERROR (Status)) {
if (!IS_PCI_16550_SERIAL (&Pci)) {
- for (PciSerialParameter = (PCI_SERIAL_PARAMETER *) PcdGetPtr (PcdPciSerialParameters)
+ for (PciSerialParameter = (PCI_SERIAL_PARAMETER *)PcdGetPtr (PcdPciSerialParameters)
; PciSerialParameter->VendorId != 0xFFFF
; PciSerialParameter++
- ) {
+ )
+ {
if ((Pci.Hdr.VendorId == PciSerialParameter->VendorId) &&
(Pci.Hdr.DeviceId == PciSerialParameter->DeviceId)
- ) {
+ )
+ {
break;
}
}
+
if (PciSerialParameter->VendorId == 0xFFFF) {
Status = EFI_UNSUPPORTED;
} else {
@@ -294,12 +299,13 @@ IsPciSerialController ( // Close the I/O Abstraction(s) used to perform the supported test
//
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- gSerialControllerDriver.DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ gSerialControllerDriver.DriverBindingHandle,
+ Controller
+ );
}
+
if (EFI_ERROR (Status)) {
return Status;
}
@@ -308,24 +314,24 @@ IsPciSerialController ( // Open the EFI Device Path protocol needed to perform the supported test
//
Status = gBS->OpenProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- (VOID **) &DevicePath,
- gSerialControllerDriver.DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_BY_DRIVER
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&DevicePath,
+ gSerialControllerDriver.DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
ASSERT (Status != EFI_ALREADY_STARTED);
//
// Close protocol, don't use device path protocol in the Support() function
//
gBS->CloseProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- gSerialControllerDriver.DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ gSerialControllerDriver.DriverBindingHandle,
+ Controller
+ );
return Status;
}
@@ -343,15 +349,15 @@ IsPciSerialController ( EFI_STATUS
EFIAPI
SerialControllerDriverSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- UART_DEVICE_PATH *Uart;
- UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
+ EFI_STATUS Status;
+ UART_DEVICE_PATH *Uart;
+ UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
//
// Test RemainingDevicePath
@@ -360,10 +366,11 @@ SerialControllerDriverSupported ( Status = EFI_UNSUPPORTED;
Uart = SkipControllerDevicePathNode (RemainingDevicePath, NULL, NULL);
- if (DevicePathType (Uart) != MESSAGING_DEVICE_PATH ||
- DevicePathSubType (Uart) != MSG_UART_DP ||
- DevicePathNodeLength (Uart) != sizeof (UART_DEVICE_PATH)
- ) {
+ if ((DevicePathType (Uart) != MESSAGING_DEVICE_PATH) ||
+ (DevicePathSubType (Uart) != MSG_UART_DP) ||
+ (DevicePathNodeLength (Uart) != sizeof (UART_DEVICE_PATH))
+ )
+ {
return EFI_UNSUPPORTED;
}
@@ -374,7 +381,7 @@ SerialControllerDriverSupported ( return EFI_UNSUPPORTED;
}
- FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *) NextDevicePathNode (Uart);
+ FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *)NextDevicePathNode (Uart);
if (IsUartFlowControlDevicePathNode (FlowControl)) {
//
// If the second node is Flow Control Node,
@@ -390,6 +397,7 @@ SerialControllerDriverSupported ( if (EFI_ERROR (Status)) {
Status = IsPciSerialController (Controller);
}
+
return Status;
}
@@ -415,31 +423,31 @@ SerialControllerDriverSupported ( **/
EFI_STATUS
CreateSerialDevice (
- IN EFI_HANDLE Controller,
- IN UART_DEVICE_PATH *Uart,
- IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
- IN BOOLEAN CreateControllerNode,
- IN UINT32 Instance,
- IN PARENT_IO_PROTOCOL_PTR ParentIo,
- IN PCI_SERIAL_PARAMETER *PciSerialParameter OPTIONAL,
- IN PCI_DEVICE_INFO *PciDeviceInfo OPTIONAL
+ IN EFI_HANDLE Controller,
+ IN UART_DEVICE_PATH *Uart,
+ IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
+ IN BOOLEAN CreateControllerNode,
+ IN UINT32 Instance,
+ IN PARENT_IO_PROTOCOL_PTR ParentIo,
+ IN PCI_SERIAL_PARAMETER *PciSerialParameter OPTIONAL,
+ IN PCI_DEVICE_INFO *PciDeviceInfo OPTIONAL
)
{
- EFI_STATUS Status;
- SERIAL_DEV *SerialDevice;
- UINT8 BarIndex;
- UINT64 Offset;
- UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
- UINT32 FlowControlMap;
- ACPI_RESOURCE_HEADER_PTR Resources;
- EFI_ACPI_IO_PORT_DESCRIPTOR *Io;
- EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR *FixedIo;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AddressSpace;
- EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
-
- BarIndex = 0;
- Offset = 0;
- FlowControl = NULL;
+ EFI_STATUS Status;
+ SERIAL_DEV *SerialDevice;
+ UINT8 BarIndex;
+ UINT64 Offset;
+ UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
+ UINT32 FlowControlMap;
+ ACPI_RESOURCE_HEADER_PTR Resources;
+ EFI_ACPI_IO_PORT_DESCRIPTOR *Io;
+ EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR *FixedIo;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AddressSpace;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+
+ BarIndex = 0;
+ Offset = 0;
+ FlowControl = NULL;
FlowControlMap = 0;
//
@@ -455,7 +463,7 @@ CreateSerialDevice ( if (Uart != NULL) {
CopyMem (&SerialDevice->UartDevicePath, Uart, sizeof (UART_DEVICE_PATH));
- FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *) NextDevicePathNode (Uart);
+ FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *)NextDevicePathNode (Uart);
if (IsUartFlowControlDevicePathNode (FlowControl)) {
FlowControlMap = ReadUnaligned32 (&FlowControl->FlowControlMap);
} else {
@@ -468,16 +476,19 @@ CreateSerialDevice ( //
if (PciSerialParameter != NULL) {
BarIndex = (PciSerialParameter->BarIndex == MAX_UINT8) ? 0 : PciSerialParameter->BarIndex;
- Offset = PciSerialParameter->Offset;
+ Offset = PciSerialParameter->Offset;
if (PciSerialParameter->RegisterStride != 0) {
SerialDevice->RegisterStride = PciSerialParameter->RegisterStride;
}
+
if (PciSerialParameter->ClockRate != 0) {
SerialDevice->ClockRate = PciSerialParameter->ClockRate;
}
+
if (PciSerialParameter->ReceiveFifoDepth != 0) {
SerialDevice->ReceiveFifoDepth = PciSerialParameter->ReceiveFifoDepth;
}
+
if (PciSerialParameter->TransmitFifoDepth != 0) {
SerialDevice->TransmitFifoDepth = PciSerialParameter->TransmitFifoDepth;
}
@@ -487,9 +498,16 @@ CreateSerialDevice ( // Pass NULL ActualBaudRate to VerifyUartParameters to disallow baudrate degrade.
// DriverBindingStart() shouldn't create a handle with different UART device path.
//
- if (!VerifyUartParameters (SerialDevice->ClockRate, SerialDevice->UartDevicePath.BaudRate, SerialDevice->UartDevicePath.DataBits,
- SerialDevice->UartDevicePath.Parity, SerialDevice->UartDevicePath.StopBits, NULL, NULL
- )) {
+ if (!VerifyUartParameters (
+ SerialDevice->ClockRate,
+ SerialDevice->UartDevicePath.BaudRate,
+ SerialDevice->UartDevicePath.DataBits,
+ SerialDevice->UartDevicePath.Parity,
+ SerialDevice->UartDevicePath.StopBits,
+ NULL,
+ NULL
+ ))
+ {
Status = EFI_INVALID_PARAMETER;
goto CreateError;
}
@@ -497,7 +515,7 @@ CreateSerialDevice ( if (PciSerialParameter == NULL) {
Status = ParentIo.Sio->GetResources (ParentIo.Sio, &Resources);
} else {
- Status = ParentIo.PciIo->GetBarAttributes (ParentIo.PciIo, BarIndex, NULL, (VOID **) &Resources);
+ Status = ParentIo.PciIo->GetBarAttributes (ParentIo.PciIo, BarIndex, NULL, (VOID **)&Resources);
}
if (!EFI_ERROR (Status)) {
@@ -508,39 +526,43 @@ CreateSerialDevice ( //
while ((Resources.SmallHeader->Byte != ACPI_END_TAG_DESCRIPTOR) && (SerialDevice->BaseAddress == 0)) {
switch (Resources.SmallHeader->Byte) {
- case ACPI_IO_PORT_DESCRIPTOR:
- Io = (EFI_ACPI_IO_PORT_DESCRIPTOR *) Resources.SmallHeader;
- if (Io->Length != 0) {
- SerialDevice->BaseAddress = Io->BaseAddressMin;
- }
- break;
+ case ACPI_IO_PORT_DESCRIPTOR:
+ Io = (EFI_ACPI_IO_PORT_DESCRIPTOR *)Resources.SmallHeader;
+ if (Io->Length != 0) {
+ SerialDevice->BaseAddress = Io->BaseAddressMin;
+ }
- case ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR:
- FixedIo = (EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR *) Resources.SmallHeader;
- if (FixedIo->Length != 0) {
- SerialDevice->BaseAddress = FixedIo->BaseAddress;
- }
- break;
+ break;
- case ACPI_ADDRESS_SPACE_DESCRIPTOR:
- AddressSpace = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Resources.SmallHeader;
- if (AddressSpace->AddrLen != 0) {
- if (AddressSpace->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
- SerialDevice->MmioAccess = TRUE;
+ case ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR:
+ FixedIo = (EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR *)Resources.SmallHeader;
+ if (FixedIo->Length != 0) {
+ SerialDevice->BaseAddress = FixedIo->BaseAddress;
}
- SerialDevice->BaseAddress = AddressSpace->AddrRangeMin + Offset;
- }
- break;
+
+ break;
+
+ case ACPI_ADDRESS_SPACE_DESCRIPTOR:
+ AddressSpace = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Resources.SmallHeader;
+ if (AddressSpace->AddrLen != 0) {
+ if (AddressSpace->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ SerialDevice->MmioAccess = TRUE;
+ }
+
+ SerialDevice->BaseAddress = AddressSpace->AddrRangeMin + Offset;
+ }
+
+ break;
}
if (Resources.SmallHeader->Bits.Type == 0) {
- Resources.SmallHeader = (ACPI_SMALL_RESOURCE_HEADER *) ((UINT8 *) Resources.SmallHeader
- + Resources.SmallHeader->Bits.Length
- + sizeof (*Resources.SmallHeader));
+ Resources.SmallHeader = (ACPI_SMALL_RESOURCE_HEADER *)((UINT8 *)Resources.SmallHeader
+ + Resources.SmallHeader->Bits.Length
+ + sizeof (*Resources.SmallHeader));
} else {
- Resources.LargeHeader = (ACPI_LARGE_RESOURCE_HEADER *) ((UINT8 *) Resources.LargeHeader
- + Resources.LargeHeader->Length
- + sizeof (*Resources.LargeHeader));
+ Resources.LargeHeader = (ACPI_LARGE_RESOURCE_HEADER *)((UINT8 *)Resources.LargeHeader
+ + Resources.LargeHeader->Length
+ + sizeof (*Resources.LargeHeader));
}
}
}
@@ -550,7 +572,7 @@ CreateSerialDevice ( goto CreateError;
}
- SerialDevice->HardwareFlowControl = (BOOLEAN) (FlowControlMap == UART_FLOW_CONTROL_HARDWARE);
+ SerialDevice->HardwareFlowControl = (BOOLEAN)(FlowControlMap == UART_FLOW_CONTROL_HARDWARE);
//
// Report status code the serial present
@@ -576,10 +598,10 @@ CreateSerialDevice ( //
if (CreateControllerNode) {
mControllerDevicePathTemplate.ControllerNumber = SerialDevice->Instance;
- SerialDevice->DevicePath = AppendDevicePathNode (
- SerialDevice->ParentDevicePath,
- (EFI_DEVICE_PATH_PROTOCOL *) &mControllerDevicePathTemplate
- );
+ SerialDevice->DevicePath = AppendDevicePathNode (
+ SerialDevice->ParentDevicePath,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mControllerDevicePathTemplate
+ );
SerialDevice->ContainsControllerNode = TRUE;
}
@@ -592,15 +614,16 @@ CreateSerialDevice ( if (TempDevicePath != NULL) {
SerialDevice->DevicePath = AppendDevicePathNode (
TempDevicePath,
- (EFI_DEVICE_PATH_PROTOCOL *) &SerialDevice->UartDevicePath
+ (EFI_DEVICE_PATH_PROTOCOL *)&SerialDevice->UartDevicePath
);
FreePool (TempDevicePath);
} else {
SerialDevice->DevicePath = AppendDevicePathNode (
SerialDevice->ParentDevicePath,
- (EFI_DEVICE_PATH_PROTOCOL *) &SerialDevice->UartDevicePath
+ (EFI_DEVICE_PATH_PROTOCOL *)&SerialDevice->UartDevicePath
);
}
+
//
// 3. Append the Flow Control device path node.
// Only produce the Flow Control node when remaining device path has it
@@ -610,11 +633,12 @@ CreateSerialDevice ( if (TempDevicePath != NULL) {
SerialDevice->DevicePath = AppendDevicePathNode (
TempDevicePath,
- (EFI_DEVICE_PATH_PROTOCOL *) FlowControl
+ (EFI_DEVICE_PATH_PROTOCOL *)FlowControl
);
FreePool (TempDevicePath);
}
}
+
ASSERT (SerialDevice->DevicePath != NULL);
//
@@ -644,20 +668,23 @@ CreateSerialDevice ( //
Status = gBS->InstallMultipleProtocolInterfaces (
&SerialDevice->Handle,
- &gEfiDevicePathProtocolGuid, SerialDevice->DevicePath,
- &gEfiSerialIoProtocolGuid, &SerialDevice->SerialIo,
+ &gEfiDevicePathProtocolGuid,
+ SerialDevice->DevicePath,
+ &gEfiSerialIoProtocolGuid,
+ &SerialDevice->SerialIo,
NULL
);
if (EFI_ERROR (Status)) {
goto CreateError;
}
+
//
// Open For Child Device
//
Status = gBS->OpenProtocol (
Controller,
PciSerialParameter != NULL ? &gEfiPciIoProtocolGuid : &gEfiSioProtocolGuid,
- (VOID **) &ParentIo,
+ (VOID **)&ParentIo,
gSerialControllerDriver.DriverBindingHandle,
SerialDevice->Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
@@ -666,8 +693,10 @@ CreateSerialDevice ( if (EFI_ERROR (Status)) {
gBS->UninstallMultipleProtocolInterfaces (
SerialDevice->Handle,
- &gEfiDevicePathProtocolGuid, SerialDevice->DevicePath,
- &gEfiSerialIoProtocolGuid, &SerialDevice->SerialIo,
+ &gEfiDevicePathProtocolGuid,
+ SerialDevice->DevicePath,
+ &gEfiSerialIoProtocolGuid,
+ &SerialDevice->SerialIo,
NULL
);
}
@@ -677,11 +706,14 @@ CreateError: if (SerialDevice->DevicePath != NULL) {
FreePool (SerialDevice->DevicePath);
}
+
if (SerialDevice->ControllerNameTable != NULL) {
FreeUnicodeStringTable (SerialDevice->ControllerNameTable);
}
+
FreePool (SerialDevice);
}
+
return Status;
}
@@ -697,18 +729,18 @@ CreateError: **/
SERIAL_DEV **
GetChildSerialDevices (
- IN EFI_HANDLE Controller,
- IN EFI_GUID *IoProtocolGuid,
- OUT UINTN *Count
+ IN EFI_HANDLE Controller,
+ IN EFI_GUID *IoProtocolGuid,
+ OUT UINTN *Count
)
{
- EFI_STATUS Status;
- UINTN Index;
- EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfoBuffer;
- UINTN EntryCount;
- SERIAL_DEV **SerialDevices;
- EFI_SERIAL_IO_PROTOCOL *SerialIo;
- BOOLEAN OpenByDriver;
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfoBuffer;
+ UINTN EntryCount;
+ SERIAL_DEV **SerialDevices;
+ EFI_SERIAL_IO_PROTOCOL *SerialIo;
+ BOOLEAN OpenByDriver;
*Count = 0;
//
@@ -716,11 +748,11 @@ GetChildSerialDevices ( // update the attributes/control.
//
Status = gBS->OpenProtocolInformation (
- Controller,
- IoProtocolGuid,
- &OpenInfoBuffer,
- &EntryCount
- );
+ Controller,
+ IoProtocolGuid,
+ &OpenInfoBuffer,
+ &EntryCount
+ );
if (EFI_ERROR (Status)) {
return NULL;
}
@@ -728,29 +760,29 @@ GetChildSerialDevices ( SerialDevices = AllocatePool (EntryCount * sizeof (SERIAL_DEV *));
ASSERT (SerialDevices != NULL);
- *Count = 0;
+ *Count = 0;
OpenByDriver = FALSE;
for (Index = 0; Index < EntryCount; Index++) {
if ((OpenInfoBuffer[Index].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) != 0) {
Status = gBS->OpenProtocol (
- OpenInfoBuffer[Index].ControllerHandle,
- &gEfiSerialIoProtocolGuid,
- (VOID **) &SerialIo,
- gSerialControllerDriver.DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL
- );
+ OpenInfoBuffer[Index].ControllerHandle,
+ &gEfiSerialIoProtocolGuid,
+ (VOID **)&SerialIo,
+ gSerialControllerDriver.DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
if (!EFI_ERROR (Status)) {
SerialDevices[(*Count)++] = SERIAL_DEV_FROM_THIS (SerialIo);
}
}
-
if ((OpenInfoBuffer[Index].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) != 0) {
ASSERT (OpenInfoBuffer[Index].AgentHandle == gSerialControllerDriver.DriverBindingHandle);
OpenByDriver = TRUE;
}
}
+
if (OpenInfoBuffer != NULL) {
FreePool (OpenInfoBuffer);
}
@@ -772,32 +804,32 @@ GetChildSerialDevices ( EFI_STATUS
EFIAPI
SerialControllerDriverStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- UINTN Index;
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- EFI_DEVICE_PATH_PROTOCOL *Node;
- EFI_SERIAL_IO_PROTOCOL *SerialIo;
- UINT32 ControllerNumber;
- UART_DEVICE_PATH *Uart;
- UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
- UINT32 Control;
- PARENT_IO_PROTOCOL_PTR ParentIo;
- ACPI_HID_DEVICE_PATH *Acpi;
- EFI_GUID *IoProtocolGuid;
- PCI_SERIAL_PARAMETER *PciSerialParameter;
- PCI_SERIAL_PARAMETER DefaultPciSerialParameter;
- PCI_TYPE00 Pci;
- UINT32 PciSerialCount;
- SERIAL_DEV **SerialDevices;
- UINTN SerialDeviceCount;
- PCI_DEVICE_INFO *PciDeviceInfo;
- UINT64 Supports;
- BOOLEAN ContainsControllerNode;
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *Node;
+ EFI_SERIAL_IO_PROTOCOL *SerialIo;
+ UINT32 ControllerNumber;
+ UART_DEVICE_PATH *Uart;
+ UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
+ UINT32 Control;
+ PARENT_IO_PROTOCOL_PTR ParentIo;
+ ACPI_HID_DEVICE_PATH *Acpi;
+ EFI_GUID *IoProtocolGuid;
+ PCI_SERIAL_PARAMETER *PciSerialParameter;
+ PCI_SERIAL_PARAMETER DefaultPciSerialParameter;
+ PCI_TYPE00 Pci;
+ UINT32 PciSerialCount;
+ SERIAL_DEV **SerialDevices;
+ UINTN SerialDeviceCount;
+ PCI_DEVICE_INFO *PciDeviceInfo;
+ UINT64 Supports;
+ BOOLEAN ContainsControllerNode;
//
// Get the Parent Device Path
@@ -805,14 +837,15 @@ SerialControllerDriverStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID **) &ParentDevicePath,
+ (VOID **)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
+ if (EFI_ERROR (Status) && (Status != EFI_ALREADY_STARTED)) {
return Status;
}
+
//
// Report status code enable the serial
//
@@ -826,25 +859,26 @@ SerialControllerDriverStart ( // Grab the IO abstraction we need to get any work done
//
IoProtocolGuid = &gEfiSioProtocolGuid;
- Status = gBS->OpenProtocol (
- Controller,
- IoProtocolGuid,
- (VOID **) &ParentIo,
- This->DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_BY_DRIVER
- );
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
+ Status = gBS->OpenProtocol (
+ Controller,
+ IoProtocolGuid,
+ (VOID **)&ParentIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+ if (EFI_ERROR (Status) && (Status != EFI_ALREADY_STARTED)) {
IoProtocolGuid = &gEfiPciIoProtocolGuid;
- Status = gBS->OpenProtocol (
- Controller,
- IoProtocolGuid,
- (VOID **) &ParentIo,
- This->DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_BY_DRIVER
- );
+ Status = gBS->OpenProtocol (
+ Controller,
+ IoProtocolGuid,
+ (VOID **)&ParentIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
}
+
ASSERT (!EFI_ERROR (Status) || Status == EFI_ALREADY_STARTED);
//
@@ -854,9 +888,9 @@ SerialControllerDriverStart ( return EFI_SUCCESS;
}
- ControllerNumber = 0;
+ ControllerNumber = 0;
ContainsControllerNode = FALSE;
- SerialDevices = GetChildSerialDevices (Controller, IoProtocolGuid, &SerialDeviceCount);
+ SerialDevices = GetChildSerialDevices (Controller, IoProtocolGuid, &SerialDeviceCount);
if (SerialDeviceCount != 0) {
if (RemainingDevicePath == NULL) {
@@ -869,31 +903,41 @@ SerialControllerDriverStart ( //
// Update the attributes/control of the SerialIo instance specified by RemainingDevicePath.
//
- Uart = (UART_DEVICE_PATH *) SkipControllerDevicePathNode (RemainingDevicePath, &ContainsControllerNode, &ControllerNumber);
+ Uart = (UART_DEVICE_PATH *)SkipControllerDevicePathNode (RemainingDevicePath, &ContainsControllerNode, &ControllerNumber);
for (Index = 0; Index < SerialDeviceCount; Index++) {
ASSERT ((SerialDevices != NULL) && (SerialDevices[Index] != NULL));
if ((!SerialDevices[Index]->ContainsControllerNode && !ContainsControllerNode) ||
- (SerialDevices[Index]->ContainsControllerNode && ContainsControllerNode && SerialDevices[Index]->Instance == ControllerNumber)
- ) {
+ (SerialDevices[Index]->ContainsControllerNode && ContainsControllerNode && (SerialDevices[Index]->Instance == ControllerNumber))
+ )
+ {
SerialIo = &SerialDevices[Index]->SerialIo;
- Status = EFI_INVALID_PARAMETER;
+ Status = EFI_INVALID_PARAMETER;
//
// Pass NULL ActualBaudRate to VerifyUartParameters to disallow baudrate degrade.
// DriverBindingStart() shouldn't create a handle with different UART device path.
//
- if (VerifyUartParameters (SerialDevices[Index]->ClockRate, Uart->BaudRate, Uart->DataBits,
- (EFI_PARITY_TYPE) Uart->Parity, (EFI_STOP_BITS_TYPE) Uart->StopBits, NULL, NULL)) {
+ if (VerifyUartParameters (
+ SerialDevices[Index]->ClockRate,
+ Uart->BaudRate,
+ Uart->DataBits,
+ (EFI_PARITY_TYPE)Uart->Parity,
+ (EFI_STOP_BITS_TYPE)Uart->StopBits,
+ NULL,
+ NULL
+ ))
+ {
Status = SerialIo->SetAttributes (
SerialIo,
Uart->BaudRate,
SerialIo->Mode->ReceiveFifoDepth,
SerialIo->Mode->Timeout,
- (EFI_PARITY_TYPE) Uart->Parity,
+ (EFI_PARITY_TYPE)Uart->Parity,
Uart->DataBits,
- (EFI_STOP_BITS_TYPE) Uart->StopBits
+ (EFI_STOP_BITS_TYPE)Uart->StopBits
);
}
- FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *) NextDevicePathNode (Uart);
+
+ FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *)NextDevicePathNode (Uart);
if (!EFI_ERROR (Status) && IsUartFlowControlDevicePathNode (FlowControl)) {
Status = SerialIo->GetControl (SerialIo, &Control);
if (!EFI_ERROR (Status)) {
@@ -902,6 +946,7 @@ SerialControllerDriverStart ( } else {
Control &= ~EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
}
+
//
// Clear the bits that are not allowed to pass to SetControl
//
@@ -911,9 +956,11 @@ SerialControllerDriverStart ( Status = SerialIo->SetControl (SerialIo, Control);
}
}
+
break;
}
}
+
if (Index != SerialDeviceCount) {
//
// Directly return if the SerialIo instance specified by RemainingDevicePath is found and updated.
@@ -922,13 +969,14 @@ SerialControllerDriverStart ( if (SerialDevices != NULL) {
FreePool (SerialDevices);
}
+
return Status;
}
}
}
if (RemainingDevicePath != NULL) {
- Uart = (UART_DEVICE_PATH *) SkipControllerDevicePathNode (RemainingDevicePath, &ContainsControllerNode, &ControllerNumber);
+ Uart = (UART_DEVICE_PATH *)SkipControllerDevicePathNode (RemainingDevicePath, &ContainsControllerNode, &ControllerNumber);
} else {
Uart = NULL;
}
@@ -936,12 +984,13 @@ SerialControllerDriverStart ( PciDeviceInfo = NULL;
if (IoProtocolGuid == &gEfiSioProtocolGuid) {
Status = EFI_NOT_FOUND;
- if (RemainingDevicePath == NULL || !ContainsControllerNode) {
+ if ((RemainingDevicePath == NULL) || !ContainsControllerNode) {
Node = ParentDevicePath;
do {
- Acpi = (ACPI_HID_DEVICE_PATH *) Node;
+ Acpi = (ACPI_HID_DEVICE_PATH *)Node;
Node = NextDevicePathNode (Node);
} while (!IsDevicePathEnd (Node));
+
Status = CreateSerialDevice (Controller, Uart, ParentDevicePath, FALSE, Acpi->UID, ParentIo, NULL, NULL);
DEBUG ((DEBUG_INFO, "PciSioSerial: Create SIO child serial device - %r\n", Status));
}
@@ -955,7 +1004,8 @@ SerialControllerDriverStart ( for (PciSerialParameter = PcdGetPtr (PcdPciSerialParameters); PciSerialParameter->VendorId != 0xFFFF; PciSerialParameter++) {
if ((PciSerialParameter->VendorId == Pci.Hdr.VendorId) &&
(PciSerialParameter->DeviceId == Pci.Hdr.DeviceId)
- ) {
+ )
+ {
PciSerialCount++;
}
}
@@ -968,29 +1018,29 @@ SerialControllerDriverStart ( PciDeviceInfo = AllocatePool (sizeof (PCI_DEVICE_INFO));
ASSERT (PciDeviceInfo != NULL);
PciDeviceInfo->ChildCount = 0;
- PciDeviceInfo->PciIo = ParentIo.PciIo;
- Status = ParentIo.PciIo->Attributes (
- ParentIo.PciIo,
- EfiPciIoAttributeOperationGet,
- 0,
- &PciDeviceInfo->PciAttributes
- );
+ PciDeviceInfo->PciIo = ParentIo.PciIo;
+ Status = ParentIo.PciIo->Attributes (
+ ParentIo.PciIo,
+ EfiPciIoAttributeOperationGet,
+ 0,
+ &PciDeviceInfo->PciAttributes
+ );
if (!EFI_ERROR (Status)) {
Status = ParentIo.PciIo->Attributes (
- ParentIo.PciIo,
- EfiPciIoAttributeOperationSupported,
- 0,
- &Supports
- );
+ ParentIo.PciIo,
+ EfiPciIoAttributeOperationSupported,
+ 0,
+ &Supports
+ );
if (!EFI_ERROR (Status)) {
Supports &= (UINT64)(EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
- Status = ParentIo.PciIo->Attributes (
- ParentIo.PciIo,
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+ Status = ParentIo.PciIo->Attributes (
+ ParentIo.PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
}
}
} else {
@@ -1007,18 +1057,18 @@ SerialControllerDriverStart ( //
// PCI serial device contains only one UART
//
- if (RemainingDevicePath == NULL || !ContainsControllerNode) {
+ if ((RemainingDevicePath == NULL) || !ContainsControllerNode) {
//
// This PCI serial device is matched by class code in Supported()
//
if (PciSerialCount == 0) {
- DefaultPciSerialParameter.VendorId = Pci.Hdr.VendorId;
- DefaultPciSerialParameter.DeviceId = Pci.Hdr.DeviceId;
- DefaultPciSerialParameter.BarIndex = 0;
- DefaultPciSerialParameter.Offset = 0;
+ DefaultPciSerialParameter.VendorId = Pci.Hdr.VendorId;
+ DefaultPciSerialParameter.DeviceId = Pci.Hdr.DeviceId;
+ DefaultPciSerialParameter.BarIndex = 0;
+ DefaultPciSerialParameter.Offset = 0;
DefaultPciSerialParameter.RegisterStride = 0;
- DefaultPciSerialParameter.ClockRate = 0;
- PciSerialParameter = &DefaultPciSerialParameter;
+ DefaultPciSerialParameter.ClockRate = 0;
+ PciSerialParameter = &DefaultPciSerialParameter;
} else if (PciSerialCount == 1) {
PciSerialParameter = PcdGetPtr (PcdPciSerialParameters);
}
@@ -1033,13 +1083,14 @@ SerialControllerDriverStart ( //
// PCI serial device contains multiple UARTs
//
- if (RemainingDevicePath == NULL || ContainsControllerNode) {
+ if ((RemainingDevicePath == NULL) || ContainsControllerNode) {
PciSerialCount = 0;
for (PciSerialParameter = PcdGetPtr (PcdPciSerialParameters); PciSerialParameter->VendorId != 0xFFFF; PciSerialParameter++) {
if ((PciSerialParameter->VendorId == Pci.Hdr.VendorId) &&
(PciSerialParameter->DeviceId == Pci.Hdr.DeviceId) &&
((RemainingDevicePath == NULL) || (ControllerNumber == PciSerialCount))
- ) {
+ )
+ {
//
// Create controller node when PCI serial device contains multiple UARTs
//
@@ -1070,14 +1121,15 @@ SerialControllerDriverStart ( if (EFI_ERROR (Status) && (SerialDeviceCount == 0)) {
if (PciDeviceInfo != NULL) {
Status = ParentIo.PciIo->Attributes (
- ParentIo.PciIo,
- EfiPciIoAttributeOperationSet,
- PciDeviceInfo->PciAttributes,
- NULL
- );
+ ParentIo.PciIo,
+ EfiPciIoAttributeOperationSet,
+ PciDeviceInfo->PciAttributes,
+ NULL
+ );
ASSERT_EFI_ERROR (Status);
FreePool (PciDeviceInfo);
}
+
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
@@ -1110,28 +1162,28 @@ SerialControllerDriverStart ( EFI_STATUS
EFIAPI
SerialControllerDriverStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
- EFI_STATUS Status;
- UINTN Index;
- BOOLEAN AllChildrenStopped;
- EFI_SERIAL_IO_PROTOCOL *SerialIo;
- SERIAL_DEV *SerialDevice;
- VOID *IoProtocol;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- PCI_DEVICE_INFO *PciDeviceInfo;
+ EFI_STATUS Status;
+ UINTN Index;
+ BOOLEAN AllChildrenStopped;
+ EFI_SERIAL_IO_PROTOCOL *SerialIo;
+ SERIAL_DEV *SerialDevice;
+ VOID *IoProtocol;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ PCI_DEVICE_INFO *PciDeviceInfo;
PciDeviceInfo = NULL;
Status = gBS->HandleProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID **) &DevicePath
+ (VOID **)&DevicePath
);
//
@@ -1174,17 +1226,15 @@ SerialControllerDriverStop ( AllChildrenStopped = TRUE;
for (Index = 0; Index < NumberOfChildren; Index++) {
-
Status = gBS->OpenProtocol (
ChildHandleBuffer[Index],
&gEfiSerialIoProtocolGuid,
- (VOID **) &SerialIo,
+ (VOID **)&SerialIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
if (!EFI_ERROR (Status)) {
-
SerialDevice = SERIAL_DEV_FROM_THIS (SerialIo);
ASSERT ((PciDeviceInfo == NULL) || (PciDeviceInfo == SerialDevice->PciDeviceInfo));
PciDeviceInfo = SerialDevice->PciDeviceInfo;
@@ -1198,8 +1248,10 @@ SerialControllerDriverStop ( Status = gBS->UninstallMultipleProtocolInterfaces (
ChildHandleBuffer[Index],
- &gEfiDevicePathProtocolGuid, SerialDevice->DevicePath,
- &gEfiSerialIoProtocolGuid, &SerialDevice->SerialIo,
+ &gEfiDevicePathProtocolGuid,
+ SerialDevice->DevicePath,
+ &gEfiSerialIoProtocolGuid,
+ &SerialDevice->SerialIo,
NULL
);
if (EFI_ERROR (Status)) {
@@ -1237,14 +1289,15 @@ SerialControllerDriverStop ( if ((PciDeviceInfo != NULL) && (PciDeviceInfo->ChildCount == 0)) {
ASSERT (PciDeviceInfo->PciIo != NULL);
Status = PciDeviceInfo->PciIo->Attributes (
- PciDeviceInfo->PciIo,
- EfiPciIoAttributeOperationSet,
- PciDeviceInfo->PciAttributes,
- NULL
- );
+ PciDeviceInfo->PciIo,
+ EfiPciIoAttributeOperationSet,
+ PciDeviceInfo->PciAttributes,
+ NULL
+ );
ASSERT_EFI_ERROR (Status);
FreePool (PciDeviceInfo);
}
+
return EFI_SUCCESS;
}
}
diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.h b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.h index fa5aba07e1..5903ab5cd3 100644 --- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.h +++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.h @@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _SERIAL_H_
#define _SERIAL_H_
-
#include <Uefi.h>
#include <IndustryStandard/Pci.h>
@@ -34,13 +33,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Driver Binding Externs
//
-extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;
-extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;
+extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;
-#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"
-#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"
-#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)
+#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"
+#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"
+#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)
//
// Internal Data Structures
@@ -61,73 +60,73 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2; /// RegisterStride equals to 4.
///
typedef struct {
- UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
- UINT16 DeviceId; ///< Device ID to match the PCI device
- UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
- UINT64 Offset; ///< The byte offset into to the BAR
- UINT8 BarIndex; ///< Which BAR to get the UART base address
- UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
- UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
- UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
- UINT8 Reserved[2];
+ UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
+ UINT16 DeviceId; ///< Device ID to match the PCI device
+ UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
+ UINT64 Offset; ///< The byte offset into to the BAR
+ UINT8 BarIndex; ///< Which BAR to get the UART base address
+ UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ UINT8 Reserved[2];
} PCI_SERIAL_PARAMETER;
#pragma pack()
-#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.
+#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.
typedef struct {
- UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).
- UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).
- UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.
+ UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).
+ UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).
+ UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.
} SERIAL_DEV_FIFO;
typedef union {
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_SIO_PROTOCOL *Sio;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_SIO_PROTOCOL *Sio;
} PARENT_IO_PROTOCOL_PTR;
typedef struct {
- EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.
- UINTN ChildCount; // Count of child SerialIo instance.
- UINT64 PciAttributes; // Original PCI attributes.
+ EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.
+ UINTN ChildCount; // Count of child SerialIo instance.
+ UINT64 PciAttributes; // Original PCI attributes.
} PCI_DEVICE_INFO;
typedef struct {
- UINT32 Signature;
- EFI_HANDLE Handle;
- EFI_SERIAL_IO_PROTOCOL SerialIo;
- EFI_SERIAL_IO_MODE SerialMode;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
-
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- UART_DEVICE_PATH UartDevicePath;
-
- EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address
- BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO
- UINT8 RegisterStride; ///< UART Register Stride
- UINT32 ClockRate; ///< UART clock rate
-
- UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.
- SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data
-
- UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.
- SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data
-
- BOOLEAN SoftwareLoopbackEnable;
- BOOLEAN HardwareFlowControl;
- EFI_UNICODE_STRING_TABLE *ControllerNameTable;
- BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node
- UINT32 Instance;
- PCI_DEVICE_INFO *PciDeviceInfo;
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_SERIAL_IO_PROTOCOL SerialIo;
+ EFI_SERIAL_IO_MODE SerialMode;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
+ UART_DEVICE_PATH UartDevicePath;
+
+ EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address
+ BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO
+ UINT8 RegisterStride; ///< UART Register Stride
+ UINT32 ClockRate; ///< UART clock rate
+
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.
+ SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data
+
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.
+ SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data
+
+ BOOLEAN SoftwareLoopbackEnable;
+ BOOLEAN HardwareFlowControl;
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;
+ BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node
+ UINT32 Instance;
+ PCI_DEVICE_INFO *PciDeviceInfo;
} SERIAL_DEV;
-#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')
-#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
+#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')
+#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
//
// Serial Driver Defaults
//
-#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
-#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \
+#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
+#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \
EFI_SERIAL_DATA_SET_READY | \
EFI_SERIAL_RING_INDICATE | \
EFI_SERIAL_CARRIER_DETECT | \
@@ -139,23 +138,23 @@ typedef struct { EFI_SERIAL_OUTPUT_BUFFER_EMPTY | \
EFI_SERIAL_INPUT_BUFFER_EMPTY)
-#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
-#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
+#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
+#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
//
// UART Registers
//
-#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register
-#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register
-#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB
-#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB
-#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register
-#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register
-#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register
-#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register
-#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register
-#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register
-#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register
-#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register
+#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register
+#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register
+#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB
+#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB
+#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register
+#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register
+#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register
+#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register
+#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register
+#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register
+#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register
+#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register
#pragma pack(1)
///
@@ -163,13 +162,13 @@ typedef struct { ///
typedef union {
struct {
- UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable
- UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable
- UINT8 Rie : 1; ///< Receiver Interrupt Enable
- UINT8 Mie : 1; ///< Modem Interrupt Enable
- UINT8 Reserved : 4;
+ UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable
+ UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable
+ UINT8 Rie : 1; ///< Receiver Interrupt Enable
+ UINT8 Mie : 1; ///< Modem Interrupt Enable
+ UINT8 Reserved : 4;
} Bits;
- UINT8 Data;
+ UINT8 Data;
} SERIAL_PORT_IER;
///
@@ -177,15 +176,15 @@ typedef union { ///
typedef union {
struct {
- UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable
- UINT8 ResetRF : 1; ///< Reset Reciever FIFO
- UINT8 ResetTF : 1; ///< Reset Transmistter FIFO
- UINT8 Dms : 1; ///< DMA Mode Select
- UINT8 Reserved : 1;
- UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO
- UINT8 Rtb : 2; ///< Receive Trigger Bits
+ UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable
+ UINT8 ResetRF : 1; ///< Reset Reciever FIFO
+ UINT8 ResetTF : 1; ///< Reset Transmistter FIFO
+ UINT8 Dms : 1; ///< DMA Mode Select
+ UINT8 Reserved : 1;
+ UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO
+ UINT8 Rtb : 2; ///< Receive Trigger Bits
} Bits;
- UINT8 Data;
+ UINT8 Data;
} SERIAL_PORT_FCR;
///
@@ -193,15 +192,15 @@ typedef union { ///
typedef union {
struct {
- UINT8 SerialDB : 2; ///< Number of Serial Data Bits
- UINT8 StopB : 1; ///< Number of Stop Bits
- UINT8 ParEn : 1; ///< Parity Enable
- UINT8 EvenPar : 1; ///< Even Parity Select
- UINT8 SticPar : 1; ///< Sticky Parity
- UINT8 BrCon : 1; ///< Break Control
- UINT8 DLab : 1; ///< Divisor Latch Access Bit
+ UINT8 SerialDB : 2; ///< Number of Serial Data Bits
+ UINT8 StopB : 1; ///< Number of Stop Bits
+ UINT8 ParEn : 1; ///< Parity Enable
+ UINT8 EvenPar : 1; ///< Even Parity Select
+ UINT8 SticPar : 1; ///< Sticky Parity
+ UINT8 BrCon : 1; ///< Break Control
+ UINT8 DLab : 1; ///< Divisor Latch Access Bit
} Bits;
- UINT8 Data;
+ UINT8 Data;
} SERIAL_PORT_LCR;
///
@@ -209,14 +208,14 @@ typedef union { ///
typedef union {
struct {
- UINT8 DtrC : 1; ///< Data Terminal Ready Control
- UINT8 Rts : 1; ///< Request To Send Control
- UINT8 Out1 : 1; ///< Output1
- UINT8 Out2 : 1; ///< Output2, used to disable interrupt
- UINT8 Lme : 1; ///< Loopback Mode Enable
- UINT8 Reserved : 3;
+ UINT8 DtrC : 1; ///< Data Terminal Ready Control
+ UINT8 Rts : 1; ///< Request To Send Control
+ UINT8 Out1 : 1; ///< Output1
+ UINT8 Out2 : 1; ///< Output2, used to disable interrupt
+ UINT8 Lme : 1; ///< Loopback Mode Enable
+ UINT8 Reserved : 3;
} Bits;
- UINT8 Data;
+ UINT8 Data;
} SERIAL_PORT_MCR;
///
@@ -224,16 +223,16 @@ typedef union { ///
typedef union {
struct {
- UINT8 Dr : 1; ///< Receiver Data Ready Status
- UINT8 Oe : 1; ///< Overrun Error Status
- UINT8 Pe : 1; ///< Parity Error Status
- UINT8 Fe : 1; ///< Framing Error Status
- UINT8 Bi : 1; ///< Break Interrupt Status
- UINT8 Thre : 1; ///< Transmistter Holding Register Status
- UINT8 Temt : 1; ///< Transmitter Empty Status
- UINT8 FIFOe : 1; ///< FIFO Error Status
+ UINT8 Dr : 1; ///< Receiver Data Ready Status
+ UINT8 Oe : 1; ///< Overrun Error Status
+ UINT8 Pe : 1; ///< Parity Error Status
+ UINT8 Fe : 1; ///< Framing Error Status
+ UINT8 Bi : 1; ///< Break Interrupt Status
+ UINT8 Thre : 1; ///< Transmistter Holding Register Status
+ UINT8 Temt : 1; ///< Transmitter Empty Status
+ UINT8 FIFOe : 1; ///< FIFO Error Status
} Bits;
- UINT8 Data;
+ UINT8 Data;
} SERIAL_PORT_LSR;
///
@@ -241,48 +240,49 @@ typedef union { ///
typedef union {
struct {
- UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status
- UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status
- UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status
- UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status
- UINT8 Cts : 1; ///< Clear To Send Status
- UINT8 Dsr : 1; ///< Data Set Ready Status
- UINT8 Ri : 1; ///< Ring Indicator Status
- UINT8 Dcd : 1; ///< Data Carrier Detect Status
+ UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status
+ UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status
+ UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status
+ UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status
+ UINT8 Cts : 1; ///< Clear To Send Status
+ UINT8 Dsr : 1; ///< Data Set Ready Status
+ UINT8 Ri : 1; ///< Ring Indicator Status
+ UINT8 Dcd : 1; ///< Data Carrier Detect Status
} Bits;
- UINT8 Data;
+ UINT8 Data;
} SERIAL_PORT_MSR;
#pragma pack()
//
// Define serial register I/O macros
//
-#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)
-#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)
-#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)
-#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)
-#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)
-#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)
-#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)
-#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)
-#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)
-#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)
-
-#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)
-#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)
-#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)
-#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)
-#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)
-#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)
-#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)
-#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)
-#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)
-#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)
+#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)
+#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)
+#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)
+#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)
+#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)
+#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)
+#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)
+#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)
+#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)
+#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)
+
+#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)
+#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)
+#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)
+#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)
+#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)
+#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)
+#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)
+#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)
+#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)
+#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)
//
// Prototypes
// Driver model protocol interface
//
+
/**
Check to see if this driver supports the given controller
@@ -296,9 +296,9 @@ typedef union { EFI_STATUS
EFIAPI
SerialControllerDriverSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -313,9 +313,9 @@ SerialControllerDriverSupported ( EFI_STATUS
EFIAPI
SerialControllerDriverStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -333,15 +333,16 @@ SerialControllerDriverStart ( EFI_STATUS
EFIAPI
SerialControllerDriverStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
//
// Serial I/O Protocol Interface
//
+
/**
Reset serial device.
@@ -354,7 +355,7 @@ SerialControllerDriverStop ( EFI_STATUS
EFIAPI
SerialReset (
- IN EFI_SERIAL_IO_PROTOCOL *This
+ IN EFI_SERIAL_IO_PROTOCOL *This
);
/**
@@ -377,13 +378,13 @@ SerialReset ( EFI_STATUS
EFIAPI
SerialSetAttributes (
- IN EFI_SERIAL_IO_PROTOCOL *This,
- IN UINT64 BaudRate,
- IN UINT32 ReceiveFifoDepth,
- IN UINT32 Timeout,
- IN EFI_PARITY_TYPE Parity,
- IN UINT8 DataBits,
- IN EFI_STOP_BITS_TYPE StopBits
+ IN EFI_SERIAL_IO_PROTOCOL *This,
+ IN UINT64 BaudRate,
+ IN UINT32 ReceiveFifoDepth,
+ IN UINT32 Timeout,
+ IN EFI_PARITY_TYPE Parity,
+ IN UINT8 DataBits,
+ IN EFI_STOP_BITS_TYPE StopBits
);
/**
@@ -399,8 +400,8 @@ SerialSetAttributes ( EFI_STATUS
EFIAPI
SerialSetControl (
- IN EFI_SERIAL_IO_PROTOCOL *This,
- IN UINT32 Control
+ IN EFI_SERIAL_IO_PROTOCOL *This,
+ IN UINT32 Control
);
/**
@@ -415,8 +416,8 @@ SerialSetControl ( EFI_STATUS
EFIAPI
SerialGetControl (
- IN EFI_SERIAL_IO_PROTOCOL *This,
- OUT UINT32 *Control
+ IN EFI_SERIAL_IO_PROTOCOL *This,
+ OUT UINT32 *Control
);
/**
@@ -435,9 +436,9 @@ SerialGetControl ( EFI_STATUS
EFIAPI
SerialWrite (
- IN EFI_SERIAL_IO_PROTOCOL *This,
- IN OUT UINTN *BufferSize,
- IN VOID *Buffer
+ IN EFI_SERIAL_IO_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
);
/**
@@ -456,14 +457,15 @@ SerialWrite ( EFI_STATUS
EFIAPI
SerialRead (
- IN EFI_SERIAL_IO_PROTOCOL *This,
- IN OUT UINTN *BufferSize,
- OUT VOID *Buffer
+ IN EFI_SERIAL_IO_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
);
//
// Internal Functions
//
+
/**
Use scratchpad register to test if this serial port is present.
@@ -473,7 +475,7 @@ SerialRead ( **/
BOOLEAN
SerialPresent (
- IN SERIAL_DEV *SerialDevice
+ IN SERIAL_DEV *SerialDevice
);
/**
@@ -486,7 +488,7 @@ SerialPresent ( **/
BOOLEAN
SerialFifoFull (
- IN SERIAL_DEV_FIFO *Fifo
+ IN SERIAL_DEV_FIFO *Fifo
);
/**
@@ -499,7 +501,7 @@ SerialFifoFull ( **/
BOOLEAN
SerialFifoEmpty (
- IN SERIAL_DEV_FIFO *Fifo
+ IN SERIAL_DEV_FIFO *Fifo
);
/**
@@ -514,8 +516,8 @@ SerialFifoEmpty ( **/
EFI_STATUS
SerialFifoAdd (
- IN SERIAL_DEV_FIFO *Fifo,
- IN UINT8 Data
+ IN SERIAL_DEV_FIFO *Fifo,
+ IN UINT8 Data
);
/**
@@ -530,8 +532,8 @@ SerialFifoAdd ( **/
EFI_STATUS
SerialFifoRemove (
- IN SERIAL_DEV_FIFO *Fifo,
- OUT UINT8 *Data
+ IN SERIAL_DEV_FIFO *Fifo,
+ OUT UINT8 *Data
);
/**
@@ -546,7 +548,7 @@ SerialFifoRemove ( **/
EFI_STATUS
SerialReceiveTransmit (
- IN SERIAL_DEV *SerialDevice
+ IN SERIAL_DEV *SerialDevice
);
/**
@@ -559,8 +561,8 @@ SerialReceiveTransmit ( **/
UINT8
SerialReadRegister (
- IN SERIAL_DEV *SerialDev,
- IN UINT32 Offset
+ IN SERIAL_DEV *SerialDev,
+ IN UINT32 Offset
);
/**
@@ -572,15 +574,15 @@ SerialReadRegister ( **/
VOID
SerialWriteRegister (
- IN SERIAL_DEV *SerialDev,
- IN UINT32 Offset,
- IN UINT8 Data
+ IN SERIAL_DEV *SerialDev,
+ IN UINT32 Offset,
+ IN UINT8 Data
);
-
//
// EFI Component Name Functions
//
+
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -628,7 +630,6 @@ SerialComponentNameGetDriverName ( OUT CHAR16 **DriverName
);
-
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -700,11 +701,11 @@ SerialComponentNameGetDriverName ( EFI_STATUS
EFIAPI
SerialComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
/**
@@ -715,8 +716,8 @@ SerialComponentNameGetControllerName ( **/
VOID
AddName (
- IN SERIAL_DEV *SerialDevice,
- IN UINT32 Uid
+ IN SERIAL_DEV *SerialDevice,
+ IN UINT32 Uid
);
/**
@@ -741,13 +742,13 @@ AddName ( **/
BOOLEAN
VerifyUartParameters (
- IN UINT32 ClockRate,
- IN UINT64 BaudRate,
- IN UINT8 DataBits,
- IN EFI_PARITY_TYPE Parity,
- IN EFI_STOP_BITS_TYPE StopBits,
- OUT UINT64 *Divisor,
- OUT UINT64 *ActualBaudRate
+ IN UINT32 ClockRate,
+ IN UINT64 BaudRate,
+ IN UINT8 DataBits,
+ IN EFI_PARITY_TYPE Parity,
+ IN EFI_STOP_BITS_TYPE StopBits,
+ OUT UINT64 *Divisor,
+ OUT UINT64 *ActualBaudRate
);
/**
@@ -762,9 +763,9 @@ VerifyUartParameters ( **/
UART_DEVICE_PATH *
SkipControllerDevicePathNode (
- EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- BOOLEAN *ContainsControllerNode,
- UINT32 *ControllerNumber
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ BOOLEAN *ContainsControllerNode,
+ UINT32 *ControllerNumber
);
/**
@@ -778,6 +779,7 @@ SkipControllerDevicePathNode ( **/
BOOLEAN
IsUartFlowControlDevicePathNode (
- IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
+ IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl
);
+
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c index f8b9a0e3ee..8a85a6c3b8 100644 --- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c +++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c @@ -20,27 +20,31 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
UART_DEVICE_PATH *
SkipControllerDevicePathNode (
- EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- BOOLEAN *ContainsControllerNode,
- UINT32 *ControllerNumber
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ BOOLEAN *ContainsControllerNode,
+ UINT32 *ControllerNumber
)
{
if ((DevicePathType (DevicePath) == HARDWARE_DEVICE_PATH) &&
(DevicePathSubType (DevicePath) == HW_CONTROLLER_DP)
- ) {
+ )
+ {
if (ContainsControllerNode != NULL) {
*ContainsControllerNode = TRUE;
}
+
if (ControllerNumber != NULL) {
- *ControllerNumber = ((CONTROLLER_DEVICE_PATH *) DevicePath)->ControllerNumber;
+ *ControllerNumber = ((CONTROLLER_DEVICE_PATH *)DevicePath)->ControllerNumber;
}
+
DevicePath = NextDevicePathNode (DevicePath);
} else {
if (ContainsControllerNode != NULL) {
*ContainsControllerNode = FALSE;
}
}
- return (UART_DEVICE_PATH *) DevicePath;
+
+ return (UART_DEVICE_PATH *)DevicePath;
}
/**
@@ -65,26 +69,27 @@ SkipControllerDevicePathNode ( **/
BOOLEAN
VerifyUartParameters (
- IN UINT32 ClockRate,
- IN UINT64 BaudRate,
- IN UINT8 DataBits,
- IN EFI_PARITY_TYPE Parity,
- IN EFI_STOP_BITS_TYPE StopBits,
- OUT UINT64 *Divisor,
- OUT UINT64 *ActualBaudRate
+ IN UINT32 ClockRate,
+ IN UINT64 BaudRate,
+ IN UINT8 DataBits,
+ IN EFI_PARITY_TYPE Parity,
+ IN EFI_STOP_BITS_TYPE StopBits,
+ OUT UINT64 *Divisor,
+ OUT UINT64 *ActualBaudRate
)
{
- UINT64 Remainder;
- UINT32 ComputedBaudRate;
- UINT64 ComputedDivisor;
- UINT64 Percent;
+ UINT64 Remainder;
+ UINT32 ComputedBaudRate;
+ UINT64 ComputedDivisor;
+ UINT64 Percent;
if ((DataBits < 5) || (DataBits > 8) ||
(Parity < NoParity) || (Parity > SpaceParity) ||
(StopBits < OneStopBit) || (StopBits > TwoStopBits) ||
((DataBits == 5) && (StopBits == TwoStopBits)) ||
((DataBits >= 6) && (DataBits <= 8) && (StopBits == OneFiveStopBits))
- ) {
+ )
+ {
return FALSE;
}
@@ -108,6 +113,7 @@ VerifyUartParameters ( if (Remainder >= LShiftU64 (BaudRate, 3)) {
ComputedDivisor++;
}
+
//
// If the computed divisor is larger than the maximum value that can be programmed
// into the UART, then the requested baud rate can not be supported.
@@ -128,13 +134,13 @@ VerifyUartParameters ( // Actual baud rate that the serial port will be programmed for
// should be with in 4% of requested one.
//
- ComputedBaudRate = ClockRate / ((UINT16) ComputedDivisor << 4);
+ ComputedBaudRate = ClockRate / ((UINT16)ComputedDivisor << 4);
if (ComputedBaudRate == 0) {
return FALSE;
}
Percent = DivU64x32 (MultU64x32 (BaudRate, 100), ComputedBaudRate);
- DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
+ DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((DEBUG_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
@@ -147,18 +153,23 @@ VerifyUartParameters ( if (ActualBaudRate != NULL) {
*ActualBaudRate = BaudRate;
}
+
if (Divisor != NULL) {
*Divisor = ComputedDivisor;
}
+
return TRUE;
}
+
if (ComputedBaudRate < BaudRate) {
if (ActualBaudRate != NULL) {
*ActualBaudRate = ComputedBaudRate;
}
+
if (Divisor != NULL) {
*Divisor = ComputedDivisor;
}
+
return TRUE;
}
@@ -170,22 +181,25 @@ VerifyUartParameters ( if (ComputedDivisor == MAX_UINT16) {
return FALSE;
}
+
ComputedDivisor++;
- ComputedBaudRate = ClockRate / ((UINT16) ComputedDivisor << 4);
+ ComputedBaudRate = ClockRate / ((UINT16)ComputedDivisor << 4);
if (ComputedBaudRate == 0) {
return FALSE;
}
- DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
+ DEBUG ((DEBUG_INFO, "ClockRate = %d\n", ClockRate));
DEBUG ((DEBUG_INFO, "Divisor = %ld\n", ComputedDivisor));
DEBUG ((DEBUG_INFO, "BaudRate/Actual (%ld/%d) = %d%%\n", BaudRate, ComputedBaudRate, Percent));
if (ActualBaudRate != NULL) {
*ActualBaudRate = ComputedBaudRate;
}
+
if (Divisor != NULL) {
*Divisor = ComputedDivisor;
}
+
return TRUE;
}
@@ -198,10 +212,10 @@ VerifyUartParameters ( **/
BOOLEAN
SerialFifoFull (
- IN SERIAL_DEV_FIFO *Fifo
+ IN SERIAL_DEV_FIFO *Fifo
)
{
- return (BOOLEAN) (((Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE) == Fifo->Head);
+ return (BOOLEAN)(((Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE) == Fifo->Head);
}
/**
@@ -213,11 +227,11 @@ SerialFifoFull ( **/
BOOLEAN
SerialFifoEmpty (
- IN SERIAL_DEV_FIFO *Fifo
+ IN SERIAL_DEV_FIFO *Fifo
)
{
- return (BOOLEAN) (Fifo->Head == Fifo->Tail);
+ return (BOOLEAN)(Fifo->Head == Fifo->Tail);
}
/**
@@ -231,8 +245,8 @@ SerialFifoEmpty ( **/
EFI_STATUS
SerialFifoAdd (
- IN OUT SERIAL_DEV_FIFO *Fifo,
- IN UINT8 Data
+ IN OUT SERIAL_DEV_FIFO *Fifo,
+ IN UINT8 Data
)
{
//
@@ -241,11 +255,12 @@ SerialFifoAdd ( if (SerialFifoFull (Fifo)) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// FIFO is not full can add data
//
Fifo->Data[Fifo->Tail] = Data;
- Fifo->Tail = (Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE;
+ Fifo->Tail = (Fifo->Tail + 1) % SERIAL_MAX_FIFO_SIZE;
return EFI_SUCCESS;
}
@@ -261,8 +276,8 @@ SerialFifoAdd ( **/
EFI_STATUS
SerialFifoRemove (
- IN OUT SERIAL_DEV_FIFO *Fifo,
- OUT UINT8 *Data
+ IN OUT SERIAL_DEV_FIFO *Fifo,
+ OUT UINT8 *Data
)
{
//
@@ -271,10 +286,11 @@ SerialFifoRemove ( if (SerialFifoEmpty (Fifo)) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// FIFO is not empty, can remove data
//
- *Data = Fifo->Data[Fifo->Head];
+ *Data = Fifo->Data[Fifo->Head];
Fifo->Head = (Fifo->Head + 1) % SERIAL_MAX_FIFO_SIZE;
return EFI_SUCCESS;
}
@@ -291,16 +307,16 @@ SerialFifoRemove ( **/
EFI_STATUS
SerialReceiveTransmit (
- IN SERIAL_DEV *SerialDevice
+ IN SERIAL_DEV *SerialDevice
)
{
- SERIAL_PORT_LSR Lsr;
- UINT8 Data;
- BOOLEAN ReceiveFifoFull;
- SERIAL_PORT_MSR Msr;
- SERIAL_PORT_MCR Mcr;
- UINTN TimeOut;
+ SERIAL_PORT_LSR Lsr;
+ UINT8 Data;
+ BOOLEAN ReceiveFifoFull;
+ SERIAL_PORT_MSR Msr;
+ SERIAL_PORT_MCR Mcr;
+ UINTN TimeOut;
Data = 0;
@@ -326,13 +342,15 @@ SerialReceiveTransmit ( // if receive buffer is available.
//
if (SerialDevice->HardwareFlowControl &&
- !FeaturePcdGet(PcdSerialUseHalfHandshake)&&
+ !FeaturePcdGet (PcdSerialUseHalfHandshake) &&
!ReceiveFifoFull
- ) {
+ )
+ {
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.Rts = 1;
WRITE_MCR (SerialDevice, Mcr.Data);
}
+
do {
Lsr.Data = READ_LSR (SerialDevice);
@@ -342,13 +360,13 @@ SerialReceiveTransmit ( if ((Lsr.Bits.Dr == 1) && !ReceiveFifoFull) {
ReceiveFifoFull = SerialFifoFull (&SerialDevice->Receive);
if (!ReceiveFifoFull) {
- if (Lsr.Bits.FIFOe == 1 || Lsr.Bits.Oe == 1 || Lsr.Bits.Pe == 1 || Lsr.Bits.Fe == 1 || Lsr.Bits.Bi == 1) {
+ if ((Lsr.Bits.FIFOe == 1) || (Lsr.Bits.Oe == 1) || (Lsr.Bits.Pe == 1) || (Lsr.Bits.Fe == 1) || (Lsr.Bits.Bi == 1)) {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
EFI_ERROR_CODE,
EFI_P_EC_INPUT_ERROR | EFI_PERIPHERAL_SERIAL_PORT,
SerialDevice->DevicePath
);
- if (Lsr.Bits.FIFOe == 1 || Lsr.Bits.Pe == 1|| Lsr.Bits.Fe == 1 || Lsr.Bits.Bi == 1) {
+ if ((Lsr.Bits.FIFOe == 1) || (Lsr.Bits.Pe == 1) || (Lsr.Bits.Fe == 1) || (Lsr.Bits.Bi == 1)) {
Data = READ_RBR (SerialDevice);
continue;
}
@@ -363,15 +381,15 @@ SerialReceiveTransmit ( // tell the peer to stop sending data.
//
if (SerialDevice->HardwareFlowControl &&
- !FeaturePcdGet(PcdSerialUseHalfHandshake) &&
+ !FeaturePcdGet (PcdSerialUseHalfHandshake) &&
SerialFifoFull (&SerialDevice->Receive)
- ) {
+ )
+ {
Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.Rts = 0;
WRITE_MCR (SerialDevice, Mcr.Data);
}
-
continue;
} else {
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
@@ -381,10 +399,11 @@ SerialReceiveTransmit ( );
}
}
+
//
// Do the write
//
- if (Lsr.Bits.Thre == 1 && !SerialFifoEmpty (&SerialDevice->Transmit)) {
+ if ((Lsr.Bits.Thre == 1) && !SerialFifoEmpty (&SerialDevice->Transmit)) {
//
// Make sure the transmit data will not be missed
//
@@ -392,17 +411,18 @@ SerialReceiveTransmit ( //
// For half handshake flow control assert RTS before sending.
//
- if (FeaturePcdGet(PcdSerialUseHalfHandshake)) {
+ if (FeaturePcdGet (PcdSerialUseHalfHandshake)) {
Mcr.Data = READ_MCR (SerialDevice);
- Mcr.Bits.Rts= 0;
+ Mcr.Bits.Rts = 0;
WRITE_MCR (SerialDevice, Mcr.Data);
}
+
//
// Wait for CTS
//
- TimeOut = 0;
- Msr.Data = READ_MSR (SerialDevice);
- while ((Msr.Bits.Dcd == 1) && ((Msr.Bits.Cts == 0) ^ FeaturePcdGet(PcdSerialUseHalfHandshake))) {
+ TimeOut = 0;
+ Msr.Data = READ_MSR (SerialDevice);
+ while ((Msr.Bits.Dcd == 1) && ((Msr.Bits.Cts == 0) ^ FeaturePcdGet (PcdSerialUseHalfHandshake))) {
gBS->Stall (TIMEOUT_STALL_INTERVAL);
TimeOut++;
if (TimeOut > 5) {
@@ -412,7 +432,7 @@ SerialReceiveTransmit ( Msr.Data = READ_MSR (SerialDevice);
}
- if ((Msr.Bits.Dcd == 0) || ((Msr.Bits.Cts == 1) ^ FeaturePcdGet(PcdSerialUseHalfHandshake))) {
+ if ((Msr.Bits.Dcd == 0) || ((Msr.Bits.Cts == 1) ^ FeaturePcdGet (PcdSerialUseHalfHandshake))) {
SerialFifoRemove (&SerialDevice->Transmit, &Data);
WRITE_THR (SerialDevice, Data);
}
@@ -420,8 +440,8 @@ SerialReceiveTransmit ( //
// For half handshake flow control, tell DCE we are done.
//
- if (FeaturePcdGet(PcdSerialUseHalfHandshake)) {
- Mcr.Data = READ_MCR (SerialDevice);
+ if (FeaturePcdGet (PcdSerialUseHalfHandshake)) {
+ Mcr.Data = READ_MCR (SerialDevice);
Mcr.Bits.Rts = 1;
WRITE_MCR (SerialDevice, Mcr.Data);
}
@@ -484,12 +504,13 @@ SerialFlushTransmitFifo ( // in the rest of this function that may send additional characters to this
// UART device invalidating the flush operation.
//
- Elapsed = 0;
+ Elapsed = 0;
Lsr.Data = READ_LSR (SerialDevice);
while (Lsr.Bits.Temt == 0 || Lsr.Bits.Thre == 0) {
if (Elapsed >= Timeout) {
return EFI_TIMEOUT;
}
+
gBS->Stall (TIMEOUT_STALL_INTERVAL);
Elapsed += TIMEOUT_STALL_INTERVAL;
Lsr.Data = READ_LSR (SerialDevice);
@@ -501,6 +522,7 @@ SerialFlushTransmitFifo ( //
// Interface Functions
//
+
/**
Reset serial device.
@@ -516,14 +538,14 @@ SerialReset ( IN EFI_SERIAL_IO_PROTOCOL *This
)
{
- EFI_STATUS Status;
- SERIAL_DEV *SerialDevice;
- SERIAL_PORT_LCR Lcr;
- SERIAL_PORT_IER Ier;
- SERIAL_PORT_MCR Mcr;
- SERIAL_PORT_FCR Fcr;
- EFI_TPL Tpl;
- UINT32 Control;
+ EFI_STATUS Status;
+ SERIAL_DEV *SerialDevice;
+ SERIAL_PORT_LCR Lcr;
+ SERIAL_PORT_IER Ier;
+ SERIAL_PORT_MCR Mcr;
+ SERIAL_PORT_FCR Fcr;
+ EFI_TPL Tpl;
+ UINT32 Control;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
@@ -557,17 +579,17 @@ SerialReset ( //
// Turn off all interrupts
//
- Ier.Data = READ_IER (SerialDevice);
- Ier.Bits.Ravie = 0;
- Ier.Bits.Theie = 0;
- Ier.Bits.Rie = 0;
- Ier.Bits.Mie = 0;
+ Ier.Data = READ_IER (SerialDevice);
+ Ier.Bits.Ravie = 0;
+ Ier.Bits.Theie = 0;
+ Ier.Bits.Rie = 0;
+ Ier.Bits.Mie = 0;
WRITE_IER (SerialDevice, Ier.Data);
//
// Reset the FIFO
//
- Fcr.Data = 0;
+ Fcr.Data = 0;
Fcr.Bits.TrFIFOE = 0;
WRITE_FCR (SerialDevice, Fcr.Data);
@@ -588,12 +610,13 @@ SerialReset ( //
// Enable FIFO
//
- Fcr.Bits.TrFIFOE = 1;
+ Fcr.Bits.TrFIFOE = 1;
if (SerialDevice->ReceiveFifoDepth > 16) {
Fcr.Bits.TrFIFO64 = 1;
}
- Fcr.Bits.ResetRF = 1;
- Fcr.Bits.ResetTF = 1;
+
+ Fcr.Bits.ResetRF = 1;
+ Fcr.Bits.ResetTF = 1;
WRITE_FCR (SerialDevice, Fcr.Data);
//
@@ -604,15 +627,16 @@ SerialReset ( This->Mode->BaudRate,
This->Mode->ReceiveFifoDepth,
This->Mode->Timeout,
- (EFI_PARITY_TYPE) This->Mode->Parity,
- (UINT8) This->Mode->DataBits,
- (EFI_STOP_BITS_TYPE) This->Mode->StopBits
+ (EFI_PARITY_TYPE)This->Mode->Parity,
+ (UINT8)This->Mode->DataBits,
+ (EFI_STOP_BITS_TYPE)This->Mode->StopBits
);
if (EFI_ERROR (Status)) {
gBS->RestoreTPL (Tpl);
return EFI_DEVICE_ERROR;
}
+
//
// Go set the current control bits
//
@@ -620,9 +644,11 @@ SerialReset ( if (SerialDevice->HardwareFlowControl) {
Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
}
+
if (SerialDevice->SoftwareLoopbackEnable) {
Control |= EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
}
+
Status = This->SetControl (
This,
Control
@@ -636,7 +662,7 @@ SerialReset ( //
// Reset the software FIFO
//
- SerialDevice->Receive.Head = SerialDevice->Receive.Tail = 0;
+ SerialDevice->Receive.Head = SerialDevice->Receive.Tail = 0;
SerialDevice->Transmit.Head = SerialDevice->Transmit.Tail = 0;
gBS->RestoreTPL (Tpl);
@@ -675,12 +701,12 @@ SerialSetAttributes ( IN EFI_STOP_BITS_TYPE StopBits
)
{
- EFI_STATUS Status;
- SERIAL_DEV *SerialDevice;
- UINT64 Divisor;
- SERIAL_PORT_LCR Lcr;
- UART_DEVICE_PATH *Uart;
- EFI_TPL Tpl;
+ EFI_STATUS Status;
+ SERIAL_DEV *SerialDevice;
+ UINT64 Divisor;
+ SERIAL_PORT_LCR Lcr;
+ UART_DEVICE_PATH *Uart;
+ EFI_TPL Tpl;
SerialDevice = SERIAL_DEV_FROM_THIS (This);
@@ -700,7 +726,7 @@ SerialSetAttributes ( }
if (Parity == DefaultParity) {
- Parity = (EFI_PARITY_TYPE) PcdGet8 (PcdUartDefaultParity);
+ Parity = (EFI_PARITY_TYPE)PcdGet8 (PcdUartDefaultParity);
}
if (DataBits == 0) {
@@ -708,7 +734,7 @@ SerialSetAttributes ( }
if (StopBits == DefaultStopBits) {
- StopBits = (EFI_STOP_BITS_TYPE) PcdGet8 (PcdUartDefaultStopBits);
+ StopBits = (EFI_STOP_BITS_TYPE)PcdGet8 (PcdUartDefaultStopBits);
}
if (!VerifyUartParameters (SerialDevice->ClockRate, BaudRate, DataBits, Parity, StopBits, &Divisor, &BaudRate)) {
@@ -744,8 +770,8 @@ SerialSetAttributes ( //
// Write the divisor to the serial port
//
- WRITE_DLL (SerialDevice, (UINT8) Divisor);
- WRITE_DLM (SerialDevice, (UINT8) ((UINT16) Divisor >> 8));
+ WRITE_DLL (SerialDevice, (UINT8)Divisor);
+ WRITE_DLM (SerialDevice, (UINT8)((UINT16)Divisor >> 8));
//
// Put serial port back in normal mode and set remaining attributes.
@@ -753,98 +779,100 @@ SerialSetAttributes ( Lcr.Bits.DLab = 0;
switch (Parity) {
- case NoParity:
- Lcr.Bits.ParEn = 0;
- Lcr.Bits.EvenPar = 0;
- Lcr.Bits.SticPar = 0;
- break;
-
- case EvenParity:
- Lcr.Bits.ParEn = 1;
- Lcr.Bits.EvenPar = 1;
- Lcr.Bits.SticPar = 0;
- break;
-
- case OddParity:
- Lcr.Bits.ParEn = 1;
- Lcr.Bits.EvenPar = 0;
- Lcr.Bits.SticPar = 0;
- break;
-
- case SpaceParity:
- Lcr.Bits.ParEn = 1;
- Lcr.Bits.EvenPar = 1;
- Lcr.Bits.SticPar = 1;
- break;
-
- case MarkParity:
- Lcr.Bits.ParEn = 1;
- Lcr.Bits.EvenPar = 0;
- Lcr.Bits.SticPar = 1;
- break;
-
- default:
- break;
+ case NoParity:
+ Lcr.Bits.ParEn = 0;
+ Lcr.Bits.EvenPar = 0;
+ Lcr.Bits.SticPar = 0;
+ break;
+
+ case EvenParity:
+ Lcr.Bits.ParEn = 1;
+ Lcr.Bits.EvenPar = 1;
+ Lcr.Bits.SticPar = 0;
+ break;
+
+ case OddParity:
+ Lcr.Bits.ParEn = 1;
+ Lcr.Bits.EvenPar = 0;
+ Lcr.Bits.SticPar = 0;
+ break;
+
+ case SpaceParity:
+ Lcr.Bits.ParEn = 1;
+ Lcr.Bits.EvenPar = 1;
+ Lcr.Bits.SticPar = 1;
+ break;
+
+ case MarkParity:
+ Lcr.Bits.ParEn = 1;
+ Lcr.Bits.EvenPar = 0;
+ Lcr.Bits.SticPar = 1;
+ break;
+
+ default:
+ break;
}
switch (StopBits) {
- case OneStopBit:
- Lcr.Bits.StopB = 0;
- break;
+ case OneStopBit:
+ Lcr.Bits.StopB = 0;
+ break;
- case OneFiveStopBits:
- case TwoStopBits:
- Lcr.Bits.StopB = 1;
- break;
+ case OneFiveStopBits:
+ case TwoStopBits:
+ Lcr.Bits.StopB = 1;
+ break;
- default:
- break;
+ default:
+ break;
}
+
//
// DataBits
//
- Lcr.Bits.SerialDB = (UINT8) ((DataBits - 5) & 0x03);
+ Lcr.Bits.SerialDB = (UINT8)((DataBits - 5) & 0x03);
WRITE_LCR (SerialDevice, Lcr.Data);
//
// Set the Serial I/O mode
//
- This->Mode->BaudRate = BaudRate;
- This->Mode->ReceiveFifoDepth = ReceiveFifoDepth;
- This->Mode->Timeout = Timeout;
- This->Mode->Parity = Parity;
- This->Mode->DataBits = DataBits;
- This->Mode->StopBits = StopBits;
+ This->Mode->BaudRate = BaudRate;
+ This->Mode->ReceiveFifoDepth = ReceiveFifoDepth;
+ This->Mode->Timeout = Timeout;
+ This->Mode->Parity = Parity;
+ This->Mode->DataBits = DataBits;
+ This->Mode->StopBits = StopBits;
//
// See if Device Path Node has actually changed
//
- if (SerialDevice->UartDevicePath.BaudRate == BaudRate &&
- SerialDevice->UartDevicePath.DataBits == DataBits &&
- SerialDevice->UartDevicePath.Parity == Parity &&
- SerialDevice->UartDevicePath.StopBits == StopBits
- ) {
+ if ((SerialDevice->UartDevicePath.BaudRate == BaudRate) &&
+ (SerialDevice->UartDevicePath.DataBits == DataBits) &&
+ (SerialDevice->UartDevicePath.Parity == Parity) &&
+ (SerialDevice->UartDevicePath.StopBits == StopBits)
+ )
+ {
gBS->RestoreTPL (Tpl);
return EFI_SUCCESS;
}
+
//
// Update the device path
//
SerialDevice->UartDevicePath.BaudRate = BaudRate;
SerialDevice->UartDevicePath.DataBits = DataBits;
- SerialDevice->UartDevicePath.Parity = (UINT8) Parity;
- SerialDevice->UartDevicePath.StopBits = (UINT8) StopBits;
+ SerialDevice->UartDevicePath.Parity = (UINT8)Parity;
+ SerialDevice->UartDevicePath.StopBits = (UINT8)StopBits;
Status = EFI_SUCCESS;
if (SerialDevice->Handle != NULL) {
-
//
// Skip the optional Controller device path node
//
Uart = SkipControllerDevicePathNode (
- (EFI_DEVICE_PATH_PROTOCOL *) (
- (UINT8 *) SerialDevice->DevicePath + GetDevicePathSize (SerialDevice->ParentDevicePath) - END_DEVICE_PATH_LENGTH
- ),
+ (EFI_DEVICE_PATH_PROTOCOL *)(
+ (UINT8 *)SerialDevice->DevicePath + GetDevicePathSize (SerialDevice->ParentDevicePath) - END_DEVICE_PATH_LENGTH
+ ),
NULL,
NULL
);
@@ -879,11 +907,11 @@ SerialSetControl ( IN UINT32 Control
)
{
- SERIAL_DEV *SerialDevice;
- SERIAL_PORT_MCR Mcr;
- EFI_TPL Tpl;
- UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
- EFI_STATUS Status;
+ SERIAL_DEV *SerialDevice;
+ SERIAL_PORT_MCR Mcr;
+ EFI_TPL Tpl;
+ UART_FLOW_CONTROL_DEVICE_PATH *FlowControl;
+ EFI_STATUS Status;
//
// The control bits that can be set are :
@@ -900,7 +928,8 @@ SerialSetControl ( //
if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE | EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE |
- EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
+ EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0)
+ {
return EFI_UNSUPPORTED;
}
@@ -915,12 +944,12 @@ SerialSetControl ( //
SerialFlushTransmitFifo (SerialDevice);
- Mcr.Data = READ_MCR (SerialDevice);
- Mcr.Bits.DtrC = 0;
- Mcr.Bits.Rts = 0;
- Mcr.Bits.Lme = 0;
+ Mcr.Data = READ_MCR (SerialDevice);
+ Mcr.Bits.DtrC = 0;
+ Mcr.Bits.Rts = 0;
+ Mcr.Bits.Lme = 0;
SerialDevice->SoftwareLoopbackEnable = FALSE;
- SerialDevice->HardwareFlowControl = FALSE;
+ SerialDevice->HardwareFlowControl = FALSE;
if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
Mcr.Bits.DtrC = 1;
@@ -946,14 +975,15 @@ SerialSetControl ( Status = EFI_SUCCESS;
if (SerialDevice->Handle != NULL) {
- FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *) (
- (UINTN) SerialDevice->DevicePath
- + GetDevicePathSize (SerialDevice->ParentDevicePath)
- - END_DEVICE_PATH_LENGTH
- + sizeof (UART_DEVICE_PATH)
- );
+ FlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *)(
+ (UINTN)SerialDevice->DevicePath
+ + GetDevicePathSize (SerialDevice->ParentDevicePath)
+ - END_DEVICE_PATH_LENGTH
+ + sizeof (UART_DEVICE_PATH)
+ );
if (IsUartFlowControlDevicePathNode (FlowControl) &&
- ((BOOLEAN) (ReadUnaligned32 (&FlowControl->FlowControlMap) == UART_FLOW_CONTROL_HARDWARE) != SerialDevice->HardwareFlowControl)) {
+ ((BOOLEAN)(ReadUnaligned32 (&FlowControl->FlowControlMap) == UART_FLOW_CONTROL_HARDWARE) != SerialDevice->HardwareFlowControl))
+ {
//
// Flow Control setting is changed, need to reinstall device path protocol
//
@@ -988,16 +1018,16 @@ SerialGetControl ( OUT UINT32 *Control
)
{
- SERIAL_DEV *SerialDevice;
- SERIAL_PORT_MSR Msr;
- SERIAL_PORT_MCR Mcr;
- EFI_TPL Tpl;
+ SERIAL_DEV *SerialDevice;
+ SERIAL_PORT_MSR Msr;
+ SERIAL_PORT_MCR Mcr;
+ EFI_TPL Tpl;
- Tpl = gBS->RaiseTPL (TPL_NOTIFY);
+ Tpl = gBS->RaiseTPL (TPL_NOTIFY);
- SerialDevice = SERIAL_DEV_FROM_THIS (This);
+ SerialDevice = SERIAL_DEV_FROM_THIS (This);
- *Control = 0;
+ *Control = 0;
//
// Read the Modem Status Register
@@ -1019,6 +1049,7 @@ SerialGetControl ( if (Msr.Bits.Dcd == 1) {
*Control |= EFI_SERIAL_CARRIER_DETECT;
}
+
//
// Read the Modem Control Register
//
@@ -1039,6 +1070,7 @@ SerialGetControl ( if (SerialDevice->HardwareFlowControl) {
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
}
+
//
// Update FIFO status
//
@@ -1097,9 +1129,9 @@ SerialWrite ( UINTN Timeout;
UINTN BitsPerCharacter;
- SerialDevice = SERIAL_DEV_FROM_THIS (This);
- Elapsed = 0;
- ActualWrite = 0;
+ SerialDevice = SERIAL_DEV_FROM_THIS (This);
+ Elapsed = 0;
+ ActualWrite = 0;
if (*BufferSize == 0) {
return EFI_SUCCESS;
@@ -1115,9 +1147,9 @@ SerialWrite ( return EFI_DEVICE_ERROR;
}
- Tpl = gBS->RaiseTPL (TPL_NOTIFY);
+ Tpl = gBS->RaiseTPL (TPL_NOTIFY);
- CharBuffer = (UINT8 *) Buffer;
+ CharBuffer = (UINT8 *)Buffer;
//
// Compute the number of bits in a single character. This is a start bit,
@@ -1143,10 +1175,10 @@ SerialWrite ( Timeout = MAX (
This->Mode->Timeout,
(UINTN)DivU64x64Remainder (
- BitsPerCharacter * (SerialDevice->TransmitFifoDepth + 1) * 1000000,
- This->Mode->BaudRate,
- NULL
- )
+ BitsPerCharacter * (SerialDevice->TransmitFifoDepth + 1) * 1000000,
+ This->Mode->BaudRate,
+ NULL
+ )
);
for (Index = 0; Index < *BufferSize; Index++) {
@@ -1208,8 +1240,8 @@ SerialRead ( EFI_STATUS Status;
EFI_TPL Tpl;
- SerialDevice = SERIAL_DEV_FROM_THIS (This);
- Elapsed = 0;
+ SerialDevice = SERIAL_DEV_FROM_THIS (This);
+ Elapsed = 0;
if (*BufferSize == 0) {
return EFI_SUCCESS;
@@ -1219,9 +1251,9 @@ SerialRead ( return EFI_DEVICE_ERROR;
}
- Tpl = gBS->RaiseTPL (TPL_NOTIFY);
+ Tpl = gBS->RaiseTPL (TPL_NOTIFY);
- Status = SerialReceiveTransmit (SerialDevice);
+ Status = SerialReceiveTransmit (SerialDevice);
if (EFI_ERROR (Status)) {
*BufferSize = 0;
@@ -1237,7 +1269,7 @@ SerialRead ( return EFI_DEVICE_ERROR;
}
- CharBuffer = (UINT8 *) Buffer;
+ CharBuffer = (UINT8 *)Buffer;
for (Index = 0; Index < *BufferSize; Index++) {
while (SerialFifoRemove (&SerialDevice->Receive, &(CharBuffer[Index])) != EFI_SUCCESS) {
//
@@ -1261,6 +1293,7 @@ SerialRead ( return EFI_DEVICE_ERROR;
}
}
+
//
// Successful read so reset timeout
//
@@ -1283,12 +1316,12 @@ SerialRead ( **/
BOOLEAN
SerialPresent (
- IN SERIAL_DEV *SerialDevice
+ IN SERIAL_DEV *SerialDevice
)
{
- UINT8 Temp;
- BOOLEAN Status;
+ UINT8 Temp;
+ BOOLEAN Status;
Status = TRUE;
@@ -1307,6 +1340,7 @@ SerialPresent ( if (READ_SCR (SerialDevice) != 0x55) {
Status = FALSE;
}
+
//
// Restore SCR
//
@@ -1325,23 +1359,36 @@ SerialPresent ( **/
UINT8
SerialReadRegister (
- IN SERIAL_DEV *SerialDev,
- IN UINT32 Offset
+ IN SERIAL_DEV *SerialDev,
+ IN UINT32 Offset
)
{
- UINT8 Data;
- EFI_STATUS Status;
+ UINT8 Data;
+ EFI_STATUS Status;
if (SerialDev->PciDeviceInfo == NULL) {
- return IoRead8 ((UINTN) SerialDev->BaseAddress + Offset * SerialDev->RegisterStride);
+ return IoRead8 ((UINTN)SerialDev->BaseAddress + Offset * SerialDev->RegisterStride);
} else {
if (SerialDev->MmioAccess) {
- Status = SerialDev->PciDeviceInfo->PciIo->Mem.Read (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
- SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
+ Status = SerialDev->PciDeviceInfo->PciIo->Mem.Read (
+ SerialDev->PciDeviceInfo->PciIo,
+ EfiPciIoWidthUint8,
+ EFI_PCI_IO_PASS_THROUGH_BAR,
+ SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
+ 1,
+ &Data
+ );
} else {
- Status = SerialDev->PciDeviceInfo->PciIo->Io.Read (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
- SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
+ Status = SerialDev->PciDeviceInfo->PciIo->Io.Read (
+ SerialDev->PciDeviceInfo->PciIo,
+ EfiPciIoWidthUint8,
+ EFI_PCI_IO_PASS_THROUGH_BAR,
+ SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
+ 1,
+ &Data
+ );
}
+
ASSERT_EFI_ERROR (Status);
return Data;
}
@@ -1356,23 +1403,36 @@ SerialReadRegister ( **/
VOID
SerialWriteRegister (
- IN SERIAL_DEV *SerialDev,
- IN UINT32 Offset,
- IN UINT8 Data
+ IN SERIAL_DEV *SerialDev,
+ IN UINT32 Offset,
+ IN UINT8 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (SerialDev->PciDeviceInfo == NULL) {
- IoWrite8 ((UINTN) SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, Data);
+ IoWrite8 ((UINTN)SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, Data);
} else {
if (SerialDev->MmioAccess) {
- Status = SerialDev->PciDeviceInfo->PciIo->Mem.Write (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
- SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
+ Status = SerialDev->PciDeviceInfo->PciIo->Mem.Write (
+ SerialDev->PciDeviceInfo->PciIo,
+ EfiPciIoWidthUint8,
+ EFI_PCI_IO_PASS_THROUGH_BAR,
+ SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
+ 1,
+ &Data
+ );
} else {
- Status = SerialDev->PciDeviceInfo->PciIo->Io.Write (SerialDev->PciDeviceInfo->PciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR,
- SerialDev->BaseAddress + Offset * SerialDev->RegisterStride, 1, &Data);
+ Status = SerialDev->PciDeviceInfo->PciIo->Io.Write (
+ SerialDev->PciDeviceInfo->PciIo,
+ EfiPciIoWidthUint8,
+ EFI_PCI_IO_PASS_THROUGH_BAR,
+ SerialDev->BaseAddress + Offset * SerialDev->RegisterStride,
+ 1,
+ &Data
+ );
}
+
ASSERT_EFI_ERROR (Status);
}
}
diff --git a/MdeModulePkg/Bus/Pci/SataControllerDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/SataControllerDxe/ComponentName.c index 5086d77474..9cc416fc1f 100644 --- a/MdeModulePkg/Bus/Pci/SataControllerDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/SataControllerDxe/ComponentName.c @@ -20,16 +20,16 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSataControllerCompon //
/// EFI Component Name 2 Protocol
///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SataControllerComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SataControllerComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)SataControllerComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)SataControllerComponentNameGetControllerName,
"en"
};
//
/// Driver Name Strings
///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverNameTable[] = {
{
"eng;en",
(CHAR16 *)L"Sata Controller Init Driver"
@@ -43,7 +43,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverName ///
/// Controller Name Strings
///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerControllerNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerControllerNameTable[] = {
{
"eng;en",
(CHAR16 *)L"Sata Controller"
@@ -78,9 +78,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerController EFI_STATUS
EFIAPI
SataControllerComponentNameGetDriverName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN CHAR8 *Language,
- OUT CHAR16 **DriverName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -135,14 +135,14 @@ SataControllerComponentNameGetDriverName ( EFI_STATUS
EFIAPI
SataControllerComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Make sure this driver is currently managing ControllHandle
@@ -161,11 +161,10 @@ SataControllerComponentNameGetControllerName ( }
return LookupUnicodeString2 (
- Language,
- This->SupportedLanguages,
- mSataControllerControllerNameTable,
- ControllerName,
- (BOOLEAN)(This == &gSataControllerComponentName)
- );
+ Language,
+ This->SupportedLanguages,
+ mSataControllerControllerNameTable,
+ ControllerName,
+ (BOOLEAN)(This == &gSataControllerComponentName)
+ );
}
-
diff --git a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c index 1133e1c935..f661efaec7 100644 --- a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c +++ b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c @@ -12,7 +12,7 @@ ///
/// EFI_DRIVER_BINDING_PROTOCOL instance
///
-EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding = {
+EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding = {
SataControllerSupported,
SataControllerStart,
SataControllerStop,
@@ -33,11 +33,11 @@ EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding = { UINT32
EFIAPI
AhciReadReg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (PciIo != NULL);
@@ -47,7 +47,7 @@ AhciReadReg ( PciIo,
EfiPciIoWidthUint32,
AHCI_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -73,21 +73,20 @@ CalculateBestPioMode ( OUT UINT16 *SelectedMode
)
{
- UINT16 PioMode;
- UINT16 AdvancedPioMode;
- UINT16 Temp;
- UINT16 Index;
- UINT16 MinimumPioCycleTime;
+ UINT16 PioMode;
+ UINT16 AdvancedPioMode;
+ UINT16 Temp;
+ UINT16 Index;
+ UINT16 MinimumPioCycleTime;
Temp = 0xff;
- PioMode = (UINT8) (((ATA5_IDENTIFY_DATA *) (&(IdentifyData->AtaData)))->pio_cycle_timing >> 8);
+ PioMode = (UINT8)(((ATA5_IDENTIFY_DATA *)(&(IdentifyData->AtaData)))->pio_cycle_timing >> 8);
//
// See whether Identify Data word 64 - 70 are valid
//
if ((IdentifyData->AtaData.field_validity & 0x02) == 0x02) {
-
AdvancedPioMode = IdentifyData->AtaData.advanced_pio_modes;
DEBUG ((DEBUG_INFO, "CalculateBestPioMode: AdvancedPioMode = %x\n", AdvancedPioMode));
@@ -105,7 +104,7 @@ CalculateBestPioMode ( // the best PIO Mode is the value in pio_cycle_timing.
//
if (Temp != 0xff) {
- AdvancedPioMode = (UINT16) (Temp + 3);
+ AdvancedPioMode = (UINT16)(Temp + 3);
} else {
AdvancedPioMode = PioMode;
}
@@ -113,16 +112,16 @@ CalculateBestPioMode ( //
// Limit the PIO mode to at most PIO4.
//
- PioMode = (UINT16) MIN (AdvancedPioMode, 4);
+ PioMode = (UINT16)MIN (AdvancedPioMode, 4);
MinimumPioCycleTime = IdentifyData->AtaData.min_pio_cycle_time_with_flow_control;
if (MinimumPioCycleTime <= 120) {
- PioMode = (UINT16) MIN (4, PioMode);
+ PioMode = (UINT16)MIN (4, PioMode);
} else if (MinimumPioCycleTime <= 180) {
- PioMode = (UINT16) MIN (3, PioMode);
+ PioMode = (UINT16)MIN (3, PioMode);
} else if (MinimumPioCycleTime <= 240) {
- PioMode = (UINT16) MIN (2, PioMode);
+ PioMode = (UINT16)MIN (2, PioMode);
} else {
PioMode = 0;
}
@@ -136,7 +135,7 @@ CalculateBestPioMode ( }
if (PioMode >= *DisPioMode) {
- PioMode = (UINT16) (*DisPioMode - 1);
+ PioMode = (UINT16)(*DisPioMode - 1);
}
}
@@ -145,7 +144,6 @@ CalculateBestPioMode ( } else {
*SelectedMode = PioMode; // ATA_PIO_MODE_2 to ATA_PIO_MODE_4;
}
-
} else {
//
// Identify Data word 64 - 70 are not valid
@@ -166,7 +164,6 @@ CalculateBestPioMode ( } else {
*SelectedMode = 2; // ATA_PIO_MODE_2;
}
-
}
return EFI_SUCCESS;
@@ -190,8 +187,8 @@ CalculateBestUdmaMode ( OUT UINT16 *SelectedMode
)
{
- UINT16 TempMode;
- UINT16 DeviceUDmaMode;
+ UINT16 TempMode;
+ UINT16 DeviceUDmaMode;
DeviceUDmaMode = 0;
@@ -205,7 +202,7 @@ CalculateBestUdmaMode ( DeviceUDmaMode = IdentifyData->AtaData.ultra_dma_mode;
DEBUG ((DEBUG_INFO, "CalculateBestUdmaMode: DeviceUDmaMode = %x\n", DeviceUDmaMode));
DeviceUDmaMode &= 0x3f;
- TempMode = 0; // initialize it to UDMA-0
+ TempMode = 0; // initialize it to UDMA-0
while ((DeviceUDmaMode >>= 1) != 0) {
TempMode++;
@@ -221,7 +218,7 @@ CalculateBestUdmaMode ( }
if (TempMode >= *DisUDmaMode) {
- TempMode = (UINT16) (*DisUDmaMode - 1);
+ TempMode = (UINT16)(*DisUDmaMode - 1);
}
}
@@ -246,11 +243,11 @@ CalculateBestUdmaMode ( EFI_STATUS
EFIAPI
InitializeSataControllerDriver (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Install driver model protocol(s).
@@ -285,14 +282,14 @@ InitializeSataControllerDriver ( EFI_STATUS
EFIAPI
SataControllerSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- PCI_TYPE00 PciData;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 PciData;
//
// Attempt to open PCI I/O Protocol
@@ -300,7 +297,7 @@ SataControllerSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -348,9 +345,9 @@ SataControllerSupported ( EFI_STATUS
EFIAPI
SataControllerStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
@@ -372,7 +369,7 @@ SataControllerStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -394,8 +391,8 @@ SataControllerStart ( //
// Initialize Sata Private Data
//
- Private->Signature = SATA_CONTROLLER_SIGNATURE;
- Private->PciIo = PciIo;
+ Private->Signature = SATA_CONTROLLER_SIGNATURE;
+ Private->PciIo = PciIo;
Private->IdeInit.GetChannelInfo = IdeInitGetChannelInfo;
Private->IdeInit.NotifyPhase = IdeInitNotifyPhase;
Private->IdeInit.SubmitData = IdeInitSubmitData;
@@ -415,7 +412,7 @@ SataControllerStart ( &Private->OriginalPciAttributes
);
if (EFI_ERROR (Status)) {
- goto Done;
+ goto Done;
}
DEBUG ((
@@ -437,12 +434,12 @@ SataControllerStart ( DEBUG ((DEBUG_INFO, "Supported PCI Attributes = 0x%llx\n", Supports));
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
- Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
if (EFI_ERROR (Status)) {
goto Done;
}
@@ -475,13 +472,16 @@ SataControllerStart ( Status = EFI_UNSUPPORTED;
goto Done;
}
+
MaxPortNumber = 31;
while (MaxPortNumber > 0) {
if ((Data32 & ((UINT32)1 << MaxPortNumber)) != 0) {
break;
}
+
MaxPortNumber--;
}
+
//
// Make the ChannelCount equal to the max port number (0 based) plus 1.
//
@@ -492,13 +492,13 @@ SataControllerStart ( //
Data32 = AhciReadReg (PciIo, R_AHCI_CAP);
DEBUG ((DEBUG_INFO, "HBA Capabilities(CAP) = 0x%x\n", Data32));
- Private->DeviceCount = AHCI_MAX_DEVICES;
+ Private->DeviceCount = AHCI_MAX_DEVICES;
if ((Data32 & B_AHCI_CAP_SPM) == B_AHCI_CAP_SPM) {
Private->DeviceCount = AHCI_MULTI_MAX_DEVICES;
}
}
- TotalCount = (UINTN) (Private->IdeInit.ChannelCount) * (UINTN) (Private->DeviceCount);
+ TotalCount = (UINTN)(Private->IdeInit.ChannelCount) * (UINTN)(Private->DeviceCount);
Private->DisqualifiedModes = AllocateZeroPool ((sizeof (EFI_ATA_COLLECTIVE_MODE)) * TotalCount);
if (Private->DisqualifiedModes == NULL) {
Status = EFI_OUT_OF_RESOURCES;
@@ -529,23 +529,25 @@ SataControllerStart ( Done:
if (EFI_ERROR (Status)) {
-
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
if (Private != NULL) {
if (Private->DisqualifiedModes != NULL) {
FreePool (Private->DisqualifiedModes);
}
+
if (Private->IdentifyData != NULL) {
FreePool (Private->IdentifyData);
}
+
if (Private->IdentifyValid != NULL) {
FreePool (Private->IdentifyValid);
}
+
if (Private->PciAttributesChanged) {
//
// Restore original PCI attributes
@@ -557,6 +559,7 @@ Done: NULL
);
}
+
FreePool (Private);
}
}
@@ -581,10 +584,10 @@ Done: EFI_STATUS
EFIAPI
SataControllerStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -597,7 +600,7 @@ SataControllerStop ( Status = gBS->OpenProtocol (
Controller,
&gEfiIdeControllerInitProtocolGuid,
- (VOID **) &IdeInit,
+ (VOID **)&IdeInit,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -626,12 +629,15 @@ SataControllerStop ( if (Private->DisqualifiedModes != NULL) {
FreePool (Private->DisqualifiedModes);
}
+
if (Private->IdentifyData != NULL) {
FreePool (Private->IdentifyData);
}
+
if (Private->IdentifyValid != NULL) {
FreePool (Private->IdentifyValid);
}
+
if (Private->PciAttributesChanged) {
//
// Restore original PCI attributes
@@ -643,6 +649,7 @@ SataControllerStop ( NULL
);
}
+
FreePool (Private);
}
@@ -691,6 +698,7 @@ FlatDeviceIndex ( //
// Interface functions of IDE_CONTROLLER_INIT protocol
//
+
/**
Returns the information about the specified IDE channel.
@@ -730,18 +738,19 @@ FlatDeviceIndex ( EFI_STATUS
EFIAPI
IdeInitGetChannelInfo (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- OUT BOOLEAN *Enabled,
- OUT UINT8 *MaxDevices
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ OUT BOOLEAN *Enabled,
+ OUT UINT8 *MaxDevices
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
+
Private = SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS (This);
ASSERT (Private != NULL);
if (Channel < This->ChannelCount) {
- *Enabled = TRUE;
+ *Enabled = TRUE;
*MaxDevices = Private->DeviceCount;
return EFI_SUCCESS;
}
@@ -778,9 +787,9 @@ IdeInitGetChannelInfo ( EFI_STATUS
EFIAPI
IdeInitNotifyPhase (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
- IN UINT8 Channel
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
+ IN UINT8 Channel
)
{
return EFI_SUCCESS;
@@ -828,10 +837,10 @@ IdeInitNotifyPhase ( EFI_STATUS
EFIAPI
IdeInitSubmitData (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- IN EFI_IDENTIFY_DATA *IdentifyData
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_IDENTIFY_DATA *IdentifyData
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
@@ -907,10 +916,10 @@ IdeInitSubmitData ( EFI_STATUS
EFIAPI
IdeInitDisqualifyMode (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- IN EFI_ATA_COLLECTIVE_MODE *BadModes
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *BadModes
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
@@ -995,10 +1004,10 @@ IdeInitDisqualifyMode ( EFI_STATUS
EFIAPI
IdeInitCalculateMode (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
)
{
EFI_SATA_CONTROLLER_PRIVATE_DATA *Private;
@@ -1024,8 +1033,8 @@ IdeInitCalculateMode ( DeviceIndex = FlatDeviceIndex (Private, Channel, Device);
- IdentifyData = &(Private->IdentifyData[DeviceIndex]);
- IdentifyValid = Private->IdentifyValid[DeviceIndex];
+ IdentifyData = &(Private->IdentifyData[DeviceIndex]);
+ IdentifyValid = Private->IdentifyValid[DeviceIndex];
DisqualifiedModes = &(Private->DisqualifiedModes[DeviceIndex]);
//
@@ -1037,32 +1046,32 @@ IdeInitCalculateMode ( }
Status = CalculateBestPioMode (
- IdentifyData,
- (DisqualifiedModes->PioMode.Valid ? ((UINT16 *) &(DisqualifiedModes->PioMode.Mode)) : NULL),
- &SelectedMode
- );
+ IdentifyData,
+ (DisqualifiedModes->PioMode.Valid ? ((UINT16 *)&(DisqualifiedModes->PioMode.Mode)) : NULL),
+ &SelectedMode
+ );
if (!EFI_ERROR (Status)) {
(*SupportedModes)->PioMode.Valid = TRUE;
- (*SupportedModes)->PioMode.Mode = SelectedMode;
-
+ (*SupportedModes)->PioMode.Mode = SelectedMode;
} else {
(*SupportedModes)->PioMode.Valid = FALSE;
}
+
DEBUG ((DEBUG_INFO, "IdeInitCalculateMode: PioMode = %x\n", (*SupportedModes)->PioMode.Mode));
Status = CalculateBestUdmaMode (
- IdentifyData,
- (DisqualifiedModes->UdmaMode.Valid ? ((UINT16 *) &(DisqualifiedModes->UdmaMode.Mode)) : NULL),
- &SelectedMode
- );
+ IdentifyData,
+ (DisqualifiedModes->UdmaMode.Valid ? ((UINT16 *)&(DisqualifiedModes->UdmaMode.Mode)) : NULL),
+ &SelectedMode
+ );
if (!EFI_ERROR (Status)) {
(*SupportedModes)->UdmaMode.Valid = TRUE;
(*SupportedModes)->UdmaMode.Mode = SelectedMode;
-
} else {
(*SupportedModes)->UdmaMode.Valid = FALSE;
}
+
DEBUG ((DEBUG_INFO, "IdeInitCalculateMode: UdmaMode = %x\n", (*SupportedModes)->UdmaMode.Mode));
//
@@ -1097,10 +1106,10 @@ IdeInitCalculateMode ( EFI_STATUS
EFIAPI
IdeInitSetTiming (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- IN EFI_ATA_COLLECTIVE_MODE *Modes
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *Modes
)
{
return EFI_SUCCESS;
diff --git a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h index 7af3ad855f..4d545fb1f9 100644 --- a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h +++ b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h @@ -30,94 +30,95 @@ //
// Global Variables definitions
//
-extern EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding;
-extern EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2;
-#define AHCI_BAR_INDEX 0x05
-#define R_AHCI_CAP 0x0
-#define B_AHCI_CAP_NPS (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) // Number of Ports
-#define B_AHCI_CAP_SPM BIT17 // Supports Port Multiplier
-#define R_AHCI_PI 0xC
+#define AHCI_BAR_INDEX 0x05
+#define R_AHCI_CAP 0x0
+#define B_AHCI_CAP_NPS (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) // Number of Ports
+#define B_AHCI_CAP_SPM BIT17 // Supports Port Multiplier
+#define R_AHCI_PI 0xC
///
/// AHCI each channel can have up to 1 device
///
-#define AHCI_MAX_DEVICES 0x01
+#define AHCI_MAX_DEVICES 0x01
///
/// AHCI each channel can have 15 devices in the presence of a multiplier
///
-#define AHCI_MULTI_MAX_DEVICES 0x0F
+#define AHCI_MULTI_MAX_DEVICES 0x0F
///
/// IDE supports 2 channel max
///
-#define IDE_MAX_CHANNEL 0x02
+#define IDE_MAX_CHANNEL 0x02
///
/// IDE supports 2 devices max
///
-#define IDE_MAX_DEVICES 0x02
+#define IDE_MAX_DEVICES 0x02
-#define SATA_ENUMER_ALL FALSE
+#define SATA_ENUMER_ALL FALSE
//
// Sata Controller driver private data structure
//
-#define SATA_CONTROLLER_SIGNATURE SIGNATURE_32('S','A','T','A')
+#define SATA_CONTROLLER_SIGNATURE SIGNATURE_32('S','A','T','A')
typedef struct _EFI_SATA_CONTROLLER_PRIVATE_DATA {
//
// Standard signature used to identify Sata Controller private data
//
- UINT32 Signature;
+ UINT32 Signature;
//
// Protocol instance of IDE_CONTROLLER_INIT produced by this driver
//
- EFI_IDE_CONTROLLER_INIT_PROTOCOL IdeInit;
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL IdeInit;
//
// Copy of protocol pointers used by this driver
//
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
//
// The number of devices that are supported by this channel
//
- UINT8 DeviceCount;
+ UINT8 DeviceCount;
//
// The highest disqulified mode for each attached device,
// From ATA/ATAPI spec, if a mode is not supported,
// the modes higher than it is also not supported
//
- EFI_ATA_COLLECTIVE_MODE *DisqualifiedModes;
+ EFI_ATA_COLLECTIVE_MODE *DisqualifiedModes;
//
// A copy of EFI_IDENTIFY_DATA data for each attached SATA device and its flag
//
- EFI_IDENTIFY_DATA *IdentifyData;
- BOOLEAN *IdentifyValid;
+ EFI_IDENTIFY_DATA *IdentifyData;
+ BOOLEAN *IdentifyValid;
//
// Track the state so that the PCI attributes that were modified
// can be restored to the original value later.
//
- BOOLEAN PciAttributesChanged;
+ BOOLEAN PciAttributesChanged;
//
// Copy of the original PCI Attributes
//
- UINT64 OriginalPciAttributes;
+ UINT64 OriginalPciAttributes;
} EFI_SATA_CONTROLLER_PRIVATE_DATA;
-#define SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_SATA_CONTROLLER_PRIVATE_DATA, IdeInit, SATA_CONTROLLER_SIGNATURE)
+#define SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_SATA_CONTROLLER_PRIVATE_DATA, IdeInit, SATA_CONTROLLER_SIGNATURE)
//
// Driver binding functions declaration
//
+
/**
Supported function of Driver Binding protocol for this driver.
Test to see if this driver supports ControllerHandle.
@@ -135,9 +136,9 @@ typedef struct _EFI_SATA_CONTROLLER_PRIVATE_DATA { EFI_STATUS
EFIAPI
SataControllerSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -157,9 +158,9 @@ SataControllerSupported ( EFI_STATUS
EFIAPI
SataControllerStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -177,15 +178,16 @@ SataControllerStart ( EFI_STATUS
EFIAPI
SataControllerStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
//
// IDE controller init functions declaration
//
+
/**
Returns the information about the specified IDE channel.
@@ -226,10 +228,10 @@ SataControllerStop ( EFI_STATUS
EFIAPI
IdeInitGetChannelInfo (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- OUT BOOLEAN *Enabled,
- OUT UINT8 *MaxDevices
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ OUT BOOLEAN *Enabled,
+ OUT UINT8 *MaxDevices
);
/**
@@ -260,9 +262,9 @@ IdeInitGetChannelInfo ( EFI_STATUS
EFIAPI
IdeInitNotifyPhase (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
- IN UINT8 Channel
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
+ IN UINT8 Channel
);
/**
@@ -307,10 +309,10 @@ IdeInitNotifyPhase ( EFI_STATUS
EFIAPI
IdeInitSubmitData (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- IN EFI_IDENTIFY_DATA *IdentifyData
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_IDENTIFY_DATA *IdentifyData
);
/**
@@ -356,10 +358,10 @@ IdeInitSubmitData ( EFI_STATUS
EFIAPI
IdeInitDisqualifyMode (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- IN EFI_ATA_COLLECTIVE_MODE *BadModes
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *BadModes
);
/**
@@ -419,10 +421,10 @@ IdeInitDisqualifyMode ( EFI_STATUS
EFIAPI
IdeInitCalculateMode (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
);
/**
@@ -451,15 +453,16 @@ IdeInitCalculateMode ( EFI_STATUS
EFIAPI
IdeInitSetTiming (
- IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
- IN UINT8 Channel,
- IN UINT8 Device,
- IN EFI_ATA_COLLECTIVE_MODE *Modes
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *Modes
);
//
// Forward reference declaration
//
+
/**
Retrieves a Unicode string that is the user readable name of the UEFI Driver.
@@ -484,9 +487,9 @@ IdeInitSetTiming ( EFI_STATUS
EFIAPI
SataControllerComponentNameGetDriverName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN CHAR8 *Language,
- OUT CHAR16 **DriverName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
);
/**
@@ -532,12 +535,11 @@ SataControllerComponentNameGetDriverName ( EFI_STATUS
EFIAPI
SataControllerComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
#endif
-
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c index c915d37bf3..2301d4ab4d 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c @@ -11,7 +11,7 @@ //
// EFI Component Name Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName = {
SdMmcPciHcComponentNameGetDriverName,
SdMmcPciHcComponentNameGetControllerName,
"eng"
@@ -20,20 +20,20 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentNa //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SdMmcPciHcComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SdMmcPciHcComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)SdMmcPciHcComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)SdMmcPciHcComponentNameGetControllerName,
"en"
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcDriverNameTable[] = {
{ "eng;en", L"Edkii Sd/Mmc Host Controller Driver" },
- { NULL , NULL }
+ { NULL, NULL }
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcControllerNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcControllerNameTable[] = {
{ "eng;en", L"Edkii Sd/Mmc Host Controller" },
- { NULL , NULL }
+ { NULL, NULL }
};
/**
@@ -78,9 +78,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcControllerName EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetDriverName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN CHAR8 *Language,
- OUT CHAR16 **DriverName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -163,16 +163,16 @@ SdMmcPciHcComponentNameGetDriverName ( EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- if (Language == NULL || ControllerName == NULL) {
+ if ((Language == NULL) || (ControllerName == NULL)) {
return EFI_INVALID_PARAMETER;
}
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c index 8b5f8e8ee7..a392a4e31a 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c @@ -24,14 +24,14 @@ **/
EFI_STATUS
EmmcReset (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -41,9 +41,9 @@ EmmcReset ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeBc;
- SdMmcCmdBlk.ResponseType = 0;
+ SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeBc;
+ SdMmcCmdBlk.ResponseType = 0;
SdMmcCmdBlk.CommandArgument = 0;
gBS->Stall (1000);
@@ -74,10 +74,10 @@ EmmcGetOcr ( IN OUT UINT32 *Argument
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -87,9 +87,9 @@ EmmcGetOcr ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
+ SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
SdMmcCmdBlk.CommandArgument = *Argument;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -118,14 +118,14 @@ EmmcGetOcr ( **/
EFI_STATUS
EmmcGetAllCid (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -135,9 +135,9 @@ EmmcGetAllCid ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+ SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
SdMmcCmdBlk.CommandArgument = 0;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -161,15 +161,15 @@ EmmcGetAllCid ( **/
EFI_STATUS
EmmcSetRca (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -179,9 +179,9 @@ EmmcSetRca ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -211,13 +211,13 @@ EmmcGetCsd ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
- OUT EMMC_CSD *Csd
+ OUT EMMC_CSD *Csd
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -227,9 +227,9 @@ EmmcGetCsd ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+ SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -237,7 +237,7 @@ EmmcGetCsd ( //
// For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
//
- CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
+ CopyMem (((UINT8 *)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
}
return Status;
@@ -258,15 +258,15 @@ EmmcGetCsd ( **/
EFI_STATUS
EmmcSelect (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -276,9 +276,9 @@ EmmcSelect ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -303,13 +303,13 @@ EFI_STATUS EmmcGetExtCsd (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
- OUT EMMC_EXT_CSD *ExtCsd
+ OUT EMMC_EXT_CSD *ExtCsd
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -319,9 +319,9 @@ EmmcGetExtCsd ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0x00000000;
Packet.InDataBuffer = ExtCsd;
@@ -350,18 +350,18 @@ EmmcGetExtCsd ( **/
EFI_STATUS
EmmcSwitch (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT8 Access,
- IN UINT8 Index,
- IN UINT8 Value,
- IN UINT8 CmdSet
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT8 Access,
+ IN UINT8 Index,
+ IN UINT8 Value,
+ IN UINT8 CmdSet
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -371,9 +371,9 @@ EmmcSwitch ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SWITCH;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
+ SdMmcCmdBlk.CommandIndex = EMMC_SWITCH;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
SdMmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -400,13 +400,13 @@ EmmcSendStatus ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
- OUT UINT32 *DevStatus
+ OUT UINT32 *DevStatus
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -416,9 +416,9 @@ EmmcSendStatus ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -447,16 +447,16 @@ EmmcSendStatus ( **/
EFI_STATUS
EmmcSendTuningBlk (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT8 BusWidth
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT8 BusWidth
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
- UINT8 TuningBlock[128];
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+ UINT8 TuningBlock[128];
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -466,9 +466,9 @@ EmmcSendTuningBlk ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0;
Packet.InDataBuffer = TuningBlock;
@@ -503,24 +503,25 @@ EmmcSendTuningBlk ( **/
EFI_STATUS
EmmcTuningClkForHs200 (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT8 BusWidth
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT8 BusWidth
)
{
- EFI_STATUS Status;
- UINT8 HostCtrl2;
- UINT8 Retry;
+ EFI_STATUS Status;
+ UINT8 HostCtrl2;
+ UINT8 Retry;
//
// Notify the host that the sampling clock tuning procedure starts.
//
HostCtrl2 = BIT6;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
//
@@ -550,11 +551,12 @@ EmmcTuningClkForHs200 ( //
// Abort the tuning procedure and reset the tuning circuit.
//
- HostCtrl2 = (UINT8)~(BIT6 | BIT7);
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ HostCtrl2 = (UINT8) ~(BIT6 | BIT7);
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
+
return EFI_DEVICE_ERROR;
}
@@ -615,19 +617,19 @@ EmmcCheckSwitchStatus ( **/
EFI_STATUS
EmmcSwitchBusWidth (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN BOOLEAN IsDdr,
- IN UINT8 BusWidth
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN BOOLEAN IsDdr,
+ IN UINT8 BusWidth
)
{
- EFI_STATUS Status;
- UINT8 Access;
- UINT8 Index;
- UINT8 Value;
- UINT8 CmdSet;
+ EFI_STATUS Status;
+ UINT8 Access;
+ UINT8 Index;
+ UINT8 Value;
+ UINT8 CmdSet;
//
// Write Byte, the Value field is written into the byte pointed by Index.
@@ -683,23 +685,23 @@ EmmcSwitchBusWidth ( **/
EFI_STATUS
EmmcSwitchBusTiming (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength,
- IN SD_MMC_BUS_MODE BusTiming,
- IN UINT32 ClockFreq
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength,
+ IN SD_MMC_BUS_MODE BusTiming,
+ IN UINT32 ClockFreq
)
{
- EFI_STATUS Status;
- UINT8 Access;
- UINT8 Index;
- UINT8 Value;
- UINT8 CmdSet;
- SD_MMC_HC_PRIVATE_DATA *Private;
- UINT8 HostCtrl1;
- BOOLEAN DelaySendStatus;
+ EFI_STATUS Status;
+ UINT8 Access;
+ UINT8 Index;
+ UINT8 Value;
+ UINT8 CmdSet;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ UINT8 HostCtrl1;
+ BOOLEAN DelaySendStatus;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
//
@@ -733,15 +735,15 @@ EmmcSwitchBusTiming ( return Status;
}
- if (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcHsDdr) {
+ if ((BusTiming == SdMmcMmcHsSdr) || (BusTiming == SdMmcMmcHsDdr)) {
HostCtrl1 = BIT2;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
} else {
- HostCtrl1 = (UINT8)~BIT2;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ HostCtrl1 = (UINT8) ~BIT2;
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -767,6 +769,7 @@ EmmcSwitchBusTiming ( if (EFI_ERROR (Status)) {
return Status;
}
+
DelaySendStatus = FALSE;
} else {
DelaySendStatus = TRUE;
@@ -808,18 +811,19 @@ EmmcSwitchBusTiming ( **/
EFI_STATUS
EmmcSwitchToHighSpeed (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN SD_MMC_BUS_SETTINGS *BusMode
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN SD_MMC_BUS_SETTINGS *BusMode
)
{
EFI_STATUS Status;
BOOLEAN IsDdr;
- if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != SdMmcMmcHsDdr && BusMode->BusTiming != SdMmcMmcLegacy) ||
- BusMode->ClockFreq > 52) {
+ if (((BusMode->BusTiming != SdMmcMmcHsSdr) && (BusMode->BusTiming != SdMmcMmcHsDdr) && (BusMode->BusTiming != SdMmcMmcLegacy)) ||
+ (BusMode->ClockFreq > 52))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -855,17 +859,18 @@ EmmcSwitchToHighSpeed ( **/
EFI_STATUS
EmmcSwitchToHS200 (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN SD_MMC_BUS_SETTINGS *BusMode
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN SD_MMC_BUS_SETTINGS *BusMode
)
{
EFI_STATUS Status;
- if (BusMode->BusTiming != SdMmcMmcHs200 ||
- (BusMode->BusWidth != 4 && BusMode->BusWidth != 8)) {
+ if ((BusMode->BusTiming != SdMmcMmcHs200) ||
+ ((BusMode->BusWidth != 4) && (BusMode->BusWidth != 8)))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -902,25 +907,26 @@ EmmcSwitchToHS200 ( **/
EFI_STATUS
EmmcSwitchToHS400 (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN SD_MMC_BUS_SETTINGS *BusMode
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN SD_MMC_BUS_SETTINGS *BusMode
)
{
EFI_STATUS Status;
SD_MMC_BUS_SETTINGS Hs200BusMode;
UINT32 HsFreq;
- if (BusMode->BusTiming != SdMmcMmcHs400 ||
- BusMode->BusWidth != 8) {
+ if ((BusMode->BusTiming != SdMmcMmcHs400) ||
+ (BusMode->BusWidth != 8))
+ {
return EFI_INVALID_PARAMETER;
}
- Hs200BusMode.BusTiming = SdMmcMmcHs200;
- Hs200BusMode.BusWidth = BusMode->BusWidth;
- Hs200BusMode.ClockFreq = BusMode->ClockFreq;
+ Hs200BusMode.BusTiming = SdMmcMmcHs200;
+ Hs200BusMode.BusWidth = BusMode->BusWidth;
+ Hs200BusMode.ClockFreq = BusMode->ClockFreq;
Hs200BusMode.DriverStrength = BusMode->DriverStrength;
Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, &Hs200BusMode);
@@ -973,29 +979,34 @@ EmmcIsBusTimingSupported ( Supported = FALSE;
switch (BusTiming) {
case SdMmcMmcHs400:
- if ((((ExtCsd->DeviceType & (BIT6 | BIT7)) != 0) && (Capabilities->Hs400 != 0)) && Capabilities->BusWidth8 != 0) {
+ if ((((ExtCsd->DeviceType & (BIT6 | BIT7)) != 0) && (Capabilities->Hs400 != 0)) && (Capabilities->BusWidth8 != 0)) {
Supported = TRUE;
}
+
break;
case SdMmcMmcHs200:
if ((((ExtCsd->DeviceType & (BIT4 | BIT5)) != 0) && (Capabilities->Sdr104 != 0))) {
Supported = TRUE;
}
+
break;
case SdMmcMmcHsDdr:
if ((((ExtCsd->DeviceType & (BIT2 | BIT3)) != 0) && (Capabilities->Ddr50 != 0))) {
Supported = TRUE;
}
+
break;
case SdMmcMmcHsSdr:
if ((((ExtCsd->DeviceType & BIT1) != 0) && (Capabilities->HighSpeed != 0))) {
Supported = TRUE;
}
+
break;
case SdMmcMmcLegacy:
if ((ExtCsd->DeviceType & BIT0) != 0) {
Supported = TRUE;
}
+
break;
default:
ASSERT (FALSE);
@@ -1018,8 +1029,8 @@ EmmcIsBusTimingSupported ( SD_MMC_BUS_MODE
EmmcGetTargetBusTiming (
IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN EMMC_EXT_CSD *ExtCsd
+ IN UINT8 SlotIndex,
+ IN EMMC_EXT_CSD *ExtCsd
)
{
SD_MMC_BUS_MODE BusTiming;
@@ -1033,6 +1044,7 @@ EmmcGetTargetBusTiming ( if (EmmcIsBusTimingSupported (Private, SlotIndex, ExtCsd, BusTiming)) {
break;
}
+
BusTiming--;
}
@@ -1052,17 +1064,17 @@ EmmcGetTargetBusTiming ( **/
BOOLEAN
EmmcIsBusWidthSupported (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN SD_MMC_BUS_MODE BusTiming,
- IN UINT16 BusWidth
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN SD_MMC_BUS_MODE BusTiming,
+ IN UINT16 BusWidth
)
{
- if (BusWidth == 8 && Private->Capability[SlotIndex].BusWidth8 != 0) {
+ if ((BusWidth == 8) && (Private->Capability[SlotIndex].BusWidth8 != 0)) {
return TRUE;
- } else if (BusWidth == 4 && BusTiming != SdMmcMmcHs400) {
+ } else if ((BusWidth == 4) && (BusTiming != SdMmcMmcHs400)) {
return TRUE;
- } else if (BusWidth == 1 && (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcLegacy)) {
+ } else if ((BusWidth == 1) && ((BusTiming == SdMmcMmcHsSdr) || (BusTiming == SdMmcMmcLegacy))) {
return TRUE;
}
@@ -1081,10 +1093,10 @@ EmmcIsBusWidthSupported ( **/
UINT8
EmmcGetTargetBusWidth (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN EMMC_EXT_CSD *ExtCsd,
- IN SD_MMC_BUS_MODE BusTiming
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN EMMC_EXT_CSD *ExtCsd,
+ IN SD_MMC_BUS_MODE BusTiming
)
{
UINT8 BusWidth;
@@ -1092,8 +1104,9 @@ EmmcGetTargetBusWidth ( PreferredBusWidth = Private->Slot[SlotIndex].OperatingParameters.BusWidth;
- if (PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE &&
- EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, PreferredBusWidth)) {
+ if ((PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE) &&
+ EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, PreferredBusWidth))
+ {
BusWidth = PreferredBusWidth;
} else if (EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, 8)) {
BusWidth = 8;
@@ -1118,14 +1131,14 @@ EmmcGetTargetBusWidth ( **/
UINT32
EmmcGetTargetClockFreq (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN EMMC_EXT_CSD *ExtCsd,
- IN SD_MMC_BUS_MODE BusTiming
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN EMMC_EXT_CSD *ExtCsd,
+ IN SD_MMC_BUS_MODE BusTiming
)
{
- UINT32 PreferredClockFreq;
- UINT32 MaxClockFreq;
+ UINT32 PreferredClockFreq;
+ UINT32 MaxClockFreq;
PreferredClockFreq = Private->Slot[SlotIndex].OperatingParameters.ClockFreq;
@@ -1143,7 +1156,7 @@ EmmcGetTargetClockFreq ( break;
}
- if (PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE && PreferredClockFreq < MaxClockFreq) {
+ if ((PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE) && (PreferredClockFreq < MaxClockFreq)) {
return PreferredClockFreq;
} else {
return MaxClockFreq;
@@ -1162,20 +1175,21 @@ EmmcGetTargetClockFreq ( **/
EDKII_SD_MMC_DRIVER_STRENGTH
EmmcGetTargetDriverStrength (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN EMMC_EXT_CSD *ExtCsd,
- IN SD_MMC_BUS_MODE BusTiming
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN EMMC_EXT_CSD *ExtCsd,
+ IN SD_MMC_BUS_MODE BusTiming
)
{
EDKII_SD_MMC_DRIVER_STRENGTH PreferredDriverStrength;
EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
PreferredDriverStrength = Private->Slot[SlotIndex].OperatingParameters.DriverStrength;
- DriverStrength.Emmc = EmmcDriverStrengthType0;
+ DriverStrength.Emmc = EmmcDriverStrengthType0;
- if (PreferredDriverStrength.Emmc != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE &&
- (ExtCsd->DriverStrength & (BIT0 << PreferredDriverStrength.Emmc))) {
+ if ((PreferredDriverStrength.Emmc != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE) &&
+ (ExtCsd->DriverStrength & (BIT0 << PreferredDriverStrength.Emmc)))
+ {
DriverStrength.Emmc = PreferredDriverStrength.Emmc;
}
@@ -1198,9 +1212,9 @@ EmmcGetTargetBusMode ( OUT SD_MMC_BUS_SETTINGS *BusMode
)
{
- BusMode->BusTiming = EmmcGetTargetBusTiming (Private, SlotIndex, ExtCsd);
- BusMode->BusWidth = EmmcGetTargetBusWidth (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
- BusMode->ClockFreq = EmmcGetTargetClockFreq (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
+ BusMode->BusTiming = EmmcGetTargetBusTiming (Private, SlotIndex, ExtCsd);
+ BusMode->BusWidth = EmmcGetTargetBusWidth (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
+ BusMode->ClockFreq = EmmcGetTargetClockFreq (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
BusMode->DriverStrength = EmmcGetTargetDriverStrength (Private, SlotIndex, ExtCsd, BusMode->BusTiming);
}
@@ -1221,17 +1235,17 @@ EmmcGetTargetBusMode ( **/
EFI_STATUS
EmmcSetBusMode (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca
)
{
- EFI_STATUS Status;
- EMMC_CSD Csd;
- EMMC_EXT_CSD ExtCsd;
- SD_MMC_BUS_SETTINGS BusMode;
- SD_MMC_HC_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
+ EMMC_CSD Csd;
+ EMMC_EXT_CSD ExtCsd;
+ SD_MMC_BUS_SETTINGS BusMode;
+ SD_MMC_HC_PRIVATE_DATA *Private;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -1260,8 +1274,14 @@ EmmcSetBusMode ( EmmcGetTargetBusMode (Private, Slot, &ExtCsd, &BusMode);
- DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Target bus mode: timing = %d, width = %d, clock freq = %d, driver strength = %d\n",
- BusMode.BusTiming, BusMode.BusWidth, BusMode.ClockFreq, BusMode.DriverStrength.Emmc));
+ DEBUG ((
+ DEBUG_INFO,
+ "EmmcSetBusMode: Target bus mode: timing = %d, width = %d, clock freq = %d, driver strength = %d\n",
+ BusMode.BusTiming,
+ BusMode.BusWidth,
+ BusMode.ClockFreq,
+ BusMode.DriverStrength.Emmc
+ ));
if (BusMode.BusTiming == SdMmcMmcHs400) {
Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, &BusMode);
@@ -1296,8 +1316,8 @@ EmmcSetBusMode ( **/
EFI_STATUS
EmmcIdentification (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
)
{
EFI_STATUS Status;
@@ -1324,13 +1344,15 @@ EmmcIdentification ( DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails with %r\n", Status));
return Status;
}
+
Ocr |= BIT30;
if (Retry++ == 100) {
DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails too many times\n"));
return EFI_DEVICE_ERROR;
}
- gBS->Stall(10 * 1000);
+
+ gBS->Stall (10 * 1000);
} while ((Ocr & BIT31) == 0);
Status = EmmcGetAllCid (PassThru, Slot);
@@ -1338,6 +1360,7 @@ EmmcIdentification ( DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd2 fails with %r\n", Status));
return Status;
}
+
//
// Slot starts from 0 and valid RCA starts from 1.
// Here we takes a simple formula to calculate the RCA.
@@ -1350,6 +1373,7 @@ EmmcIdentification ( DEBUG ((DEBUG_ERROR, "EmmcIdentification: Executing Cmd3 fails with %r\n", Status));
return Status;
}
+
//
// Enter Data Tranfer Mode.
//
@@ -1360,4 +1384,3 @@ EmmcIdentification ( return Status;
}
-
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c index b630daab76..662f9f483c 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c @@ -23,14 +23,14 @@ **/
EFI_STATUS
SdCardReset (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -65,16 +65,16 @@ SdCardReset ( **/
EFI_STATUS
SdCardVoltageCheck (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT8 SupplyVoltage,
- IN UINT8 CheckPattern
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT8 SupplyVoltage,
+ IN UINT8 CheckPattern
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -84,9 +84,9 @@ SdCardVoltageCheck ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = SD_SEND_IF_COND;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR7;
+ SdMmcCmdBlk.CommandIndex = SD_SEND_IF_COND;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR7;
SdMmcCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -116,17 +116,17 @@ SdCardVoltageCheck ( **/
EFI_STATUS
SdioSendOpCond (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT32 VoltageWindow,
- IN BOOLEAN S18R
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT32 VoltageWindow,
+ IN BOOLEAN S18R
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
- UINT32 Switch;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+ UINT32 Switch;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -176,16 +176,16 @@ SdCardSendOpCond ( IN BOOLEAN S18R,
IN BOOLEAN Xpc,
IN BOOLEAN Hcs,
- OUT UINT32 *Ocr
+ OUT UINT32 *Ocr
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
- UINT32 Switch;
- UINT32 MaxPower;
- UINT32 HostCapacity;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+ UINT32 Switch;
+ UINT32 MaxPower;
+ UINT32 HostCapacity;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -195,9 +195,9 @@ SdCardSendOpCond ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -241,14 +241,14 @@ SdCardSendOpCond ( **/
EFI_STATUS
SdCardAllSendCid (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -285,13 +285,13 @@ EFI_STATUS SdCardSetRca (
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
- OUT UINT16 *Rca
+ OUT UINT16 *Rca
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -328,15 +328,15 @@ SdCardSetRca ( **/
EFI_STATUS
SdCardSelect (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -351,6 +351,7 @@ SdCardSelect ( if (Rca != 0) {
SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
}
+
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -372,14 +373,14 @@ SdCardSelect ( **/
EFI_STATUS
SdCardVoltageSwitch (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -389,9 +390,9 @@ SdCardVoltageSwitch ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -415,17 +416,17 @@ SdCardVoltageSwitch ( **/
EFI_STATUS
SdCardSetBusWidth (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN UINT8 BusWidth
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN UINT8 BusWidth
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
- UINT8 Value;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+ UINT8 Value;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -435,9 +436,9 @@ SdCardSetBusWidth ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -490,15 +491,15 @@ SdCardSwitch ( IN SD_DRIVER_STRENGTH_TYPE DriverStrength,
IN UINT8 PowerLimit,
IN BOOLEAN Mode,
- OUT UINT8 *SwitchResp
+ OUT UINT8 *SwitchResp
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
- UINT32 ModeValue;
- UINT8 AccessMode;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+ UINT32 ModeValue;
+ UINT8 AccessMode;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -552,7 +553,8 @@ SdCardSwitch ( if ((((AccessMode & 0xF) != 0xF) && ((SwitchResp[16] & 0xF) != AccessMode)) ||
(((CommandSystem & 0xF) != 0xF) && (((SwitchResp[16] >> 4) & 0xF) != CommandSystem)) ||
(((DriverStrength & 0xF) != 0xF) && ((SwitchResp[15] & 0xF) != DriverStrength)) ||
- (((PowerLimit & 0xF) != 0xF) && (((SwitchResp[15] >> 4) & 0xF) != PowerLimit))) {
+ (((PowerLimit & 0xF) != 0xF) && (((SwitchResp[15] >> 4) & 0xF) != PowerLimit)))
+ {
return EFI_DEVICE_ERROR;
}
}
@@ -579,13 +581,13 @@ SdCardSendStatus ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
IN UINT8 Slot,
IN UINT16 Rca,
- OUT UINT32 *DevStatus
+ OUT UINT32 *DevStatus
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -595,9 +597,9 @@ SdCardSendStatus ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = SD_SEND_STATUS;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = SD_SEND_STATUS;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
@@ -625,15 +627,15 @@ SdCardSendStatus ( **/
EFI_STATUS
SdCardSendTuningBlk (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot
)
{
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- EFI_STATUS Status;
- UINT8 TuningBlock[64];
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+ UINT8 TuningBlock[64];
ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
@@ -643,9 +645,9 @@ SdCardSendTuningBlk ( Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
- SdMmcCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
SdMmcCmdBlk.CommandArgument = 0;
Packet.InDataBuffer = TuningBlock;
@@ -675,23 +677,24 @@ SdCardSendTuningBlk ( **/
EFI_STATUS
SdCardTuningClock (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot
)
{
- EFI_STATUS Status;
- UINT8 HostCtrl2;
- UINT8 Retry;
+ EFI_STATUS Status;
+ UINT8 HostCtrl2;
+ UINT8 Retry;
//
// Notify the host that the sampling clock tuning procedure starts.
//
HostCtrl2 = BIT6;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
//
@@ -711,6 +714,7 @@ SdCardTuningClock ( if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
break;
}
+
if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
return EFI_SUCCESS;
}
@@ -720,11 +724,12 @@ SdCardTuningClock ( //
// Abort the tuning procedure and reset the tuning circuit.
//
- HostCtrl2 = (UINT8)~(BIT6 | BIT7);
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ HostCtrl2 = (UINT8) ~(BIT6 | BIT7);
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
+
return EFI_DEVICE_ERROR;
}
@@ -746,15 +751,15 @@ SdCardTuningClock ( **/
EFI_STATUS
SdCardSwitchBusWidth (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN UINT8 BusWidth
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN UINT8 BusWidth
)
{
- EFI_STATUS Status;
- UINT32 DevStatus;
+ EFI_STATUS Status;
+ UINT32 DevStatus;
Status = SdCardSetBusWidth (PassThru, Slot, Rca, BusWidth);
if (EFI_ERROR (Status)) {
@@ -767,6 +772,7 @@ SdCardSwitchBusWidth ( DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: Send status fails with %r\n", Status));
return Status;
}
+
//
// Check the switch operation is really successful or not.
//
@@ -793,14 +799,14 @@ SdCardSwitchBusWidth ( **/
BOOLEAN
SdIsBusTimingSupported (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN UINT8 CardSupportedBusTimings,
- IN BOOLEAN IsInUhsI,
- IN SD_MMC_BUS_MODE BusTiming
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN UINT8 CardSupportedBusTimings,
+ IN BOOLEAN IsInUhsI,
+ IN SD_MMC_BUS_MODE BusTiming
)
{
- SD_MMC_HC_SLOT_CAP *Capability;
+ SD_MMC_HC_SLOT_CAP *Capability;
Capability = &Private->Capability[SlotIndex];
@@ -810,26 +816,31 @@ SdIsBusTimingSupported ( if ((Capability->Sdr104 != 0) && ((CardSupportedBusTimings & BIT3) != 0)) {
return TRUE;
}
+
break;
case SdMmcUhsDdr50:
if ((Capability->Ddr50 != 0) && ((CardSupportedBusTimings & BIT4) != 0)) {
return TRUE;
}
+
break;
case SdMmcUhsSdr50:
if ((Capability->Sdr50 != 0) && ((CardSupportedBusTimings & BIT2) != 0)) {
return TRUE;
}
+
break;
case SdMmcUhsSdr25:
if ((CardSupportedBusTimings & BIT1) != 0) {
return TRUE;
}
+
break;
case SdMmcUhsSdr12:
if ((CardSupportedBusTimings & BIT0) != 0) {
return TRUE;
}
+
break;
default:
break;
@@ -837,14 +848,16 @@ SdIsBusTimingSupported ( } else {
switch (BusTiming) {
case SdMmcSdHs:
- if ((Capability->HighSpeed != 0) && (CardSupportedBusTimings & BIT1) != 0) {
+ if ((Capability->HighSpeed != 0) && ((CardSupportedBusTimings & BIT1) != 0)) {
return TRUE;
}
+
break;
case SdMmcSdDs:
if ((CardSupportedBusTimings & BIT0) != 0) {
return TRUE;
}
+
break;
default:
break;
@@ -886,6 +899,7 @@ SdGetTargetBusTiming ( if (SdIsBusTimingSupported (Private, SlotIndex, CardSupportedBusTimings, IsInUhsI, BusTiming)) {
break;
}
+
BusTiming--;
}
@@ -903,9 +917,9 @@ SdGetTargetBusTiming ( **/
UINT8
SdGetTargetBusWidth (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN SD_MMC_BUS_MODE BusTiming
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN SD_MMC_BUS_MODE BusTiming
)
{
UINT8 BusWidth;
@@ -913,9 +927,10 @@ SdGetTargetBusWidth ( PreferredBusWidth = Private->Slot[SlotIndex].OperatingParameters.BusWidth;
- if (BusTiming == SdMmcSdDs || BusTiming == SdMmcSdHs) {
- if (PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE &&
- (PreferredBusWidth == 1 || PreferredBusWidth == 4)) {
+ if ((BusTiming == SdMmcSdDs) || (BusTiming == SdMmcSdHs)) {
+ if ((PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE) &&
+ ((PreferredBusWidth == 1) || (PreferredBusWidth == 4)))
+ {
BusWidth = PreferredBusWidth;
} else {
BusWidth = 4;
@@ -943,13 +958,13 @@ SdGetTargetBusWidth ( **/
UINT32
SdGetTargetBusClockFreq (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN SD_MMC_BUS_MODE BusTiming
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN SD_MMC_BUS_MODE BusTiming
)
{
- UINT32 PreferredClockFreq;
- UINT32 MaxClockFreq;
+ UINT32 PreferredClockFreq;
+ UINT32 MaxClockFreq;
PreferredClockFreq = Private->Slot[SlotIndex].OperatingParameters.ClockFreq;
@@ -971,7 +986,7 @@ SdGetTargetBusClockFreq ( MaxClockFreq = 25;
}
- if (PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE && PreferredClockFreq < MaxClockFreq) {
+ if ((PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE) && (PreferredClockFreq < MaxClockFreq)) {
return PreferredClockFreq;
} else {
return MaxClockFreq;
@@ -990,32 +1005,33 @@ SdGetTargetBusClockFreq ( **/
EDKII_SD_MMC_DRIVER_STRENGTH
SdGetTargetDriverStrength (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 SlotIndex,
- IN UINT8 CardSupportedDriverStrengths,
- IN SD_MMC_BUS_MODE BusTiming
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 SlotIndex,
+ IN UINT8 CardSupportedDriverStrengths,
+ IN SD_MMC_BUS_MODE BusTiming
)
{
EDKII_SD_MMC_DRIVER_STRENGTH PreferredDriverStrength;
EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
- if (BusTiming == SdMmcSdDs || BusTiming == SdMmcSdHs) {
+ if ((BusTiming == SdMmcSdDs) || (BusTiming == SdMmcSdHs)) {
DriverStrength.Sd = SdDriverStrengthIgnore;
return DriverStrength;
}
PreferredDriverStrength = Private->Slot[SlotIndex].OperatingParameters.DriverStrength;
- DriverStrength.Sd = SdDriverStrengthTypeB;
-
- if (PreferredDriverStrength.Sd != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE &&
- (CardSupportedDriverStrengths & (BIT0 << PreferredDriverStrength.Sd))) {
-
- if ((PreferredDriverStrength.Sd == SdDriverStrengthTypeA &&
- (Private->Capability[SlotIndex].DriverTypeA != 0)) ||
- (PreferredDriverStrength.Sd == SdDriverStrengthTypeC &&
- (Private->Capability[SlotIndex].DriverTypeC != 0)) ||
- (PreferredDriverStrength.Sd == SdDriverStrengthTypeD &&
- (Private->Capability[SlotIndex].DriverTypeD != 0))) {
+ DriverStrength.Sd = SdDriverStrengthTypeB;
+
+ if ((PreferredDriverStrength.Sd != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE) &&
+ (CardSupportedDriverStrengths & (BIT0 << PreferredDriverStrength.Sd)))
+ {
+ if (((PreferredDriverStrength.Sd == SdDriverStrengthTypeA) &&
+ (Private->Capability[SlotIndex].DriverTypeA != 0)) ||
+ ((PreferredDriverStrength.Sd == SdDriverStrengthTypeC) &&
+ (Private->Capability[SlotIndex].DriverTypeC != 0)) ||
+ ((PreferredDriverStrength.Sd == SdDriverStrengthTypeD) &&
+ (Private->Capability[SlotIndex].DriverTypeD != 0)))
+ {
DriverStrength.Sd = PreferredDriverStrength.Sd;
}
}
@@ -1041,9 +1057,9 @@ SdGetTargetBusMode ( OUT SD_MMC_BUS_SETTINGS *BusMode
)
{
- BusMode->BusTiming = SdGetTargetBusTiming (Private, SlotIndex, SwitchQueryResp[13], IsInUhsI);
- BusMode->BusWidth = SdGetTargetBusWidth (Private, SlotIndex, BusMode->BusTiming);
- BusMode->ClockFreq = SdGetTargetBusClockFreq (Private, SlotIndex, BusMode->BusTiming);
+ BusMode->BusTiming = SdGetTargetBusTiming (Private, SlotIndex, SwitchQueryResp[13], IsInUhsI);
+ BusMode->BusWidth = SdGetTargetBusWidth (Private, SlotIndex, BusMode->BusTiming);
+ BusMode->ClockFreq = SdGetTargetBusClockFreq (Private, SlotIndex, BusMode->BusTiming);
BusMode->DriverStrength = SdGetTargetDriverStrength (Private, SlotIndex, SwitchQueryResp[9], BusMode->BusTiming);
}
@@ -1065,19 +1081,19 @@ SdGetTargetBusMode ( **/
EFI_STATUS
SdCardSetBusMode (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN BOOLEAN S18A
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ IN BOOLEAN S18A
)
{
- EFI_STATUS Status;
- SD_MMC_HC_SLOT_CAP *Capability;
- UINT8 HostCtrl1;
- UINT8 SwitchResp[64];
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_MMC_BUS_SETTINGS BusMode;
+ EFI_STATUS Status;
+ SD_MMC_HC_SLOT_CAP *Capability;
+ UINT8 HostCtrl1;
+ UINT8 SwitchResp[64];
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ SD_MMC_BUS_SETTINGS BusMode;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -1109,8 +1125,14 @@ SdCardSetBusMode ( SdGetTargetBusMode (Private, Slot, SwitchResp, S18A, &BusMode);
- DEBUG ((DEBUG_INFO, "SdCardSetBusMode: Target bus mode: bus timing = %d, bus width = %d, clock freq[MHz] = %d, driver strength = %d\n",
- BusMode.BusTiming, BusMode.BusWidth, BusMode.ClockFreq, BusMode.DriverStrength.Sd));
+ DEBUG ((
+ DEBUG_INFO,
+ "SdCardSetBusMode: Target bus mode: bus timing = %d, bus width = %d, clock freq[MHz] = %d, driver strength = %d\n",
+ BusMode.BusTiming,
+ BusMode.BusWidth,
+ BusMode.ClockFreq,
+ BusMode.DriverStrength.Sd
+ ));
if (!S18A) {
Status = SdCardSwitchBusWidth (PciIo, PassThru, Slot, Rca, BusMode.BusWidth);
@@ -1134,7 +1156,7 @@ SdCardSetBusMode ( //
if (BusMode.BusTiming == SdMmcSdHs) {
HostCtrl1 = BIT2;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1174,8 +1196,8 @@ SdCardSetBusMode ( **/
EFI_STATUS
SdCardIdentification (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
)
{
EFI_STATUS Status;
@@ -1202,6 +1224,7 @@ SdCardIdentification ( DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd0 fails with %r\n", Status));
return Status;
}
+
//
// 2. Send Cmd8 to the device
//
@@ -1210,6 +1233,7 @@ SdCardIdentification ( DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd8 fails with %r\n", Status));
return Status;
}
+
//
// 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.
//
@@ -1218,6 +1242,7 @@ SdCardIdentification ( DEBUG ((DEBUG_INFO, "SdCardIdentification: Found SDIO device, ignore it as we don't support\n"));
return EFI_DEVICE_ERROR;
}
+
//
// 4. Send Acmd41 with voltage window 0 to the device
//
@@ -1259,7 +1284,8 @@ SdCardIdentification ( }
if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&
- ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {
+ ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420))
+ {
S18r = TRUE;
} else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) {
S18r = FALSE;
@@ -1267,6 +1293,7 @@ SdCardIdentification ( ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
+
//
// 5. Repeatly send Acmd41 with supply voltage window to the device.
// Note here we only support the cards complied with SD physical
@@ -1285,7 +1312,8 @@ SdCardIdentification ( DEBUG ((DEBUG_ERROR, "SdCardIdentification: SdCardSendOpCond fails too many times\n"));
return EFI_DEVICE_ERROR;
}
- gBS->Stall(10 * 1000);
+
+ gBS->Stall (10 * 1000);
} while ((Ocr & BIT31) == 0);
//
@@ -1293,10 +1321,11 @@ SdCardIdentification ( // (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the
// Capabilities register), switch its voltage to 1.8V.
//
- if ((Private->Capability[Slot].Sdr50 != 0 ||
- Private->Capability[Slot].Sdr104 != 0 ||
- Private->Capability[Slot].Ddr50 != 0) &&
- ((Ocr & BIT24) != 0)) {
+ if (((Private->Capability[Slot].Sdr50 != 0) ||
+ (Private->Capability[Slot].Sdr104 != 0) ||
+ (Private->Capability[Slot].Ddr50 != 0)) &&
+ ((Ocr & BIT24) != 0))
+ {
Status = SdCardVoltageSwitch (PassThru, Slot);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardVoltageSwitch fails with %r\n", Status));
@@ -1315,7 +1344,8 @@ SdCardIdentification ( Status = EFI_DEVICE_ERROR;
goto Error;
}
- HostCtrl2 = BIT3;
+
+ HostCtrl2 = BIT3;
SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
gBS->Stall (5000);
@@ -1341,6 +1371,7 @@ SdCardIdentification ( goto Error;
}
}
+
DEBUG ((DEBUG_INFO, "SdCardIdentification: Switch to 1.8v signal voltage success\n"));
}
@@ -1355,6 +1386,7 @@ SdCardIdentification ( DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardSetRca fails with %r\n", Status));
return Status;
}
+
//
// Enter Data Tranfer Mode.
//
@@ -1369,8 +1401,7 @@ Error: //
// Set SD Bus Power = 0
//
- PowerCtrl = (UINT8)~BIT0;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
+ PowerCtrl = (UINT8) ~BIT0;
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
return EFI_DEVICE_ERROR;
}
-
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index 57f4cf329a..ab2becdd19 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -14,12 +14,12 @@ #include "SdMmcPciHcDxe.h"
-EDKII_SD_MMC_OVERRIDE *mOverride;
+EDKII_SD_MMC_OVERRIDE *mOverride;
//
// Driver Global Variables
//
-EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
+EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
SdMmcPciHcDriverBindingSupported,
SdMmcPciHcDriverBindingStart,
SdMmcPciHcDriverBindingStop,
@@ -28,7 +28,7 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = { NULL
};
-#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0, \
+#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0,\
{EDKII_SD_MMC_BUS_WIDTH_IGNORE,\
EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\
{EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}}
@@ -36,7 +36,7 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = { //
// Template for SD/MMC host controller private data.
//
-SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
+SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
SD_MMC_HC_PRIVATE_SIGNATURE, // Signature
NULL, // ControllerHandle
NULL, // PciIo
@@ -63,7 +63,7 @@ SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = { SLOT_INIT_TEMPLATE
},
{ // Capability
- {0},
+ { 0 },
},
{ // MaxCurrent
0,
@@ -73,25 +73,25 @@ SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = { }
};
-SD_DEVICE_PATH mSdDpTemplate = {
+SD_DEVICE_PATH mSdDpTemplate = {
{
MESSAGING_DEVICE_PATH,
MSG_SD_DP,
{
- (UINT8) (sizeof (SD_DEVICE_PATH)),
- (UINT8) ((sizeof (SD_DEVICE_PATH)) >> 8)
+ (UINT8)(sizeof (SD_DEVICE_PATH)),
+ (UINT8)((sizeof (SD_DEVICE_PATH)) >> 8)
}
},
0
};
-EMMC_DEVICE_PATH mEmmcDpTemplate = {
+EMMC_DEVICE_PATH mEmmcDpTemplate = {
{
MESSAGING_DEVICE_PATH,
MSG_EMMC_DP,
{
- (UINT8) (sizeof (EMMC_DEVICE_PATH)),
- (UINT8) ((sizeof (EMMC_DEVICE_PATH)) >> 8)
+ (UINT8)(sizeof (EMMC_DEVICE_PATH)),
+ (UINT8)((sizeof (EMMC_DEVICE_PATH)) >> 8)
}
},
0
@@ -101,7 +101,7 @@ EMMC_DEVICE_PATH mEmmcDpTemplate = { // Prioritized function list to detect card type.
// User could add other card detection logic here.
//
-CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = {
+CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = {
EmmcIdentification,
SdCardIdentification,
NULL
@@ -124,7 +124,7 @@ InitializeSdMmcPciHcDxe ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EfiLibInstallDriverBindingComponentName2 (
ImageHandle,
@@ -150,19 +150,19 @@ InitializeSdMmcPciHcDxe ( VOID
EFIAPI
ProcessAsyncTaskList (
- IN EFI_EVENT Event,
- IN VOID* Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- SD_MMC_HC_PRIVATE_DATA *Private;
- LIST_ENTRY *Link;
- SD_MMC_HC_TRB *Trb;
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- BOOLEAN InfiniteWait;
- EFI_EVENT TrbEvent;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ LIST_ENTRY *Link;
+ SD_MMC_HC_TRB *Trb;
+ EFI_STATUS Status;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ BOOLEAN InfiniteWait;
+ EFI_EVENT TrbEvent;
- Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
+ Private = (SD_MMC_HC_PRIVATE_DATA *)Context;
//
// Check if the first entry in the async I/O queue is done or not.
@@ -176,6 +176,7 @@ ProcessAsyncTaskList ( Status = EFI_NO_MEDIA;
goto Done;
}
+
if (!Trb->Started) {
//
// Check whether the cmd/data line is ready for transfer.
@@ -183,7 +184,7 @@ ProcessAsyncTaskList ( Status = SdMmcCheckTrbEnv (Private, Trb);
if (!EFI_ERROR (Status)) {
Trb->Started = TRUE;
- Status = SdMmcExecTrb (Private, Trb);
+ Status = SdMmcExecTrb (Private, Trb);
if (EFI_ERROR (Status)) {
goto Done;
}
@@ -191,6 +192,7 @@ ProcessAsyncTaskList ( goto Done;
}
}
+
Status = SdMmcCheckTrbResult (Private, Trb);
}
@@ -202,10 +204,11 @@ Done: } else {
InfiniteWait = FALSE;
}
+
if ((!InfiniteWait) && (Trb->Timeout-- == 0)) {
RemoveEntryList (Link);
Trb->Packet->TransactionStatus = EFI_TIMEOUT;
- TrbEvent = Trb->Event;
+ TrbEvent = Trb->Event;
SdMmcFreeTrb (Trb);
DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p EFI_TIMEOUT\n", TrbEvent));
gBS->SignalEvent (TrbEvent);
@@ -217,11 +220,12 @@ Done: } else if ((Trb != NULL)) {
RemoveEntryList (Link);
Trb->Packet->TransactionStatus = Status;
- TrbEvent = Trb->Event;
+ TrbEvent = Trb->Event;
SdMmcFreeTrb (Trb);
DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p with %r\n", TrbEvent, Status));
gBS->SignalEvent (TrbEvent);
}
+
return;
}
@@ -236,23 +240,23 @@ Done: VOID
EFIAPI
SdMmcPciHcEnumerateDevice (
- IN EFI_EVENT Event,
- IN VOID* Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- SD_MMC_HC_PRIVATE_DATA *Private;
- EFI_STATUS Status;
- UINT8 Slot;
- BOOLEAN MediaPresent;
- UINT32 RoutineNum;
- CARD_TYPE_DETECT_ROUTINE *Routine;
- UINTN Index;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
-
- Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
+ UINT8 Slot;
+ BOOLEAN MediaPresent;
+ UINT32 RoutineNum;
+ CARD_TYPE_DETECT_ROUTINE *Routine;
+ UINTN Index;
+ LIST_ENTRY *Link;
+ LIST_ENTRY *NextLink;
+ SD_MMC_HC_TRB *Trb;
+ EFI_TPL OldTpl;
+
+ Private = (SD_MMC_HC_PRIVATE_DATA *)Context;
for (Slot = 0; Slot < SD_MMC_HC_MAX_SLOT; Slot++) {
if ((Private->Slot[Slot].Enable) && (Private->Slot[Slot].SlotType == RemovableSlot)) {
@@ -267,9 +271,10 @@ SdMmcPciHcEnumerateDevice ( OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);
- Link = NextLink) {
+ Link = NextLink)
+ {
NextLink = GetNextNode (&Private->Queue, Link);
- Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
+ Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
if (Trb->Slot == Slot) {
RemoveEntryList (Link);
Trb->Packet->TransactionStatus = EFI_NO_MEDIA;
@@ -277,17 +282,19 @@ SdMmcPciHcEnumerateDevice ( SdMmcFreeTrb (Trb);
}
}
+
gBS->RestoreTPL (OldTpl);
//
// Notify the upper layer the connect state change through ReinstallProtocolInterface.
//
gBS->ReinstallProtocolInterface (
- Private->ControllerHandle,
- &gEfiSdMmcPassThruProtocolGuid,
- &Private->PassThru,
- &Private->PassThru
- );
+ Private->ControllerHandle,
+ &gEfiSdMmcPassThruProtocolGuid,
+ &Private->PassThru,
+ &Private->PassThru
+ );
}
+
if ((Status == EFI_MEDIA_CHANGED) && MediaPresent) {
DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device connected at slot %d of pci %p\n", Slot, Private->PciIo));
//
@@ -297,6 +304,7 @@ SdMmcPciHcEnumerateDevice ( if (EFI_ERROR (Status)) {
continue;
}
+
//
// Reinitialize slot and restart identification process for the new attached device
//
@@ -307,16 +315,17 @@ SdMmcPciHcEnumerateDevice ( Private->Slot[Slot].MediaPresent = TRUE;
Private->Slot[Slot].Initialized = TRUE;
- RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
+ RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
for (Index = 0; Index < RoutineNum; Index++) {
Routine = &mCardTypeDetectRoutineTable[Index];
if (*Routine != NULL) {
- Status = (*Routine) (Private, Slot);
+ Status = (*Routine)(Private, Slot);
if (!EFI_ERROR (Status)) {
break;
}
}
}
+
//
// This card doesn't get initialized correctly.
//
@@ -385,9 +394,9 @@ SdMmcPciHcEnumerateDevice ( EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
@@ -405,7 +414,7 @@ SdMmcPciHcDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID *) &ParentDevicePath,
+ (VOID *)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -416,15 +425,16 @@ SdMmcPciHcDriverBindingSupported ( //
return Status;
}
+
//
// Close the protocol because we don't use it here.
//
gBS->CloseProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
//
// Now test the EfiPciIoProtocol.
@@ -432,7 +442,7 @@ SdMmcPciHcDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -455,30 +465,32 @@ SdMmcPciHcDriverBindingSupported ( );
if (EFI_ERROR (Status)) {
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
return EFI_UNSUPPORTED;
}
+
//
// Since we already got the PciData, we can close protocol to avoid to carry it
// on for multiple exit points.
//
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
//
// Examine SD PCI Host Controller PCI Configuration table fields.
//
if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
(PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&
- ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {
+ ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01)))
+ {
return EFI_SUCCESS;
}
@@ -523,24 +535,24 @@ SdMmcPciHcDriverBindingSupported ( EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Supports;
- UINT64 PciAttributes;
- UINT8 SlotNum;
- UINT8 FirstBar;
- UINT8 Slot;
- UINT8 Index;
- CARD_TYPE_DETECT_ROUTINE *Routine;
- UINT32 RoutineNum;
- BOOLEAN MediaPresent;
- BOOLEAN Support64BitDma;
+ EFI_STATUS Status;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Supports;
+ UINT64 PciAttributes;
+ UINT8 SlotNum;
+ UINT8 FirstBar;
+ UINT8 Slot;
+ UINT8 Index;
+ CARD_TYPE_DETECT_ROUTINE *Routine;
+ UINT32 RoutineNum;
+ BOOLEAN MediaPresent;
+ BOOLEAN Support64BitDma;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@@ -552,7 +564,7 @@ SdMmcPciHcDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -620,11 +632,17 @@ SdMmcPciHcDriverBindingStart ( // implementations.
//
if (mOverride == NULL) {
- Status = gBS->LocateProtocol (&gEdkiiSdMmcOverrideProtocolGuid, NULL,
- (VOID **)&mOverride);
+ Status = gBS->LocateProtocol (
+ &gEdkiiSdMmcOverrideProtocolGuid,
+ NULL,
+ (VOID **)&mOverride
+ );
if (!EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "%a: found SD/MMC override protocol\n",
- __FUNCTION__));
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: found SD/MMC override protocol\n",
+ __FUNCTION__
+ ));
}
}
@@ -655,8 +673,12 @@ SdMmcPciHcDriverBindingStart ( &Private->BaseClkFreq[Slot]
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",
- __FUNCTION__, Status));
+ DEBUG ((
+ DEBUG_WARN,
+ "%a: Failed to override capability - %r\n",
+ __FUNCTION__,
+ Status
+ ));
continue;
}
}
@@ -666,7 +688,7 @@ SdMmcPciHcDriverBindingStart ( Controller,
Slot,
EdkiiSdMmcGetOperatingParam,
- (VOID*)&Private->Slot[Slot].OperatingParameters
+ (VOID *)&Private->Slot[Slot].OperatingParameters
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: Failed to get operating parameters, using defaults\n", __FUNCTION__));
@@ -686,12 +708,13 @@ SdMmcPciHcDriverBindingStart ( // If any of the slots does not support 64b system bus
// do not enable 64b DMA in the PCI layer.
//
- if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300 &&
- Private->Capability[Slot].SysBus64V3 == 0) ||
- (Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400 &&
- Private->Capability[Slot].SysBus64V3 == 0) ||
- (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410 &&
- Private->Capability[Slot].SysBus64V4 == 0)) {
+ if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
+ (Private->Capability[Slot].SysBus64V3 == 0)) ||
+ ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
+ (Private->Capability[Slot].SysBus64V3 == 0)) ||
+ ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
+ (Private->Capability[Slot].SysBus64V4 == 0)))
+ {
Support64BitDma = FALSE;
}
@@ -713,6 +736,7 @@ SdMmcPciHcDriverBindingStart ( if (EFI_ERROR (Status)) {
continue;
}
+
//
// Check whether there is a SD/MMC card attached
//
@@ -737,16 +761,17 @@ SdMmcPciHcDriverBindingStart ( Private->Slot[Slot].MediaPresent = TRUE;
Private->Slot[Slot].Initialized = TRUE;
- RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
+ RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
for (Index = 0; Index < RoutineNum; Index++) {
Routine = &mCardTypeDetectRoutineTable[Index];
if (*Routine != NULL) {
- Status = (*Routine) (Private, Slot);
+ Status = (*Routine)(Private, Slot);
if (!EFI_ERROR (Status)) {
break;
}
}
}
+
//
// This card doesn't get initialized correctly.
//
@@ -831,12 +856,13 @@ Done: NULL
);
}
+
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
if ((Private != NULL) && (Private->TimerEvent != NULL)) {
gBS->CloseEvent (Private->TimerEvent);
@@ -883,26 +909,26 @@ Done: EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru;
- SD_MMC_HC_PRIVATE_DATA *Private;
- EFI_PCI_IO_PROTOCOL *PciIo;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- SD_MMC_HC_TRB *Trb;
+ EFI_STATUS Status;
+ EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ LIST_ENTRY *Link;
+ LIST_ENTRY *NextLink;
+ SD_MMC_HC_TRB *Trb;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: Start\n"));
Status = gBS->OpenProtocol (
Controller,
&gEfiSdMmcPassThruProtocolGuid,
- (VOID**) &PassThru,
+ (VOID **)&PassThru,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -919,20 +945,23 @@ SdMmcPciHcDriverBindingStop ( gBS->CloseEvent (Private->TimerEvent);
Private->TimerEvent = NULL;
}
+
if (Private->ConnectEvent != NULL) {
gBS->CloseEvent (Private->ConnectEvent);
Private->ConnectEvent = NULL;
}
+
//
// As the timer is closed, there is no needs to use TPL lock to
// protect the critical region "queue".
//
for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);
- Link = NextLink) {
+ Link = NextLink)
+ {
NextLink = GetNextNode (&Private->Queue, Link);
RemoveEntryList (Link);
- Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
+ Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
Trb->Packet->TransactionStatus = EFI_ABORTED;
gBS->SignalEvent (Trb->Event);
SdMmcFreeTrb (Trb);
@@ -1003,6 +1032,7 @@ SdMmcPassThruExecSyncTrb ( gBS->RestoreTPL (OldTpl);
break;
}
+
gBS->RestoreTPL (OldTpl);
}
@@ -1068,15 +1098,15 @@ SdMmcPassThruExecSyncTrb ( EFI_STATUS
EFIAPI
SdMmcPassThruPassThru (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN EFI_EVENT Event OPTIONAL
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN UINT8 Slot,
+ IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
)
{
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_MMC_HC_TRB *Trb;
+ EFI_STATUS Status;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ SD_MMC_HC_TRB *Trb;
if ((This == NULL) || (Packet == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1112,6 +1142,7 @@ SdMmcPassThruPassThru ( if (Trb == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// Immediately return for async I/O.
//
@@ -1158,12 +1189,12 @@ SdMmcPassThruPassThru ( EFI_STATUS
EFIAPI
SdMmcPassThruGetNextSlot (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN OUT UINT8 *Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT8 *Slot
)
{
- SD_MMC_HC_PRIVATE_DATA *Private;
- UINT8 Index;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ UINT8 Index;
if ((This == NULL) || (Slot == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1174,20 +1205,22 @@ SdMmcPassThruGetNextSlot ( if (*Slot == 0xFF) {
for (Index = 0; Index < SD_MMC_HC_MAX_SLOT; Index++) {
if (Private->Slot[Index].Enable) {
- *Slot = Index;
+ *Slot = Index;
Private->PreviousSlot = Index;
return EFI_SUCCESS;
}
}
+
return EFI_NOT_FOUND;
} else if (*Slot == Private->PreviousSlot) {
for (Index = *Slot + 1; Index < SD_MMC_HC_MAX_SLOT; Index++) {
if (Private->Slot[Index].Enable) {
- *Slot = Index;
+ *Slot = Index;
Private->PreviousSlot = Index;
return EFI_SUCCESS;
}
}
+
return EFI_NOT_FOUND;
} else {
return EFI_INVALID_PARAMETER;
@@ -1231,14 +1264,14 @@ SdMmcPassThruGetNextSlot ( EFI_STATUS
EFIAPI
SdMmcPassThruBuildDevicePath (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN UINT8 Slot,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_DEVICE_PATH *SdNode;
- EMMC_DEVICE_PATH *EmmcNode;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ SD_DEVICE_PATH *SdNode;
+ EMMC_DEVICE_PATH *EmmcNode;
if ((This == NULL) || (DevicePath == NULL) || (Slot >= SD_MMC_HC_MAX_SLOT)) {
return EFI_INVALID_PARAMETER;
@@ -1255,17 +1288,19 @@ SdMmcPassThruBuildDevicePath ( if (SdNode == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
SdNode->SlotNumber = Slot;
- *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) SdNode;
+ *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)SdNode;
} else if (Private->Slot[Slot].CardType == EmmcCardType) {
EmmcNode = AllocateCopyPool (sizeof (EMMC_DEVICE_PATH), &mEmmcDpTemplate);
if (EmmcNode == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
EmmcNode->SlotNumber = Slot;
- *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) EmmcNode;
+ *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)EmmcNode;
} else {
//
// Currently we only support SD and EMMC two device nodes.
@@ -1300,15 +1335,15 @@ SdMmcPassThruBuildDevicePath ( EFI_STATUS
EFIAPI
SdMmcPassThruGetSlotNumber (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINT8 *Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT8 *Slot
)
{
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_DEVICE_PATH *SdNode;
- EMMC_DEVICE_PATH *EmmcNode;
- UINT8 SlotNumber;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ SD_DEVICE_PATH *SdNode;
+ EMMC_DEVICE_PATH *EmmcNode;
+ UINT8 SlotNumber;
if ((This == NULL) || (DevicePath == NULL) || (Slot == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1322,16 +1357,17 @@ SdMmcPassThruGetSlotNumber ( if ((DevicePath->Type != MESSAGING_DEVICE_PATH) ||
((DevicePath->SubType != MSG_SD_DP) &&
(DevicePath->SubType != MSG_EMMC_DP)) ||
- (DevicePathNodeLength(DevicePath) != sizeof(SD_DEVICE_PATH)) ||
- (DevicePathNodeLength(DevicePath) != sizeof(EMMC_DEVICE_PATH))) {
+ (DevicePathNodeLength (DevicePath) != sizeof (SD_DEVICE_PATH)) ||
+ (DevicePathNodeLength (DevicePath) != sizeof (EMMC_DEVICE_PATH)))
+ {
return EFI_UNSUPPORTED;
}
if (DevicePath->SubType == MSG_SD_DP) {
- SdNode = (SD_DEVICE_PATH *) DevicePath;
+ SdNode = (SD_DEVICE_PATH *)DevicePath;
SlotNumber = SdNode->SlotNumber;
} else {
- EmmcNode = (EMMC_DEVICE_PATH *) DevicePath;
+ EmmcNode = (EMMC_DEVICE_PATH *)DevicePath;
SlotNumber = EmmcNode->SlotNumber;
}
@@ -1373,15 +1409,15 @@ SdMmcPassThruGetSlotNumber ( EFI_STATUS
EFIAPI
SdMmcPassThruResetDevice (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN UINT8 Slot
)
{
- SD_MMC_HC_PRIVATE_DATA *Private;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+ LIST_ENTRY *Link;
+ LIST_ENTRY *NextLink;
+ SD_MMC_HC_TRB *Trb;
+ EFI_TPL OldTpl;
if (This == NULL) {
return EFI_INVALID_PARAMETER;
@@ -1400,6 +1436,7 @@ SdMmcPassThruResetDevice ( if (!Private->Slot[Slot].Initialized) {
return EFI_DEVICE_ERROR;
}
+
//
// Free all async I/O requests in the queue
//
@@ -1407,10 +1444,11 @@ SdMmcPassThruResetDevice ( for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);
- Link = NextLink) {
+ Link = NextLink)
+ {
NextLink = GetNextNode (&Private->Queue, Link);
RemoveEntryList (Link);
- Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
+ Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
Trb->Packet->TransactionStatus = EFI_ABORTED;
gBS->SignalEvent (Trb->Event);
SdMmcFreeTrb (Trb);
@@ -1420,4 +1458,3 @@ SdMmcPassThruResetDevice ( return EFI_SUCCESS;
}
-
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index fb69aa4baf..85e09cf114 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -35,11 +35,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "SdMmcPciHci.h"
-extern EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2;
-extern EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding;
-extern EDKII_SD_MMC_OVERRIDE *mOverride;
+extern EDKII_SD_MMC_OVERRIDE *mOverride;
#define SD_MMC_HC_PRIVATE_SIGNATURE SIGNATURE_32 ('s', 'd', 't', 'f')
@@ -49,18 +49,18 @@ extern EDKII_SD_MMC_OVERRIDE *mOverride; //
// Generic time out value, 1 microsecond as unit.
//
-#define SD_MMC_HC_GENERIC_TIMEOUT 1 * 1000 * 1000
+#define SD_MMC_HC_GENERIC_TIMEOUT 1 * 1000 * 1000
//
// SD/MMC async transfer timer interval, set by experience.
// The unit is 100us, takes 1ms as interval.
//
-#define SD_MMC_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS(1)
+#define SD_MMC_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// SD/MMC removable device enumeration timer interval, set by experience.
// The unit is 100us, takes 100ms as interval.
//
-#define SD_MMC_HC_ENUM_TIMER EFI_TIMER_PERIOD_MILLISECONDS(100)
+#define SD_MMC_HC_ENUM_TIMER EFI_TIMER_PERIOD_MILLISECONDS(100)
typedef enum {
UnknownCardType,
@@ -78,97 +78,97 @@ typedef enum { } EFI_SD_MMC_SLOT_TYPE;
typedef struct {
- BOOLEAN Enable;
- EFI_SD_MMC_SLOT_TYPE SlotType;
- BOOLEAN MediaPresent;
- BOOLEAN Initialized;
- SD_MMC_CARD_TYPE CardType;
- UINT64 CurrentFreq;
- EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters;
+ BOOLEAN Enable;
+ EFI_SD_MMC_SLOT_TYPE SlotType;
+ BOOLEAN MediaPresent;
+ BOOLEAN Initialized;
+ SD_MMC_CARD_TYPE CardType;
+ UINT64 CurrentFreq;
+ EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters;
} SD_MMC_HC_SLOT;
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_HANDLE ControllerHandle;
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_HANDLE ControllerHandle;
+ EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_SD_MMC_PASS_THRU_PROTOCOL PassThru;
+ EFI_SD_MMC_PASS_THRU_PROTOCOL PassThru;
- UINT64 PciAttributes;
+ UINT64 PciAttributes;
//
// The field is used to record the previous slot in GetNextSlot().
//
- UINT8 PreviousSlot;
+ UINT8 PreviousSlot;
//
// For Non-blocking operation.
//
- EFI_EVENT TimerEvent;
+ EFI_EVENT TimerEvent;
//
// For Sd removable device enumeration.
//
- EFI_EVENT ConnectEvent;
- LIST_ENTRY Queue;
+ EFI_EVENT ConnectEvent;
+ LIST_ENTRY Queue;
- SD_MMC_HC_SLOT Slot[SD_MMC_HC_MAX_SLOT];
- SD_MMC_HC_SLOT_CAP Capability[SD_MMC_HC_MAX_SLOT];
- UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
- UINT16 ControllerVersion[SD_MMC_HC_MAX_SLOT];
+ SD_MMC_HC_SLOT Slot[SD_MMC_HC_MAX_SLOT];
+ SD_MMC_HC_SLOT_CAP Capability[SD_MMC_HC_MAX_SLOT];
+ UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
+ UINT16 ControllerVersion[SD_MMC_HC_MAX_SLOT];
//
// Some controllers may require to override base clock frequency
// value stored in Capabilities Register 1.
//
- UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
+ UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
} SD_MMC_HC_PRIVATE_DATA;
typedef struct {
- SD_MMC_BUS_MODE BusTiming;
- UINT8 BusWidth;
- UINT32 ClockFreq;
- EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
+ SD_MMC_BUS_MODE BusTiming;
+ UINT8 BusWidth;
+ UINT32 ClockFreq;
+ EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
} SD_MMC_BUS_SETTINGS;
-#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
+#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
-#define SD_MMC_TRB_RETRIES 5
+#define SD_MMC_TRB_RETRIES 5
//
// TRB (Transfer Request Block) contains information for the cmd request.
//
typedef struct {
- UINT32 Signature;
- LIST_ENTRY TrbList;
-
- UINT8 Slot;
- UINT16 BlockSize;
-
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- VOID *Data;
- UINT32 DataLen;
- BOOLEAN Read;
- EFI_PHYSICAL_ADDRESS DataPhy;
- VOID *DataMap;
- SD_MMC_HC_TRANSFER_MODE Mode;
- SD_MMC_HC_ADMA_LENGTH_MODE AdmaLengthMode;
-
- EFI_EVENT Event;
- BOOLEAN Started;
- BOOLEAN CommandComplete;
- UINT64 Timeout;
- UINT32 Retries;
-
- BOOLEAN PioModeTransferCompleted;
- UINT32 PioBlockIndex;
-
- SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
- SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc;
- SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc;
- EFI_PHYSICAL_ADDRESS AdmaDescPhy;
- VOID *AdmaMap;
- UINT32 AdmaPages;
-
- SD_MMC_HC_PRIVATE_DATA *Private;
+ UINT32 Signature;
+ LIST_ENTRY TrbList;
+
+ UINT8 Slot;
+ UINT16 BlockSize;
+
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ VOID *Data;
+ UINT32 DataLen;
+ BOOLEAN Read;
+ EFI_PHYSICAL_ADDRESS DataPhy;
+ VOID *DataMap;
+ SD_MMC_HC_TRANSFER_MODE Mode;
+ SD_MMC_HC_ADMA_LENGTH_MODE AdmaLengthMode;
+
+ EFI_EVENT Event;
+ BOOLEAN Started;
+ BOOLEAN CommandComplete;
+ UINT64 Timeout;
+ UINT32 Retries;
+
+ BOOLEAN PioModeTransferCompleted;
+ UINT32 PioBlockIndex;
+
+ SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
+ SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc;
+ SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc;
+ EFI_PHYSICAL_ADDRESS AdmaDescPhy;
+ VOID *AdmaMap;
+ UINT32 AdmaPages;
+
+ SD_MMC_HC_PRIVATE_DATA *Private;
} SD_MMC_HC_TRB;
#define SD_MMC_HC_TRB_FROM_THIS(a) \
@@ -178,22 +178,23 @@ typedef struct { // Task for Non-blocking mode.
//
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
-
- UINT8 Slot;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- BOOLEAN IsStart;
- EFI_EVENT Event;
- UINT64 RetryTimes;
- BOOLEAN InfiniteWait;
- VOID *Map;
- VOID *MapAddress;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+
+ UINT8 Slot;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ BOOLEAN IsStart;
+ EFI_EVENT Event;
+ UINT64 RetryTimes;
+ BOOLEAN InfiniteWait;
+ VOID *Map;
+ VOID *MapAddress;
} SD_MMC_HC_QUEUE;
//
// Prototypes
//
+
/**
Execute card identification procedure.
@@ -207,8 +208,8 @@ typedef struct { typedef
EFI_STATUS
(*CARD_TYPE_DETECT_ROUTINE) (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
);
/**
@@ -251,10 +252,10 @@ EFI_STATUS EFI_STATUS
EFIAPI
SdMmcPassThruPassThru (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN EFI_EVENT Event OPTIONAL
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN UINT8 Slot,
+ IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
);
/**
@@ -289,8 +290,8 @@ SdMmcPassThruPassThru ( EFI_STATUS
EFIAPI
SdMmcPassThruGetNextSlot (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN OUT UINT8 *Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT8 *Slot
);
/**
@@ -330,9 +331,9 @@ SdMmcPassThruGetNextSlot ( EFI_STATUS
EFIAPI
SdMmcPassThruBuildDevicePath (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN UINT8 Slot,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
);
/**
@@ -359,9 +360,9 @@ SdMmcPassThruBuildDevicePath ( EFI_STATUS
EFIAPI
SdMmcPassThruGetSlotNumber (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINT8 *Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT8 *Slot
);
/**
@@ -390,13 +391,14 @@ SdMmcPassThruGetSlotNumber ( EFI_STATUS
EFIAPI
SdMmcPassThruResetDevice (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
+ IN UINT8 Slot
);
//
// Driver model protocol interfaces
//
+
/**
Tests to see if this driver supports a given controller. If a child device is provided,
it further tests to see if this driver supports creating a handle for the specified child device.
@@ -442,9 +444,9 @@ SdMmcPassThruResetDevice ( EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -485,9 +487,9 @@ SdMmcPciHcDriverBindingSupported ( EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -519,15 +521,16 @@ SdMmcPciHcDriverBindingStart ( EFI_STATUS
EFIAPI
SdMmcPciHcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
//
// EFI Component Name Functions
//
+
/**
Retrieves a Unicode string that is the user readable name of the driver.
@@ -570,9 +573,9 @@ SdMmcPciHcDriverBindingStop ( EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetDriverName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN CHAR8 *Language,
- OUT CHAR16 **DriverName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
);
/**
@@ -646,11 +649,11 @@ SdMmcPciHcComponentNameGetDriverName ( EFI_STATUS
EFIAPI
SdMmcPciHcComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
/**
@@ -668,10 +671,10 @@ SdMmcPciHcComponentNameGetControllerName ( **/
SD_MMC_HC_TRB *
SdMmcCreateTrb (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN EFI_EVENT Event
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot,
+ IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event
);
/**
@@ -682,7 +685,7 @@ SdMmcCreateTrb ( **/
VOID
SdMmcFreeTrb (
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_TRB *Trb
);
/**
@@ -698,8 +701,8 @@ SdMmcFreeTrb ( **/
EFI_STATUS
SdMmcCheckTrbEnv (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
);
/**
@@ -715,8 +718,8 @@ SdMmcCheckTrbEnv ( **/
EFI_STATUS
SdMmcWaitTrbEnv (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
);
/**
@@ -731,8 +734,8 @@ SdMmcWaitTrbEnv ( **/
EFI_STATUS
SdMmcExecTrb (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
);
/**
@@ -748,8 +751,8 @@ SdMmcExecTrb ( **/
EFI_STATUS
SdMmcCheckTrbResult (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
);
/**
@@ -764,8 +767,8 @@ SdMmcCheckTrbResult ( **/
EFI_STATUS
SdMmcWaitTrbResult (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
);
/**
@@ -782,8 +785,8 @@ SdMmcWaitTrbResult ( **/
EFI_STATUS
EmmcIdentification (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
);
/**
@@ -800,8 +803,8 @@ EmmcIdentification ( **/
EFI_STATUS
SdCardIdentification (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
);
/**
@@ -840,8 +843,8 @@ SdMmcHcClockSupply ( **/
EFI_STATUS
SdMmcHcReset (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
);
/**
@@ -857,8 +860,8 @@ SdMmcHcReset ( **/
EFI_STATUS
SdMmcHcInitHost (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 6548ef71de..53b63ab52b 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -23,8 +23,8 @@ **/
VOID
DumpCapabilityReg (
- IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP *Capability
+ IN UINT8 Slot,
+ IN SD_MMC_HC_SLOT_CAP *Capability
)
{
//
@@ -55,6 +55,7 @@ DumpCapabilityReg ( } else {
DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
}
+
DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
@@ -67,6 +68,7 @@ DumpCapabilityReg ( } else {
DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
}
+
DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
@@ -88,13 +90,13 @@ DumpCapabilityReg ( EFI_STATUS
EFIAPI
SdMmcHcGetSlotInfo (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- OUT UINT8 *FirstBar,
- OUT UINT8 *SlotNum
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ OUT UINT8 *FirstBar,
+ OUT UINT8 *SlotNum
)
{
- EFI_STATUS Status;
- SD_MMC_HC_SLOT_INFO SlotInfo;
+ EFI_STATUS Status;
+ SD_MMC_HC_SLOT_INFO SlotInfo;
Status = PciIo->Pci.Read (
PciIo,
@@ -139,18 +141,18 @@ SdMmcHcGetSlotInfo ( EFI_STATUS
EFIAPI
SdMmcHcRwMmio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN BOOLEAN Read,
- IN UINT8 Count,
- IN OUT VOID *Data
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN BOOLEAN Read,
+ IN UINT8 Count,
+ IN OUT VOID *Data
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL_WIDTH Width;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL_WIDTH Width;
- if ((PciIo == NULL) || (Data == NULL)) {
+ if ((PciIo == NULL) || (Data == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -179,7 +181,7 @@ SdMmcHcRwMmio ( PciIo,
Width,
BarIndex,
- (UINT64) Offset,
+ (UINT64)Offset,
Count,
Data
);
@@ -188,7 +190,7 @@ SdMmcHcRwMmio ( PciIo,
Width,
BarIndex,
- (UINT64) Offset,
+ (UINT64)Offset,
Count,
Data
);
@@ -221,16 +223,16 @@ SdMmcHcRwMmio ( EFI_STATUS
EFIAPI
SdMmcHcOrMmio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN UINT8 Count,
- IN VOID *OrData
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN UINT8 Count,
+ IN VOID *OrData
)
{
- EFI_STATUS Status;
- UINT64 Data;
- UINT64 Or;
+ EFI_STATUS Status;
+ UINT64 Data;
+ UINT64 Or;
Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
if (EFI_ERROR (Status)) {
@@ -238,13 +240,13 @@ SdMmcHcOrMmio ( }
if (Count == 1) {
- Or = *(UINT8*) OrData;
+ Or = *(UINT8 *)OrData;
} else if (Count == 2) {
- Or = *(UINT16*) OrData;
+ Or = *(UINT16 *)OrData;
} else if (Count == 4) {
- Or = *(UINT32*) OrData;
+ Or = *(UINT32 *)OrData;
} else if (Count == 8) {
- Or = *(UINT64*) OrData;
+ Or = *(UINT64 *)OrData;
} else {
return EFI_INVALID_PARAMETER;
}
@@ -279,16 +281,16 @@ SdMmcHcOrMmio ( EFI_STATUS
EFIAPI
SdMmcHcAndMmio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN UINT8 Count,
- IN VOID *AndData
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN UINT8 Count,
+ IN VOID *AndData
)
{
- EFI_STATUS Status;
- UINT64 Data;
- UINT64 And;
+ EFI_STATUS Status;
+ UINT64 Data;
+ UINT64 And;
Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
if (EFI_ERROR (Status)) {
@@ -296,13 +298,13 @@ SdMmcHcAndMmio ( }
if (Count == 1) {
- And = *(UINT8*) AndData;
+ And = *(UINT8 *)AndData;
} else if (Count == 2) {
- And = *(UINT16*) AndData;
+ And = *(UINT16 *)AndData;
} else if (Count == 4) {
- And = *(UINT32*) AndData;
+ And = *(UINT32 *)AndData;
} else if (Count == 8) {
- And = *(UINT64*) AndData;
+ And = *(UINT64 *)AndData;
} else {
return EFI_INVALID_PARAMETER;
}
@@ -335,16 +337,16 @@ SdMmcHcAndMmio ( EFI_STATUS
EFIAPI
SdMmcHcCheckMmioSet (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN UINT8 Count,
- IN UINT64 MaskValue,
- IN UINT64 TestValue
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN UINT8 Count,
+ IN UINT64 MaskValue,
+ IN UINT64 TestValue
)
{
- EFI_STATUS Status;
- UINT64 Value;
+ EFI_STATUS Status;
+ UINT64 Value;
//
// Access PCI MMIO space to see if the value is the tested one.
@@ -389,17 +391,17 @@ SdMmcHcCheckMmioSet ( EFI_STATUS
EFIAPI
SdMmcHcWaitMmioSet (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN UINT8 Count,
- IN UINT64 MaskValue,
- IN UINT64 TestValue,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN UINT8 Count,
+ IN UINT64 MaskValue,
+ IN UINT64 TestValue,
+ IN UINT64 Timeout
)
{
- EFI_STATUS Status;
- BOOLEAN InfiniteWait;
+ EFI_STATUS Status;
+ BOOLEAN InfiniteWait;
if (Timeout == 0) {
InfiniteWait = TRUE;
@@ -449,7 +451,7 @@ SdMmcHcGetControllerVersion ( OUT UINT16 *Version
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
if (EFI_ERROR (Status)) {
@@ -473,28 +475,32 @@ SdMmcHcGetControllerVersion ( **/
EFI_STATUS
SdMmcHcReset (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
)
{
- EFI_STATUS Status;
- UINT8 SwReset;
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT8 SwReset;
+ EFI_PCI_IO_PROTOCOL *PciIo;
//
// Notify the SD/MMC override protocol that we are about to reset
// the SD/MMC host controller.
//
- if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
EdkiiSdMmcResetPre,
- NULL);
+ NULL
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: SD/MMC pre reset notifier callback failed - %r\n",
- __FUNCTION__, Status));
+ __FUNCTION__,
+ Status
+ ));
return Status;
}
}
@@ -527,8 +533,11 @@ SdMmcHcReset ( //
Status = SdMmcHcEnableInterrupt (PciIo, Slot);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
- Status));
+ DEBUG ((
+ DEBUG_INFO,
+ "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
+ Status
+ ));
return Status;
}
@@ -536,16 +545,20 @@ SdMmcHcReset ( // Notify the SD/MMC override protocol that we have just reset
// the SD/MMC host controller.
//
- if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
EdkiiSdMmcResetPost,
- NULL);
+ NULL
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: SD/MMC post reset notifier callback failed - %r\n",
- __FUNCTION__, Status));
+ __FUNCTION__,
+ Status
+ ));
}
}
@@ -565,26 +578,27 @@ SdMmcHcReset ( **/
EFI_STATUS
SdMmcHcEnableInterrupt (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot
)
{
- EFI_STATUS Status;
- UINT16 IntStatus;
+ EFI_STATUS Status;
+ UINT16 IntStatus;
//
// Enable all bits in Error Interrupt Status Enable Register
//
IntStatus = 0xFFFF;
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Enable all bits in Normal Interrupt Status Enable Register
//
IntStatus = 0xFFFF;
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
return Status;
}
@@ -604,11 +618,11 @@ EFI_STATUS SdMmcHcGetCapability (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
- OUT SD_MMC_HC_SLOT_CAP *Capability
+ OUT SD_MMC_HC_SLOT_CAP *Capability
)
{
- EFI_STATUS Status;
- UINT64 Cap;
+ EFI_STATUS Status;
+ UINT64 Cap;
Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
if (EFI_ERROR (Status)) {
@@ -635,10 +649,10 @@ EFI_STATUS SdMmcHcGetMaxCurrent (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
- OUT UINT64 *MaxCurrent
+ OUT UINT64 *MaxCurrent
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
@@ -662,14 +676,14 @@ SdMmcHcGetMaxCurrent ( **/
EFI_STATUS
SdMmcHcCardDetect (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- OUT BOOLEAN *MediaPresent
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ OUT BOOLEAN *MediaPresent
)
{
- EFI_STATUS Status;
- UINT16 Data;
- UINT32 PresentState;
+ EFI_STATUS Status;
+ UINT16 Data;
+ UINT32 PresentState;
//
// Check Present State Register to see if there is a card presented.
@@ -723,13 +737,13 @@ SdMmcHcCardDetect ( **/
EFI_STATUS
SdMmcHcStopClock (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot
)
{
- EFI_STATUS Status;
- UINT32 PresentState;
- UINT16 ClockCtrl;
+ EFI_STATUS Status;
+ UINT32 PresentState;
+ UINT16 ClockCtrl;
//
// Ensure no SD transactions are occurring on the SD Bus by
@@ -752,8 +766,8 @@ SdMmcHcStopClock ( //
// Set SD Clock Enable in the Clock Control register to 0
//
- ClockCtrl = (UINT16)~BIT2;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
+ ClockCtrl = (UINT16) ~BIT2;
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
return Status;
}
@@ -773,7 +787,7 @@ SdMmcHcStartSdClock ( IN UINT8 Slot
)
{
- UINT16 ClockCtrl;
+ UINT16 ClockCtrl;
//
// Set SD Clock Enable in the Clock Control register to 1
@@ -806,20 +820,20 @@ SdMmcHcClockSupply ( IN UINT64 ClockFreq
)
{
- EFI_STATUS Status;
- UINT32 SettingFreq;
- UINT32 Divisor;
- UINT32 Remainder;
- UINT16 ClockCtrl;
- UINT32 BaseClkFreq;
- UINT16 ControllerVer;
- EFI_PCI_IO_PROTOCOL *PciIo;
-
- PciIo = Private->PciIo;
- BaseClkFreq = Private->BaseClkFreq[Slot];
+ EFI_STATUS Status;
+ UINT32 SettingFreq;
+ UINT32 Divisor;
+ UINT32 Remainder;
+ UINT16 ClockCtrl;
+ UINT32 BaseClkFreq;
+ UINT16 ControllerVer;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+
+ PciIo = Private->PciIo;
+ BaseClkFreq = Private->BaseClkFreq[Slot];
ControllerVer = Private->ControllerVersion[Slot];
- if (BaseClkFreq == 0 || ClockFreq == 0) {
+ if ((BaseClkFreq == 0) || (ClockFreq == 0)) {
return EFI_INVALID_PARAMETER;
}
@@ -840,8 +854,9 @@ SdMmcHcClockSupply ( if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
break;
}
+
if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
- SettingFreq ++;
+ SettingFreq++;
}
}
@@ -851,17 +866,20 @@ SdMmcHcClockSupply ( // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
//
if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
- (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
+ (ControllerVer <= SD_MMC_HC_CTRL_VER_420))
+ {
ASSERT (Divisor <= 0x3FF);
ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
} else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
- (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
+ (ControllerVer == SD_MMC_HC_CTRL_VER_200))
+ {
//
// Only the most significant bit can be used as divisor.
//
if (((Divisor - 1) & Divisor) != 0) {
Divisor = 1 << (HighBitSet32 (Divisor) + 1);
}
+
ASSERT (Divisor <= 0x80);
ClockCtrl = (Divisor & 0xFF) << 8;
} else {
@@ -881,7 +899,7 @@ SdMmcHcClockSupply ( // Supply clock frequency with specified divisor
//
ClockCtrl |= BIT0;
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
return Status;
@@ -913,7 +931,7 @@ SdMmcHcClockSupply ( // legacy behavior. During first time setup we also don't know what type
// of the card slot it is and which enum value of BusTiming applies.
//
- if (!FirstTimeSetup && mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ if (!FirstTimeSetup && (mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
@@ -951,18 +969,18 @@ SdMmcHcClockSupply ( **/
EFI_STATUS
SdMmcHcPowerControl (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN UINT8 PowerCtrl
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN UINT8 PowerCtrl
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Clr SD Bus Power
//
- PowerCtrl &= (UINT8)~BIT0;
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
+ PowerCtrl &= (UINT8) ~BIT0;
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -971,7 +989,7 @@ SdMmcHcPowerControl ( // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
//
PowerCtrl |= BIT0;
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
return Status;
}
@@ -991,33 +1009,35 @@ SdMmcHcPowerControl ( **/
EFI_STATUS
SdMmcHcSetBusWidth (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN UINT16 BusWidth
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN UINT16 BusWidth
)
{
- EFI_STATUS Status;
- UINT8 HostCtrl1;
+ EFI_STATUS Status;
+ UINT8 HostCtrl1;
if (BusWidth == 1) {
- HostCtrl1 = (UINT8)~(BIT5 | BIT1);
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ HostCtrl1 = (UINT8) ~(BIT5 | BIT1);
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
} else if (BusWidth == 4) {
Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
+
HostCtrl1 |= BIT1;
- HostCtrl1 &= (UINT8)~BIT5;
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
+ HostCtrl1 &= (UINT8) ~BIT5;
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
} else if (BusWidth == 8) {
Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
- HostCtrl1 &= (UINT8)~BIT1;
+
+ HostCtrl1 &= (UINT8) ~BIT1;
HostCtrl1 |= BIT5;
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
} else {
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
@@ -1039,14 +1059,14 @@ SdMmcHcSetBusWidth ( **/
EFI_STATUS
SdMmcHcInitV4Enhancements (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP Capability,
- IN UINT16 ControllerVer
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN SD_MMC_HC_SLOT_CAP Capability,
+ IN UINT16 ControllerVer
)
{
- EFI_STATUS Status;
- UINT16 HostCtrl2;
+ EFI_STATUS Status;
+ UINT16 HostCtrl2;
//
// Check if controller version V4 or higher
@@ -1076,9 +1096,11 @@ SdMmcHcInitV4Enhancements ( HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
}
+
HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
}
+
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
@@ -1103,14 +1125,14 @@ SdMmcHcInitV4Enhancements ( **/
EFI_STATUS
SdMmcHcInitPowerVoltage (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP Capability
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN SD_MMC_HC_SLOT_CAP Capability
)
{
- EFI_STATUS Status;
- UINT8 MaxVoltage;
- UINT8 HostCtrl2;
+ EFI_STATUS Status;
+ UINT8 MaxVoltage;
+ UINT8 HostCtrl2;
//
// Calculate supported maximum voltage according to SD Bus Voltage Select
@@ -1131,7 +1153,7 @@ SdMmcHcInitPowerVoltage ( //
MaxVoltage = 0x0A;
HostCtrl2 = BIT3;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
gBS->Stall (5000);
if (EFI_ERROR (Status)) {
return Status;
@@ -1163,12 +1185,12 @@ SdMmcHcInitPowerVoltage ( **/
EFI_STATUS
SdMmcHcInitTimeoutCtrl (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot
)
{
- EFI_STATUS Status;
- UINT8 Timeout;
+ EFI_STATUS Status;
+ UINT8 Timeout;
Timeout = 0x0E;
Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
@@ -1189,33 +1211,37 @@ SdMmcHcInitTimeoutCtrl ( **/
EFI_STATUS
SdMmcHcInitHost (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- SD_MMC_HC_SLOT_CAP Capability;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ SD_MMC_HC_SLOT_CAP Capability;
//
// Notify the SD/MMC override protocol that we are about to initialize
// the SD/MMC host controller.
//
- if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
EdkiiSdMmcInitHostPre,
- NULL);
+ NULL
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: SD/MMC pre init notifier callback failed - %r\n",
- __FUNCTION__, Status));
+ __FUNCTION__,
+ Status
+ ));
return Status;
}
}
- PciIo = Private->PciIo;
+ PciIo = Private->PciIo;
Capability = Private->Capability[Slot];
Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
@@ -1249,18 +1275,23 @@ SdMmcHcInitHost ( // Notify the SD/MMC override protocol that we are have just initialized
// the SD/MMC host controller.
//
- if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
EdkiiSdMmcInitHostPost,
- NULL);
+ NULL
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: SD/MMC post init notifier callback failed - %r\n",
- __FUNCTION__, Status));
+ __FUNCTION__,
+ Status
+ ));
}
}
+
return Status;
}
@@ -1277,17 +1308,17 @@ SdMmcHcInitHost ( **/
EFI_STATUS
SdMmcHcUhsSignaling (
- IN EFI_HANDLE ControllerHandle,
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN SD_MMC_BUS_MODE Timing
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN SD_MMC_BUS_MODE Timing
)
{
- EFI_STATUS Status;
- UINT8 HostCtrl2;
+ EFI_STATUS Status;
+ UINT8 HostCtrl2;
- HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ HostCtrl2 = (UINT8) ~SD_MMC_HC_CTRL_UHS_MASK;
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1324,15 +1355,16 @@ SdMmcHcUhsSignaling ( HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
break;
default:
- HostCtrl2 = 0;
- break;
+ HostCtrl2 = 0;
+ break;
}
+
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
- if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ if ((mOverride != NULL) && (mOverride->NotifyPhase != NULL)) {
Status = mOverride->NotifyPhase (
ControllerHandle,
Slot,
@@ -1377,8 +1409,8 @@ SdMmcSetDriverStrength ( return EFI_SUCCESS;
}
- HostCtrl2 = (UINT16)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
- Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ HostCtrl2 = (UINT16) ~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
+ Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1400,19 +1432,19 @@ SdMmcSetDriverStrength ( **/
EFI_STATUS
SdMmcHcLedOnOff (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN On
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN BOOLEAN On
)
{
- EFI_STATUS Status;
- UINT8 HostCtrl1;
+ EFI_STATUS Status;
+ UINT8 HostCtrl1;
if (On) {
HostCtrl1 = BIT0;
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
} else {
- HostCtrl1 = (UINT8)~BIT0;
+ HostCtrl1 = (UINT8) ~BIT0;
Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
}
@@ -1433,23 +1465,23 @@ SdMmcHcLedOnOff ( **/
EFI_STATUS
BuildAdmaDescTable (
- IN SD_MMC_HC_TRB *Trb,
- IN UINT16 ControllerVer
+ IN SD_MMC_HC_TRB *Trb,
+ IN UINT16 ControllerVer
)
{
- EFI_PHYSICAL_ADDRESS Data;
- UINT64 DataLen;
- UINT64 Entries;
- UINT32 Index;
- UINT64 Remaining;
- UINT64 Address;
- UINTN TableSize;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINTN Bytes;
- UINT32 AdmaMaxDataPerLine;
- UINT32 DescSize;
- VOID *AdmaDesc;
+ EFI_PHYSICAL_ADDRESS Data;
+ UINT64 DataLen;
+ UINT64 Entries;
+ UINT32 Index;
+ UINT64 Remaining;
+ UINT64 Address;
+ UINTN TableSize;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINTN Bytes;
+ UINT32 AdmaMaxDataPerLine;
+ UINT32 DescSize;
+ VOID *AdmaDesc;
AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
@@ -1463,9 +1495,11 @@ BuildAdmaDescTable ( // Check for valid ranges in 32bit ADMA Descriptor Table
//
if ((Trb->Mode == SdMmcAdma32bMode) &&
- ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
+ ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)))
+ {
return EFI_INVALID_PARAMETER;
}
+
//
// Check address field alignment
//
@@ -1490,9 +1524,10 @@ BuildAdmaDescTable ( //
if (Trb->Mode == SdMmcAdma64bV3Mode) {
DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);
- }else if (Trb->Mode == SdMmcAdma64bV4Mode) {
+ } else if (Trb->Mode == SdMmcAdma64bV4Mode) {
DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);
}
+
//
// Configure 26b data length.
//
@@ -1500,20 +1535,21 @@ BuildAdmaDescTable ( AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
}
- Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
- TableSize = (UINTN)MultU64x32 (Entries, DescSize);
+ Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
+ TableSize = (UINTN)MultU64x32 (Entries, DescSize);
Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
- Status = PciIo->AllocateBuffer (
- PciIo,
- AllocateAnyPages,
- EfiBootServicesData,
- EFI_SIZE_TO_PAGES (TableSize),
- (VOID **)&AdmaDesc,
- 0
- );
+ Status = PciIo->AllocateBuffer (
+ PciIo,
+ AllocateAnyPages,
+ EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (TableSize),
+ (VOID **)&AdmaDesc,
+ 0
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
ZeroMem (AdmaDesc, TableSize);
Bytes = TableSize;
Status = PciIo->Map (
@@ -1538,21 +1574,22 @@ BuildAdmaDescTable ( }
if ((Trb->Mode == SdMmcAdma32bMode) &&
- (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
+ ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul))
+ {
//
// The ADMA doesn't support 64bit addressing.
//
PciIo->Unmap (
- PciIo,
- Trb->AdmaMap
- );
+ PciIo,
+ Trb->AdmaMap
+ );
Trb->AdmaMap = NULL;
PciIo->FreeBuffer (
- PciIo,
- EFI_SIZE_TO_PAGES (TableSize),
- AdmaDesc
- );
+ PciIo,
+ EFI_SIZE_TO_PAGES (TableSize),
+ AdmaDesc
+ );
return EFI_DEVICE_ERROR;
}
@@ -1574,25 +1611,28 @@ BuildAdmaDescTable ( if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
}
+
Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
- Trb->Adma32Desc[Index].Address = (UINT32)Address;
+ Trb->Adma32Desc[Index].Address = (UINT32)Address;
break;
} else {
Trb->Adma32Desc[Index].Valid = 1;
Trb->Adma32Desc[Index].Act = 2;
if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
- Trb->Adma32Desc[Index].UpperLength = 0;
+ Trb->Adma32Desc[Index].UpperLength = 0;
}
- Trb->Adma32Desc[Index].LowerLength = 0;
- Trb->Adma32Desc[Index].Address = (UINT32)Address;
+
+ Trb->Adma32Desc[Index].LowerLength = 0;
+ Trb->Adma32Desc[Index].Address = (UINT32)Address;
}
} else if (Trb->Mode == SdMmcAdma64bV3Mode) {
if (Remaining <= AdmaMaxDataPerLine) {
Trb->Adma64V3Desc[Index].Valid = 1;
Trb->Adma64V3Desc[Index].Act = 2;
if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
- Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
+ Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
}
+
Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
@@ -1601,8 +1641,9 @@ BuildAdmaDescTable ( Trb->Adma64V3Desc[Index].Valid = 1;
Trb->Adma64V3Desc[Index].Act = 2;
if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
- Trb->Adma64V3Desc[Index].UpperLength = 0;
+ Trb->Adma64V3Desc[Index].UpperLength = 0;
}
+
Trb->Adma64V3Desc[Index].LowerLength = 0;
Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
@@ -1612,8 +1653,9 @@ BuildAdmaDescTable ( Trb->Adma64V4Desc[Index].Valid = 1;
Trb->Adma64V4Desc[Index].Act = 2;
if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
- Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
+ Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
}
+
Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
@@ -1622,8 +1664,9 @@ BuildAdmaDescTable ( Trb->Adma64V4Desc[Index].Valid = 1;
Trb->Adma64V4Desc[Index].Act = 2;
if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
- Trb->Adma64V4Desc[Index].UpperLength = 0;
+ Trb->Adma64V4Desc[Index].UpperLength = 0;
}
+
Trb->Adma64V4Desc[Index].LowerLength = 0;
Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
@@ -1644,6 +1687,7 @@ BuildAdmaDescTable ( } else {
Trb->Adma64V4Desc[Index].End = 1;
}
+
return EFI_SUCCESS;
}
@@ -1668,14 +1712,18 @@ SdMmcPrintPacket ( DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", Packet->SdMmcCmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument));
DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", Packet->SdMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType));
}
+
if (Packet->SdMmcStatusBlk != NULL) {
- DEBUG ((DebugLevel, "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
- Packet->SdMmcStatusBlk->Resp0,
- Packet->SdMmcStatusBlk->Resp1,
- Packet->SdMmcStatusBlk->Resp2,
- Packet->SdMmcStatusBlk->Resp3
- ));
+ DEBUG ((
+ DebugLevel,
+ "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
+ Packet->SdMmcStatusBlk->Resp0,
+ Packet->SdMmcStatusBlk->Resp1,
+ Packet->SdMmcStatusBlk->Resp2,
+ Packet->SdMmcStatusBlk->Resp3
+ ));
}
+
DEBUG ((DebugLevel, "Timeout: %ld\n", Packet->Timeout));
DEBUG ((DebugLevel, "InDataBuffer: %p\n", Packet->InDataBuffer));
DEBUG ((DebugLevel, "OutDataBuffer: %p\n", Packet->OutDataBuffer));
@@ -1743,10 +1791,10 @@ SdMmcSetupMemoryForDmaTransfer ( IN SD_MMC_HC_TRB *Trb
)
{
- EFI_PCI_IO_PROTOCOL_OPERATION Flag;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINTN MapLength;
- EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL_OPERATION Flag;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN MapLength;
+ EFI_STATUS Status;
if (Trb->Read) {
Flag = EfiPciIoOperationBusMasterWrite;
@@ -1755,24 +1803,25 @@ SdMmcSetupMemoryForDmaTransfer ( }
PciIo = Private->PciIo;
- if (Trb->Data != NULL && Trb->DataLen != 0) {
+ if ((Trb->Data != NULL) && (Trb->DataLen != 0)) {
MapLength = Trb->DataLen;
- Status = PciIo->Map (
- PciIo,
- Flag,
- Trb->Data,
- &MapLength,
- &Trb->DataPhy,
- &Trb->DataMap
- );
+ Status = PciIo->Map (
+ PciIo,
+ Flag,
+ Trb->Data,
+ &MapLength,
+ &Trb->DataPhy,
+ &Trb->DataMap
+ );
if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
return EFI_BAD_BUFFER_SIZE;
}
}
- if (Trb->Mode == SdMmcAdma32bMode ||
- Trb->Mode == SdMmcAdma64bV3Mode ||
- Trb->Mode == SdMmcAdma64bV4Mode) {
+ if ((Trb->Mode == SdMmcAdma32bMode) ||
+ (Trb->Mode == SdMmcAdma64bV3Mode) ||
+ (Trb->Mode == SdMmcAdma64bV4Mode))
+ {
Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
if (EFI_ERROR (Status)) {
return Status;
@@ -1797,33 +1846,33 @@ SdMmcSetupMemoryForDmaTransfer ( **/
SD_MMC_HC_TRB *
SdMmcCreateTrb (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN EFI_EVENT Event
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN UINT8 Slot,
+ IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event
)
{
- SD_MMC_HC_TRB *Trb;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ SD_MMC_HC_TRB *Trb;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
if (Trb == NULL) {
return NULL;
}
- Trb->Signature = SD_MMC_HC_TRB_SIG;
- Trb->Slot = Slot;
- Trb->BlockSize = 0x200;
- Trb->Packet = Packet;
- Trb->Event = Event;
- Trb->Started = FALSE;
- Trb->CommandComplete = FALSE;
- Trb->Timeout = Packet->Timeout;
- Trb->Retries = SD_MMC_TRB_RETRIES;
+ Trb->Signature = SD_MMC_HC_TRB_SIG;
+ Trb->Slot = Slot;
+ Trb->BlockSize = 0x200;
+ Trb->Packet = Packet;
+ Trb->Event = Event;
+ Trb->Started = FALSE;
+ Trb->CommandComplete = FALSE;
+ Trb->Timeout = Packet->Timeout;
+ Trb->Retries = SD_MMC_TRB_RETRIES;
Trb->PioModeTransferCompleted = FALSE;
- Trb->PioBlockIndex = 0;
- Trb->Private = Private;
+ Trb->PioBlockIndex = 0;
+ Trb->Private = Private;
if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
Trb->Data = Packet->InDataBuffer;
@@ -1847,33 +1896,38 @@ SdMmcCreateTrb ( if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
(Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
((Private->Slot[Trb->Slot].CardType == SdCardType) &&
- (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
+ (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK)))
+ {
Trb->Mode = SdMmcPioMode;
} else {
if (Trb->DataLen == 0) {
Trb->Mode = SdMmcNoData;
} else if (Private->Capability[Slot].Adma2 != 0) {
- Trb->Mode = SdMmcAdma32bMode;
+ Trb->Mode = SdMmcAdma32bMode;
Trb->AdmaLengthMode = SdMmcAdmaLen16b;
if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
- (Private->Capability[Slot].SysBus64V3 == 1)) {
+ (Private->Capability[Slot].SysBus64V3 == 1))
+ {
Trb->Mode = SdMmcAdma64bV3Mode;
} else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
(Private->Capability[Slot].SysBus64V3 == 1)) ||
((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
- (Private->Capability[Slot].SysBus64V4 == 1))) {
+ (Private->Capability[Slot].SysBus64V4 == 1)))
+ {
Trb->Mode = SdMmcAdma64bV4Mode;
}
+
if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {
Trb->AdmaLengthMode = SdMmcAdmaLen26b;
}
+
Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
if (EFI_ERROR (Status)) {
goto Error;
}
} else if (Private->Capability[Slot].Sdma != 0) {
Trb->Mode = SdMmcSdmaMode;
- Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
+ Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
if (EFI_ERROR (Status)) {
goto Error;
}
@@ -1903,46 +1957,51 @@ Error: **/
VOID
SdMmcFreeTrb (
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_TRB *Trb
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = Trb->Private->PciIo;
if (Trb->AdmaMap != NULL) {
PciIo->Unmap (
- PciIo,
- Trb->AdmaMap
- );
+ PciIo,
+ Trb->AdmaMap
+ );
}
+
if (Trb->Adma32Desc != NULL) {
PciIo->FreeBuffer (
- PciIo,
- Trb->AdmaPages,
- Trb->Adma32Desc
- );
+ PciIo,
+ Trb->AdmaPages,
+ Trb->Adma32Desc
+ );
}
+
if (Trb->Adma64V3Desc != NULL) {
PciIo->FreeBuffer (
- PciIo,
- Trb->AdmaPages,
- Trb->Adma64V3Desc
- );
+ PciIo,
+ Trb->AdmaPages,
+ Trb->Adma64V3Desc
+ );
}
+
if (Trb->Adma64V4Desc != NULL) {
PciIo->FreeBuffer (
- PciIo,
- Trb->AdmaPages,
- Trb->Adma64V4Desc
- );
+ PciIo,
+ Trb->AdmaPages,
+ Trb->Adma64V4Desc
+ );
}
+
if (Trb->DataMap != NULL) {
PciIo->Unmap (
- PciIo,
- Trb->DataMap
- );
+ PciIo,
+ Trb->DataMap
+ );
}
+
FreePool (Trb);
return;
}
@@ -1960,20 +2019,21 @@ SdMmcFreeTrb ( **/
EFI_STATUS
SdMmcCheckTrbEnv (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
)
{
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT32 PresentState;
+ EFI_STATUS Status;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 PresentState;
Packet = Trb->Packet;
if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
(Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
- (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
+ (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b))
+ {
//
// Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
// the Present State register to be 0
@@ -2013,14 +2073,14 @@ SdMmcCheckTrbEnv ( **/
EFI_STATUS
SdMmcWaitTrbEnv (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
)
{
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- UINT64 Timeout;
- BOOLEAN InfiniteWait;
+ EFI_STATUS Status;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ UINT64 Timeout;
+ BOOLEAN InfiniteWait;
//
// Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
@@ -2041,6 +2101,7 @@ SdMmcWaitTrbEnv ( if (Status != EFI_NOT_READY) {
return Status;
}
+
//
// Stall for 1 microsecond.
//
@@ -2064,23 +2125,23 @@ SdMmcWaitTrbEnv ( **/
EFI_STATUS
SdMmcExecTrb (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
)
{
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 Cmd;
- UINT16 IntStatus;
- UINT32 Argument;
- UINT32 BlkCount;
- UINT16 BlkSize;
- UINT16 TransMode;
- UINT8 HostCtrl1;
- UINT64 SdmaAddr;
- UINT64 AdmaAddr;
- BOOLEAN AddressingMode64;
+ EFI_STATUS Status;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 Cmd;
+ UINT16 IntStatus;
+ UINT32 Argument;
+ UINT32 BlkCount;
+ UINT16 BlkSize;
+ UINT16 TransMode;
+ UINT8 HostCtrl1;
+ UINT64 SdmaAddr;
+ UINT64 AdmaAddr;
+ BOOLEAN AddressingMode64;
AddressingMode64 = FALSE;
@@ -2094,6 +2155,7 @@ SdMmcExecTrb ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
//
@@ -2104,8 +2166,14 @@ SdMmcExecTrb ( }
if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
- Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
- SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);
+ Status = SdMmcHcCheckMmioSet (
+ PciIo,
+ Trb->Slot,
+ SD_MMC_HC_HOST_CTRL2,
+ sizeof (UINT16),
+ SD_MMC_HC_64_ADDR_EN,
+ SD_MMC_HC_64_ADDR_EN
+ );
if (!EFI_ERROR (Status)) {
AddressingMode64 = TRUE;
}
@@ -2115,15 +2183,16 @@ SdMmcExecTrb ( // Set Host Control 1 register DMA Select field
//
if ((Trb->Mode == SdMmcAdma32bMode) ||
- (Trb->Mode == SdMmcAdma64bV4Mode)) {
+ (Trb->Mode == SdMmcAdma64bV4Mode))
+ {
HostCtrl1 = BIT4;
- Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
} else if (Trb->Mode == SdMmcAdma64bV3Mode) {
HostCtrl1 = BIT4|BIT3;
- Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -2133,7 +2202,8 @@ SdMmcExecTrb ( if (Trb->Mode == SdMmcSdmaMode) {
if ((!AddressingMode64) &&
- ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
+ ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -2150,7 +2220,8 @@ SdMmcExecTrb ( }
} else if ((Trb->Mode == SdMmcAdma32bMode) ||
(Trb->Mode == SdMmcAdma64bV3Mode) ||
- (Trb->Mode == SdMmcAdma64bV4Mode)) {
+ (Trb->Mode == SdMmcAdma64bV4Mode))
+ {
AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
if (EFI_ERROR (Status)) {
@@ -2178,11 +2249,13 @@ SdMmcExecTrb ( //
BlkCount = (Trb->DataLen / Trb->BlockSize);
}
+
if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
} else {
Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
}
+
if (EFI_ERROR (Status)) {
return Status;
}
@@ -2198,12 +2271,15 @@ SdMmcExecTrb ( if (Trb->Mode != SdMmcPioMode) {
TransMode |= BIT0;
}
+
if (Trb->Read) {
TransMode |= BIT4;
}
+
if (BlkCount > 1) {
TransMode |= BIT5 | BIT1;
}
+
//
// Only SD memory card needs to use AUTO CMD12 feature.
//
@@ -2219,10 +2295,11 @@ SdMmcExecTrb ( return Status;
}
- Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
+ Cmd = (UINT16)LShiftU64 (Packet->SdMmcCmdBlk->CommandIndex, 8);
if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
Cmd |= BIT5;
}
+
//
// Convert ResponseType to value
//
@@ -2236,7 +2313,7 @@ SdMmcExecTrb ( break;
case SdMmcResponseTypeR2:
Cmd |= (BIT0 | BIT3);
- break;
+ break;
case SdMmcResponseTypeR3:
case SdMmcResponseTypeR4:
Cmd |= BIT1;
@@ -2250,6 +2327,7 @@ SdMmcExecTrb ( break;
}
}
+
//
// Execute cmd
//
@@ -2281,18 +2359,19 @@ SdMmcSoftwareReset ( if ((ErrIntStatus & 0x0F) != 0) {
SwReset |= BIT1;
}
+
if ((ErrIntStatus & 0x70) != 0) {
SwReset |= BIT2;
}
- Status = SdMmcHcRwMmio (
- Private->PciIo,
- Slot,
- SD_MMC_HC_SW_RST,
- FALSE,
- sizeof (SwReset),
- &SwReset
- );
+ Status = SdMmcHcRwMmio (
+ Private->PciIo,
+ Slot,
+ SD_MMC_HC_SW_RST,
+ FALSE,
+ sizeof (SwReset),
+ &SwReset
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -2429,10 +2508,11 @@ SdMmcGetResponse ( sizeof (UINT32),
&Response[Index]
);
- if (EFI_ERROR (Status)) {
- return Status;
- }
+ if (EFI_ERROR (Status)) {
+ return Status;
}
+ }
+
CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
return EFI_SUCCESS;
@@ -2474,10 +2554,12 @@ SdMmcCheckCommandComplete ( if (EFI_ERROR (Status)) {
return Status;
}
+
Status = SdMmcGetResponse (Private, Trb);
if (EFI_ERROR (Status)) {
return Status;
}
+
Trb->CommandComplete = TRUE;
return EFI_SUCCESS;
}
@@ -2503,11 +2585,11 @@ SdMmcTransferDataWithPio ( IN UINT16 IntStatus
)
{
- EFI_STATUS Status;
- UINT16 Data16;
- UINT32 BlockCount;
+ EFI_STATUS Status;
+ UINT16 Data16;
+ UINT32 BlockCount;
EFI_PCI_IO_PROTOCOL_WIDTH Width;
- UINTN Count;
+ UINTN Count;
BlockCount = (Trb->DataLen / Trb->BlockSize);
if (Trb->DataLen % Trb->BlockSize != 0) {
@@ -2533,45 +2615,49 @@ SdMmcTransferDataWithPio ( Width = EfiPciIoWidthFifoUint8;
Count = Trb->BlockSize;
break;
- }
+ }
if (Trb->Read) {
if ((IntStatus & BIT5) == 0) {
return EFI_NOT_READY;
}
+
Data16 = BIT5;
SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16);
Status = Private->PciIo->Mem.Read (
- Private->PciIo,
- Width,
- Trb->Slot,
- SD_MMC_HC_BUF_DAT_PORT,
- Count,
- (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))
- );
+ Private->PciIo,
+ Width,
+ Trb->Slot,
+ SD_MMC_HC_BUF_DAT_PORT,
+ Count,
+ (VOID *)((UINT8 *)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))
+ );
if (EFI_ERROR (Status)) {
return Status;
}
+
Trb->PioBlockIndex++;
} else {
if ((IntStatus & BIT4) == 0) {
return EFI_NOT_READY;
}
+
Data16 = BIT4;
SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16);
Status = Private->PciIo->Mem.Write (
- Private->PciIo,
- Width,
- Trb->Slot,
- SD_MMC_HC_BUF_DAT_PORT,
- Count,
- (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))
- );
+ Private->PciIo,
+ Width,
+ Trb->Slot,
+ SD_MMC_HC_BUF_DAT_PORT,
+ Count,
+ (VOID *)((UINT8 *)Trb->Data + (Trb->BlockSize * Trb->PioBlockIndex))
+ );
if (EFI_ERROR (Status)) {
return Status;
}
+
Trb->PioBlockIndex++;
}
@@ -2667,7 +2753,7 @@ SdMmcCheckDataTransfer ( return Status;
}
- if (Trb->Mode == SdMmcPioMode && !Trb->PioModeTransferCompleted) {
+ if ((Trb->Mode == SdMmcPioMode) && !Trb->PioModeTransferCompleted) {
Status = SdMmcTransferDataWithPio (Private, Trb, IntStatus);
if (EFI_ERROR (Status)) {
return Status;
@@ -2687,6 +2773,7 @@ SdMmcCheckDataTransfer ( if (EFI_ERROR (Status)) {
return Status;
}
+
Status = SdMmcUpdateSdmaAddress (Private, Trb);
if (EFI_ERROR (Status)) {
return Status;
@@ -2709,15 +2796,15 @@ SdMmcCheckDataTransfer ( **/
EFI_STATUS
SdMmcCheckTrbResult (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
)
{
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- UINT16 IntStatus;
+ EFI_STATUS Status;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ UINT16 IntStatus;
- Packet = Trb->Packet;
+ Packet = Trb->Packet;
//
// Check Trb execution result by reading Normal Interrupt Status register.
//
@@ -2750,7 +2837,8 @@ SdMmcCheckTrbResult ( if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
(Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
((Private->Slot[Trb->Slot].CardType == SdCardType) &&
- (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
+ (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK)))
+ {
Status = SdMmcTransferDataWithPio (Private, Trb, IntStatus);
goto Done;
}
@@ -2762,9 +2850,10 @@ SdMmcCheckTrbResult ( }
}
- if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc ||
- Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b ||
- Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b) {
+ if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
+ (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
+ (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b))
+ {
Status = SdMmcCheckDataTransfer (Private, Trb, IntStatus);
} else {
Status = EFI_SUCCESS;
@@ -2797,14 +2886,14 @@ Done: **/
EFI_STATUS
SdMmcWaitTrbResult (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN SD_MMC_HC_TRB *Trb
+ IN SD_MMC_HC_PRIVATE_DATA *Private,
+ IN SD_MMC_HC_TRB *Trb
)
{
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- UINT64 Timeout;
- BOOLEAN InfiniteWait;
+ EFI_STATUS Status;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+ UINT64 Timeout;
+ BOOLEAN InfiniteWait;
Packet = Trb->Packet;
//
@@ -2825,6 +2914,7 @@ SdMmcWaitTrbResult ( if (Status != EFI_NOT_READY) {
return Status;
}
+
//
// Stall for 1 microsecond.
//
@@ -2835,4 +2925,3 @@ SdMmcWaitTrbResult ( return EFI_TIMEOUT;
}
-
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index 16229a846c..91155770e0 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -14,9 +14,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// SD Host Controller SlotInfo Register Offset
//
-#define SD_MMC_HC_SLOT_OFFSET 0x40
+#define SD_MMC_HC_SLOT_OFFSET 0x40
-#define SD_MMC_HC_MAX_SLOT 6
+#define SD_MMC_HC_MAX_SLOT 6
//
// SD Host Controller MMIO Register Offset
@@ -60,17 +60,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// SD Host Controller bits to HOST_CTRL2 register
//
-#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
-#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
-#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
-#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
-#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
-#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
-#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
-#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
-#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
-#define SD_MMC_HC_CTRL_MMC_HS200 0x0003
-#define SD_MMC_HC_CTRL_MMC_HS400 0x0005
+#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
+#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
+#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
+#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
+#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
+#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
+#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
+#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
+#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
+#define SD_MMC_HC_CTRL_MMC_HS200 0x0003
+#define SD_MMC_HC_CTRL_MMC_HS400 0x0005
#define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK 0x0030
@@ -97,113 +97,113 @@ typedef enum { //
// The maximum data length of each descriptor line
//
-#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB
-#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB
+#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB
+#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB
//
// ADMA descriptor for 32b addressing.
//
typedef struct {
- UINT32 Valid:1;
- UINT32 End:1;
- UINT32 Int:1;
- UINT32 Reserved:1;
- UINT32 Act:2;
- UINT32 UpperLength:10;
- UINT32 LowerLength:16;
- UINT32 Address;
+ UINT32 Valid : 1;
+ UINT32 End : 1;
+ UINT32 Int : 1;
+ UINT32 Reserved : 1;
+ UINT32 Act : 2;
+ UINT32 UpperLength : 10;
+ UINT32 LowerLength : 16;
+ UINT32 Address;
} SD_MMC_HC_ADMA_32_DESC_LINE;
//
// ADMA descriptor for 64b addressing.
//
typedef struct {
- UINT32 Valid:1;
- UINT32 End:1;
- UINT32 Int:1;
- UINT32 Reserved:1;
- UINT32 Act:2;
- UINT32 UpperLength:10;
- UINT32 LowerLength:16;
- UINT32 LowerAddress;
- UINT32 UpperAddress;
+ UINT32 Valid : 1;
+ UINT32 End : 1;
+ UINT32 Int : 1;
+ UINT32 Reserved : 1;
+ UINT32 Act : 2;
+ UINT32 UpperLength : 10;
+ UINT32 LowerLength : 16;
+ UINT32 LowerAddress;
+ UINT32 UpperAddress;
} SD_MMC_HC_ADMA_64_V3_DESC_LINE;
typedef struct {
- UINT32 Valid:1;
- UINT32 End:1;
- UINT32 Int:1;
- UINT32 Reserved:1;
- UINT32 Act:2;
- UINT32 UpperLength:10;
- UINT32 LowerLength:16;
- UINT32 LowerAddress;
- UINT32 UpperAddress;
- UINT32 Reserved1;
+ UINT32 Valid : 1;
+ UINT32 End : 1;
+ UINT32 Int : 1;
+ UINT32 Reserved : 1;
+ UINT32 Act : 2;
+ UINT32 UpperLength : 10;
+ UINT32 LowerLength : 16;
+ UINT32 LowerAddress;
+ UINT32 UpperAddress;
+ UINT32 Reserved1;
} SD_MMC_HC_ADMA_64_V4_DESC_LINE;
-#define SD_MMC_SDMA_BOUNDARY 512 * 1024
-#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
+#define SD_MMC_SDMA_BOUNDARY 512 * 1024
+#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
typedef struct {
- UINT8 FirstBar:3; // bit 0:2
- UINT8 Reserved:1; // bit 3
- UINT8 SlotNum:3; // bit 4:6
- UINT8 Reserved1:1; // bit 7
+ UINT8 FirstBar : 3; // bit 0:2
+ UINT8 Reserved : 1; // bit 3
+ UINT8 SlotNum : 3; // bit 4:6
+ UINT8 Reserved1 : 1; // bit 7
} SD_MMC_HC_SLOT_INFO;
typedef struct {
- UINT32 TimeoutFreq:6; // bit 0:5
- UINT32 Reserved:1; // bit 6
- UINT32 TimeoutUnit:1; // bit 7
- UINT32 BaseClkFreq:8; // bit 8:15
- UINT32 MaxBlkLen:2; // bit 16:17
- UINT32 BusWidth8:1; // bit 18
- UINT32 Adma2:1; // bit 19
- UINT32 Reserved2:1; // bit 20
- UINT32 HighSpeed:1; // bit 21
- UINT32 Sdma:1; // bit 22
- UINT32 SuspRes:1; // bit 23
- UINT32 Voltage33:1; // bit 24
- UINT32 Voltage30:1; // bit 25
- UINT32 Voltage18:1; // bit 26
- UINT32 SysBus64V4:1; // bit 27
- UINT32 SysBus64V3:1; // bit 28
- UINT32 AsyncInt:1; // bit 29
- UINT32 SlotType:2; // bit 30:31
- UINT32 Sdr50:1; // bit 32
- UINT32 Sdr104:1; // bit 33
- UINT32 Ddr50:1; // bit 34
- UINT32 Reserved3:1; // bit 35
- UINT32 DriverTypeA:1; // bit 36
- UINT32 DriverTypeC:1; // bit 37
- UINT32 DriverTypeD:1; // bit 38
- UINT32 DriverType4:1; // bit 39
- UINT32 TimerCount:4; // bit 40:43
- UINT32 Reserved4:1; // bit 44
- UINT32 TuningSDR50:1; // bit 45
- UINT32 RetuningMod:2; // bit 46:47
- UINT32 ClkMultiplier:8; // bit 48:55
- UINT32 Reserved5:7; // bit 56:62
- UINT32 Hs400:1; // bit 63
+ UINT32 TimeoutFreq : 6; // bit 0:5
+ UINT32 Reserved : 1; // bit 6
+ UINT32 TimeoutUnit : 1; // bit 7
+ UINT32 BaseClkFreq : 8; // bit 8:15
+ UINT32 MaxBlkLen : 2; // bit 16:17
+ UINT32 BusWidth8 : 1; // bit 18
+ UINT32 Adma2 : 1; // bit 19
+ UINT32 Reserved2 : 1; // bit 20
+ UINT32 HighSpeed : 1; // bit 21
+ UINT32 Sdma : 1; // bit 22
+ UINT32 SuspRes : 1; // bit 23
+ UINT32 Voltage33 : 1; // bit 24
+ UINT32 Voltage30 : 1; // bit 25
+ UINT32 Voltage18 : 1; // bit 26
+ UINT32 SysBus64V4 : 1; // bit 27
+ UINT32 SysBus64V3 : 1; // bit 28
+ UINT32 AsyncInt : 1; // bit 29
+ UINT32 SlotType : 2; // bit 30:31
+ UINT32 Sdr50 : 1; // bit 32
+ UINT32 Sdr104 : 1; // bit 33
+ UINT32 Ddr50 : 1; // bit 34
+ UINT32 Reserved3 : 1; // bit 35
+ UINT32 DriverTypeA : 1; // bit 36
+ UINT32 DriverTypeC : 1; // bit 37
+ UINT32 DriverTypeD : 1; // bit 38
+ UINT32 DriverType4 : 1; // bit 39
+ UINT32 TimerCount : 4; // bit 40:43
+ UINT32 Reserved4 : 1; // bit 44
+ UINT32 TuningSDR50 : 1; // bit 45
+ UINT32 RetuningMod : 2; // bit 46:47
+ UINT32 ClkMultiplier : 8; // bit 48:55
+ UINT32 Reserved5 : 7; // bit 56:62
+ UINT32 Hs400 : 1; // bit 63
} SD_MMC_HC_SLOT_CAP;
//
// SD Host controller version
//
-#define SD_MMC_HC_CTRL_VER_100 0x00
-#define SD_MMC_HC_CTRL_VER_200 0x01
-#define SD_MMC_HC_CTRL_VER_300 0x02
-#define SD_MMC_HC_CTRL_VER_400 0x03
-#define SD_MMC_HC_CTRL_VER_410 0x04
-#define SD_MMC_HC_CTRL_VER_420 0x05
+#define SD_MMC_HC_CTRL_VER_100 0x00
+#define SD_MMC_HC_CTRL_VER_200 0x01
+#define SD_MMC_HC_CTRL_VER_300 0x02
+#define SD_MMC_HC_CTRL_VER_400 0x03
+#define SD_MMC_HC_CTRL_VER_410 0x04
+#define SD_MMC_HC_CTRL_VER_420 0x05
//
// SD Host controller V4 enhancements
//
-#define SD_MMC_HC_V4_EN BIT12
-#define SD_MMC_HC_64_ADDR_EN BIT13
-#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
+#define SD_MMC_HC_V4_EN BIT12
+#define SD_MMC_HC_64_ADDR_EN BIT13
+#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
/**
Dump the content of SD/MMC host controller's Capability Register.
@@ -214,8 +214,8 @@ typedef struct { **/
VOID
DumpCapabilityReg (
- IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP *Capability
+ IN UINT8 Slot,
+ IN SD_MMC_HC_SLOT_CAP *Capability
);
/**
@@ -232,9 +232,9 @@ DumpCapabilityReg ( EFI_STATUS
EFIAPI
SdMmcHcGetSlotInfo (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- OUT UINT8 *FirstBar,
- OUT UINT8 *SlotNum
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ OUT UINT8 *FirstBar,
+ OUT UINT8 *SlotNum
);
/**
@@ -263,12 +263,12 @@ SdMmcHcGetSlotInfo ( EFI_STATUS
EFIAPI
SdMmcHcRwMmio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN BOOLEAN Read,
- IN UINT8 Count,
- IN OUT VOID *Data
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN BOOLEAN Read,
+ IN UINT8 Count,
+ IN OUT VOID *Data
);
/**
@@ -295,11 +295,11 @@ SdMmcHcRwMmio ( EFI_STATUS
EFIAPI
SdMmcHcOrMmio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN UINT8 Count,
- IN VOID *OrData
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN UINT8 Count,
+ IN VOID *OrData
);
/**
@@ -326,11 +326,11 @@ SdMmcHcOrMmio ( EFI_STATUS
EFIAPI
SdMmcHcAndMmio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN UINT8 Count,
- IN VOID *AndData
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN UINT8 Count,
+ IN VOID *AndData
);
/**
@@ -358,13 +358,13 @@ SdMmcHcAndMmio ( EFI_STATUS
EFIAPI
SdMmcHcWaitMmioSet (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 BarIndex,
- IN UINT32 Offset,
- IN UINT8 Count,
- IN UINT64 MaskValue,
- IN UINT64 TestValue,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 BarIndex,
+ IN UINT32 Offset,
+ IN UINT8 Count,
+ IN UINT64 MaskValue,
+ IN UINT64 TestValue,
+ IN UINT64 Timeout
);
/**
@@ -398,8 +398,8 @@ SdMmcHcGetControllerVersion ( **/
EFI_STATUS
SdMmcHcEnableInterrupt (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot
);
/**
@@ -417,7 +417,7 @@ EFI_STATUS SdMmcHcGetCapability (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
- OUT SD_MMC_HC_SLOT_CAP *Capability
+ OUT SD_MMC_HC_SLOT_CAP *Capability
);
/**
@@ -435,7 +435,7 @@ EFI_STATUS SdMmcHcGetMaxCurrent (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
- OUT UINT64 *MaxCurrent
+ OUT UINT64 *MaxCurrent
);
/**
@@ -455,9 +455,9 @@ SdMmcHcGetMaxCurrent ( **/
EFI_STATUS
SdMmcHcCardDetect (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- OUT BOOLEAN *MediaPresent
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ OUT BOOLEAN *MediaPresent
);
/**
@@ -474,8 +474,8 @@ SdMmcHcCardDetect ( **/
EFI_STATUS
SdMmcHcStopClock (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot
);
/**
@@ -508,9 +508,9 @@ SdMmcHcStartSdClock ( **/
EFI_STATUS
SdMmcHcPowerControl (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN UINT8 PowerCtrl
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN UINT8 PowerCtrl
);
/**
@@ -528,9 +528,9 @@ SdMmcHcPowerControl ( **/
EFI_STATUS
SdMmcHcSetBusWidth (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN UINT16 BusWidth
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN UINT16 BusWidth
);
/**
@@ -548,9 +548,9 @@ SdMmcHcSetBusWidth ( **/
EFI_STATUS
SdMmcHcInitPowerVoltage (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP Capability
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN SD_MMC_HC_SLOT_CAP Capability
);
/**
@@ -567,8 +567,8 @@ SdMmcHcInitPowerVoltage ( **/
EFI_STATUS
SdMmcHcInitTimeoutCtrl (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot
);
/**
@@ -584,10 +584,10 @@ SdMmcHcInitTimeoutCtrl ( **/
EFI_STATUS
SdMmcHcUhsSignaling (
- IN EFI_HANDLE ControllerHandle,
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN SD_MMC_BUS_MODE Timing
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN SD_MMC_BUS_MODE Timing
);
/**
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c index 9c18e6fddc..89e0a1b6a4 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c @@ -11,7 +11,7 @@ EDKII_SD_MMC_HOST_CONTROLLER_PPI mSdMmcHostControllerPpi = { GetSdMmcHcMmioBar };
-EFI_PEI_PPI_DESCRIPTOR mPpiList = {
+EFI_PEI_PPI_DESCRIPTOR mPpiList = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiPeiSdMmcHostControllerPpiGuid,
&mSdMmcHostControllerPpi
@@ -34,10 +34,10 @@ EFI_PEI_PPI_DESCRIPTOR mPpiList = { EFI_STATUS
EFIAPI
GetSdMmcHcMmioBar (
- IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,
- IN UINT8 ControllerId,
- IN OUT UINTN **MmioBar,
- OUT UINT8 *BarNum
+ IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,
+ IN UINT8 ControllerId,
+ IN OUT UINTN **MmioBar,
+ OUT UINT8 *BarNum
)
{
SD_MMC_HC_PEI_PRIVATE_DATA *Private;
@@ -70,26 +70,26 @@ GetSdMmcHcMmioBar ( EFI_STATUS
EFIAPI
InitializeSdMmcHcPeim (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_BOOT_MODE BootMode;
- EFI_STATUS Status;
- UINT16 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT32 Size;
- UINT64 MmioSize;
- UINT8 SubClass;
- UINT8 BaseClass;
- UINT8 SlotInfo;
- UINT8 SlotNum;
- UINT8 FirstBar;
- UINT8 Index;
- UINT8 Slot;
- UINT32 BarAddr;
- SD_MMC_HC_PEI_PRIVATE_DATA *Private;
+ EFI_BOOT_MODE BootMode;
+ EFI_STATUS Status;
+ UINT16 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT32 Size;
+ UINT64 MmioSize;
+ UINT8 SubClass;
+ UINT8 BaseClass;
+ UINT8 SlotInfo;
+ UINT8 SlotNum;
+ UINT8 FirstBar;
+ UINT8 Index;
+ UINT8 Slot;
+ UINT32 BarAddr;
+ SD_MMC_HC_PEI_PRIVATE_DATA *Private;
//
// Shadow this PEIM to run from memory
@@ -106,7 +106,7 @@ InitializeSdMmcHcPeim ( return EFI_SUCCESS;
}
- Private = (SD_MMC_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));
+ Private = (SD_MMC_HC_PEI_PRIVATE_DATA *)AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((DEBUG_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));
return EFI_OUT_OF_RESOURCES;
@@ -129,15 +129,15 @@ InitializeSdMmcHcPeim ( // Get the SD/MMC Pci host controller's Slot Info.
//
SlotInfo = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, SD_MMC_HC_PEI_SLOT_OFFSET));
- FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).FirstBar;
- SlotNum = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).SlotNum + 1;
+ FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO *)&SlotInfo).FirstBar;
+ SlotNum = (*(SD_MMC_HC_PEI_SLOT_INFO *)&SlotInfo).SlotNum + 1;
ASSERT ((FirstBar + SlotNum) < MAX_SD_MMC_SLOTS);
for (Index = 0, Slot = FirstBar; Slot < (FirstBar + SlotNum); Index++, Slot++) {
//
// Get the SD/MMC Pci host controller's MMIO region size.
//
- PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
+ PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16) ~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), 0xFFFFFFFF);
Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot));
@@ -153,8 +153,8 @@ InitializeSdMmcHcPeim ( // Memory space: anywhere in 64 bit address space
//
MmioSize = Size & 0xFFFFFFF0;
- PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
- Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
+ PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
+ Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
//
// Fix the length to support some spefic 64 bit BAR
//
@@ -162,7 +162,7 @@ InitializeSdMmcHcPeim ( //
// Calculate the size of 64bit bar
//
- MmioSize |= LShiftU64 ((UINT64) Size, 32);
+ MmioSize |= LShiftU64 ((UINT64)Size, 32);
MmioSize = (~(MmioSize)) + 1;
//
// Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit BAR.
@@ -175,7 +175,8 @@ InitializeSdMmcHcPeim ( //
ASSERT (FALSE);
continue;
- };
+ }
+
//
// Assign resource to the SdMmc Pci host controller's MMIO BAR.
// Enable the SdMmc Pci host controller by setting BME and MSE bits of PCI_CMD register.
@@ -187,8 +188,9 @@ InitializeSdMmcHcPeim ( //
Private->MmioBar[Private->TotalSdMmcHcs].SlotNum++;
Private->MmioBar[Private->TotalSdMmcHcs].MmioBarAddr[Index] = BarAddr;
- BarAddr += (UINT32)MmioSize;
+ BarAddr += (UINT32)MmioSize;
}
+
Private->TotalSdMmcHcs++;
ASSERT (Private->TotalSdMmcHcs < MAX_SD_MMC_HCS);
}
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.h index ee04a6b897..ade59dd6e3 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.h @@ -22,10 +22,10 @@ #include <Library/PeiServicesLib.h>
#include <Library/MemoryAllocationLib.h>
-#define SD_MMC_HC_PEI_SIGNATURE SIGNATURE_32 ('S', 'D', 'M', 'C')
+#define SD_MMC_HC_PEI_SIGNATURE SIGNATURE_32 ('S', 'D', 'M', 'C')
-#define MAX_SD_MMC_HCS 8
-#define MAX_SD_MMC_SLOTS 6
+#define MAX_SD_MMC_HCS 8
+#define MAX_SD_MMC_SLOTS 6
//
// SD Host Controller SlotInfo Register Offset
@@ -33,23 +33,23 @@ #define SD_MMC_HC_PEI_SLOT_OFFSET 0x40
typedef struct {
- UINT8 FirstBar:3; // bit 0:2
- UINT8 Reserved:1; // bit 3
- UINT8 SlotNum:3; // bit 4:6
- UINT8 Reserved1:1; // bit 7
+ UINT8 FirstBar : 3; // bit 0:2
+ UINT8 Reserved : 1; // bit 3
+ UINT8 SlotNum : 3; // bit 4:6
+ UINT8 Reserved1 : 1; // bit 7
} SD_MMC_HC_PEI_SLOT_INFO;
typedef struct {
- UINTN SlotNum;
- UINTN MmioBarAddr[MAX_SD_MMC_SLOTS];
+ UINTN SlotNum;
+ UINTN MmioBarAddr[MAX_SD_MMC_SLOTS];
} SD_MMC_HC_PEI_BAR;
typedef struct {
- UINTN Signature;
- EDKII_SD_MMC_HOST_CONTROLLER_PPI SdMmcHostControllerPpi;
- EFI_PEI_PPI_DESCRIPTOR PpiList;
- UINTN TotalSdMmcHcs;
- SD_MMC_HC_PEI_BAR MmioBar[MAX_SD_MMC_HCS];
+ UINTN Signature;
+ EDKII_SD_MMC_HOST_CONTROLLER_PPI SdMmcHostControllerPpi;
+ EFI_PEI_PPI_DESCRIPTOR PpiList;
+ UINTN TotalSdMmcHcs;
+ SD_MMC_HC_PEI_BAR MmioBar[MAX_SD_MMC_HCS];
} SD_MMC_HC_PEI_PRIVATE_DATA;
#define SD_MMC_HC_PEI_PRIVATE_DATA_FROM_THIS(a) CR (a, SD_MMC_HC_PEI_PRIVATE_DATA, SdMmcHostControllerPpi, SD_MMC_HC_PEI_SIGNATURE)
@@ -71,10 +71,10 @@ typedef struct { EFI_STATUS
EFIAPI
GetSdMmcHcMmioBar (
- IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,
- IN UINT8 ControllerId,
- IN OUT UINTN **MmioBar,
- OUT UINT8 *BarNum
+ IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,
+ IN UINT8 ControllerId,
+ IN OUT UINTN **MmioBar,
+ OUT UINT8 *BarNum
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/UfsPciHcDxe/ComponentName.c index 5dc67e8905..cff05b4da5 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/UfsPciHcDxe/ComponentName.c @@ -12,7 +12,7 @@ //
// EFI Component Name Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gUfsHcComponentName = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gUfsHcComponentName = {
UfsHcComponentNameGetDriverName,
UfsHcComponentNameGetControllerName,
"eng"
@@ -21,13 +21,13 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gUfsHcComponentName = //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gUfsHcComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) UfsHcComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) UfsHcComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gUfsHcComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)UfsHcComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)UfsHcComponentNameGetControllerName,
"en"
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcDriverNameTable[] = {
{
"eng;en",
L"Universal Flash Storage (UFS) Pci Host Controller Driver"
@@ -38,7 +38,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcDriverNameTable[] = }
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcControllerNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcControllerNameTable[] = {
{
"eng;en",
L"Universal Flash Storage (UFS) Pci Host Controller"
@@ -91,9 +91,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcControllerNameTable EFI_STATUS
EFIAPI
UfsHcComponentNameGetDriverName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN CHAR8 *Language,
- OUT CHAR16 **DriverName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
@@ -176,16 +176,16 @@ UfsHcComponentNameGetDriverName ( EFI_STATUS
EFIAPI
UfsHcComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- if (Language == NULL || ControllerName == NULL) {
+ if ((Language == NULL) || (ControllerName == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -215,5 +215,4 @@ UfsHcComponentNameGetControllerName ( ControllerName,
(BOOLEAN)(This == &gUfsHcComponentName)
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.c b/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.c index 4be90d7a80..5756ef0791 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.c @@ -12,7 +12,7 @@ //
// NVM Express Driver Binding Protocol Instance
//
-EFI_DRIVER_BINDING_PROTOCOL gUfsHcDriverBinding = {
+EFI_DRIVER_BINDING_PROTOCOL gUfsHcDriverBinding = {
UfsHcDriverBindingSupported,
UfsHcDriverBindingStart,
UfsHcDriverBindingStop,
@@ -24,7 +24,7 @@ EFI_DRIVER_BINDING_PROTOCOL gUfsHcDriverBinding = { //
// Template for Ufs host controller private data.
//
-UFS_HOST_CONTROLLER_PRIVATE_DATA gUfsHcTemplate = {
+UFS_HOST_CONTROLLER_PRIVATE_DATA gUfsHcTemplate = {
UFS_HC_PRIVATE_DATA_SIGNATURE, // Signature
{ // UfsHcProtocol
UfsHcGetMmioBar,
@@ -53,15 +53,15 @@ UFS_HOST_CONTROLLER_PRIVATE_DATA gUfsHcTemplate = { EFI_STATUS
EFIAPI
UfsHcGetMmioBar (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- OUT UINTN *MmioBar
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ OUT UINTN *MmioBar
)
{
- UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT8 BarIndex;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
+ UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT8 BarIndex;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
if ((This == NULL) || (MmioBar == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -76,7 +76,7 @@ UfsHcGetMmioBar ( PciIo,
BarIndex,
NULL,
- (VOID**) &BarDesc
+ (VOID **)&BarDesc
);
if (EFI_ERROR (Status)) {
return Status;
@@ -115,8 +115,8 @@ UfsHcMap ( IN EDKII_UFS_HOST_CONTROLLER_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
)
{
UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
@@ -130,7 +130,7 @@ UfsHcMap ( Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
PciIo = Private->PciIo;
- Status = PciIo->Map (PciIo, (EFI_PCI_IO_PROTOCOL_OPERATION)Operation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
+ Status = PciIo->Map (PciIo, (EFI_PCI_IO_PROTOCOL_OPERATION)Operation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
return Status;
}
@@ -147,8 +147,8 @@ UfsHcMap ( EFI_STATUS
EFIAPI
UfsHcUnmap (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- IN VOID *Mapping
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ IN VOID *Mapping
)
{
UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
@@ -162,7 +162,7 @@ UfsHcUnmap ( Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
PciIo = Private->PciIo;
- Status = PciIo->Unmap (PciIo, Mapping);
+ Status = PciIo->Unmap (PciIo, Mapping);
return Status;
}
@@ -189,12 +189,12 @@ UfsHcUnmap ( EFI_STATUS
EFIAPI
UfsHcAllocateBuffer (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
)
{
UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
@@ -208,7 +208,7 @@ UfsHcAllocateBuffer ( Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
PciIo = Private->PciIo;
- Status = PciIo->AllocateBuffer (PciIo, Type, MemoryType, Pages, HostAddress, Attributes);
+ Status = PciIo->AllocateBuffer (PciIo, Type, MemoryType, Pages, HostAddress, Attributes);
return Status;
}
@@ -227,9 +227,9 @@ UfsHcAllocateBuffer ( EFI_STATUS
EFIAPI
UfsHcFreeBuffer (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- IN UINTN Pages,
- IN VOID *HostAddress
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
)
{
UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
@@ -243,7 +243,7 @@ UfsHcFreeBuffer ( Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
PciIo = Private->PciIo;
- Status = PciIo->FreeBuffer (PciIo, Pages, HostAddress);
+ Status = PciIo->FreeBuffer (PciIo, Pages, HostAddress);
return Status;
}
@@ -261,7 +261,7 @@ UfsHcFreeBuffer ( EFI_STATUS
EFIAPI
UfsHcFlush (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This
)
{
UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
@@ -271,7 +271,7 @@ UfsHcFlush ( Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
PciIo = Private->PciIo;
- Status = PciIo->Flush (PciIo);
+ Status = PciIo->Flush (PciIo);
return Status;
}
@@ -312,7 +312,7 @@ UfsHcMmioRead ( PciIo = Private->PciIo;
BarIndex = Private->BarIndex;
- Status = PciIo->Mem.Read (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);
+ Status = PciIo->Mem.Read (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);
return Status;
}
@@ -354,7 +354,7 @@ UfsHcMmioWrite ( PciIo = Private->PciIo;
BarIndex = Private->BarIndex;
- Status = PciIo->Mem.Write (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);
+ Status = PciIo->Mem.Write (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);
return Status;
}
@@ -426,7 +426,7 @@ UfsHcDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
- (VOID *) &ParentDevicePath,
+ (VOID *)&ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -437,15 +437,16 @@ UfsHcDriverBindingSupported ( //
return Status;
}
+
//
// Close the protocol because we don't use it here
//
gBS->CloseProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
//
// Now test the EfiPciIoProtocol
@@ -453,7 +454,7 @@ UfsHcDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -461,6 +462,7 @@ UfsHcDriverBindingSupported ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Now further check the PCI header: Base class (offset 0x0B) and
// Sub Class (offset 0x0A). This controller should be an UFS controller
@@ -474,28 +476,30 @@ UfsHcDriverBindingSupported ( );
if (EFI_ERROR (Status)) {
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
return EFI_UNSUPPORTED;
}
+
//
// Since we already got the PciData, we can close protocol to avoid to carry it on for multiple exit points.
//
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
//
// Examine UFS Host Controller PCI Configuration table fields
//
if (PciData.Hdr.ClassCode[2] == PCI_CLASS_MASS_STORAGE) {
- if (PciData.Hdr.ClassCode[1] == 0x09 ) { //UFS Controller Subclass
+ if (PciData.Hdr.ClassCode[1] == 0x09 ) {
+ // UFS Controller Subclass
UfsHcFound = TRUE;
}
}
@@ -507,7 +511,6 @@ UfsHcDriverBindingSupported ( return Status;
}
-
/**
Starts a device controller or a bus controller.
@@ -551,12 +554,12 @@ UfsHcDriverBindingStart ( IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
- UINT64 Supports;
- UINT8 BarIndex;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;
+ UINT64 Supports;
+ UINT8 BarIndex;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
PciIo = NULL;
Private = NULL;
@@ -569,7 +572,7 @@ UfsHcDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -602,7 +605,7 @@ UfsHcDriverBindingStart ( PciIo,
BarIndex,
NULL,
- (VOID**) &BarDesc
+ (VOID **)&BarDesc
);
if (Status == EFI_UNSUPPORTED) {
continue;
@@ -656,7 +659,7 @@ UfsHcDriverBindingStart ( &Controller,
&gEdkiiUfsHostControllerProtocolGuid,
EFI_NATIVE_INTERFACE,
- (VOID*)&(Private->UfsHc)
+ (VOID *)&(Private->UfsHc)
);
Done:
@@ -672,12 +675,13 @@ Done: NULL
);
}
+
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
if (Private != NULL) {
FreePool (Private);
}
@@ -686,7 +690,6 @@ Done: return Status;
}
-
/**
Stops a device controller or a bus controller.
@@ -716,10 +719,10 @@ Done: EFI_STATUS
EFIAPI
UfsHcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -732,7 +735,7 @@ UfsHcDriverBindingStop ( Status = gBS->OpenProtocol (
Controller,
&gEdkiiUfsHostControllerProtocolGuid,
- (VOID **) &UfsHc,
+ (VOID **)&UfsHc,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -794,7 +797,7 @@ UfsHcDriverEntry ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EfiLibInstallDriverBindingComponentName2 (
ImageHandle,
diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.h b/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.h index 1cf1144675..0c329069c3 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/UfsPciHcDxe/UfsPciHcDxe.h @@ -30,27 +30,27 @@ #include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
-extern EFI_DRIVER_BINDING_PROTOCOL gUfsHcDriverBinding;
-extern EFI_COMPONENT_NAME_PROTOCOL gUfsHcComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gUfsHcComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gUfsHcDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gUfsHcComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gUfsHcComponentName2;
//
// Unique signature for private data structure.
//
-#define UFS_HC_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('U','F','S','H')
+#define UFS_HC_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('U','F','S','H')
-typedef struct _UFS_HOST_CONTROLLER_PRIVATE_DATA UFS_HOST_CONTROLLER_PRIVATE_DATA;
+typedef struct _UFS_HOST_CONTROLLER_PRIVATE_DATA UFS_HOST_CONTROLLER_PRIVATE_DATA;
//
// Ufs host controller private data structure.
//
struct _UFS_HOST_CONTROLLER_PRIVATE_DATA {
- UINT32 Signature;
+ UINT32 Signature;
- EDKII_UFS_HOST_CONTROLLER_PROTOCOL UfsHc;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT8 BarIndex;
- UINT64 PciAttributes;
+ EDKII_UFS_HOST_CONTROLLER_PROTOCOL UfsHc;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 BarIndex;
+ UINT64 PciAttributes;
};
#define UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC(a) \
@@ -178,11 +178,11 @@ UfsHcComponentNameGetDriverName ( EFI_STATUS
EFIAPI
UfsHcComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
/**
@@ -307,10 +307,10 @@ UfsHcDriverBindingStart ( EFI_STATUS
EFIAPI
UfsHcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
/**
@@ -325,8 +325,8 @@ UfsHcDriverBindingStop ( EFI_STATUS
EFIAPI
UfsHcGetMmioBar (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- OUT UINTN *MmioBar
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ OUT UINTN *MmioBar
);
/**
@@ -355,8 +355,8 @@ UfsHcMap ( IN EDKII_UFS_HOST_CONTROLLER_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
);
/**
@@ -372,8 +372,8 @@ UfsHcMap ( EFI_STATUS
EFIAPI
UfsHcUnmap (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- IN VOID *Mapping
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ IN VOID *Mapping
);
/**
@@ -399,12 +399,12 @@ UfsHcUnmap ( EFI_STATUS
EFIAPI
UfsHcAllocateBuffer (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
);
/**
@@ -422,9 +422,9 @@ UfsHcAllocateBuffer ( EFI_STATUS
EFIAPI
UfsHcFreeBuffer (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
- IN UINTN Pages,
- IN VOID *HostAddress
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
);
/**
@@ -441,7 +441,7 @@ UfsHcFreeBuffer ( EFI_STATUS
EFIAPI
UfsHcFlush (
- IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This
);
/**
diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c index 68bfade9c2..ac42b1b796 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c @@ -11,7 +11,7 @@ EDKII_UFS_HOST_CONTROLLER_PPI mUfsHostControllerPpi = { GetUfsHcMmioBar };
-EFI_PEI_PPI_DESCRIPTOR mPpiList = {
+EFI_PEI_PPI_DESCRIPTOR mPpiList = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiPeiUfsHostControllerPpiGuid,
&mUfsHostControllerPpi
@@ -31,9 +31,9 @@ EFI_PEI_PPI_DESCRIPTOR mPpiList = { EFI_STATUS
EFIAPI
GetUfsHcMmioBar (
- IN EDKII_UFS_HOST_CONTROLLER_PPI *This,
- IN UINT8 ControllerId,
- OUT UINTN *MmioBar
+ IN EDKII_UFS_HOST_CONTROLLER_PPI *This,
+ IN UINT8 ControllerId,
+ OUT UINTN *MmioBar
)
{
UFS_HC_PEI_PRIVATE_DATA *Private;
@@ -66,8 +66,8 @@ GetUfsHcMmioBar ( EFI_STATUS
EFIAPI
InitializeUfsHcPeim (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_BOOT_MODE BootMode;
@@ -97,7 +97,7 @@ InitializeUfsHcPeim ( return EFI_SUCCESS;
}
- Private = (UFS_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (UFS_HC_PEI_PRIVATE_DATA));
+ Private = (UFS_HC_PEI_PRIVATE_DATA *)AllocateZeroPool (sizeof (UFS_HC_PEI_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((DEBUG_ERROR, "Failed to allocate memory for UFS_HC_PEI_PRIVATE_DATA! \n"));
return EFI_OUT_OF_RESOURCES;
@@ -119,7 +119,7 @@ InitializeUfsHcPeim ( //
// Get the Ufs Pci host controller's MMIO region size.
//
- PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
+ PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16) ~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
@@ -135,8 +135,8 @@ InitializeUfsHcPeim ( // Memory space: anywhere in 64 bit address space
//
MmioSize = Size & 0xFFFFFFF0;
- PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
- Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
+ PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
+ Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
//
// Fix the length to support some specific 64 bit BAR
@@ -146,7 +146,7 @@ InitializeUfsHcPeim ( //
// Calculate the size of 64bit bar
//
- MmioSize |= LShiftU64 ((UINT64) Size, 32);
+ MmioSize |= LShiftU64 ((UINT64)Size, 32);
MmioSize = (~(MmioSize)) + 1;
//
@@ -160,7 +160,8 @@ InitializeUfsHcPeim ( //
ASSERT (FALSE);
continue;
- };
+ }
+
//
// Assign resource to the Ufs Pci host controller's MMIO BAR.
// Enable the Ufs Pci host controller by setting BME and MSE bits of PCI_CMD register.
diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.h b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.h index 48b42b8833..c04c84e524 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.h +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.h @@ -21,15 +21,15 @@ #include <Library/PeiServicesLib.h>
#include <Library/MemoryAllocationLib.h>
-#define UFS_HC_PEI_SIGNATURE SIGNATURE_32 ('U', 'F', 'S', 'P')
-#define MAX_UFS_HCS 8
+#define UFS_HC_PEI_SIGNATURE SIGNATURE_32 ('U', 'F', 'S', 'P')
+#define MAX_UFS_HCS 8
typedef struct {
- UINTN Signature;
- EDKII_UFS_HOST_CONTROLLER_PPI UfsHostControllerPpi;
- EFI_PEI_PPI_DESCRIPTOR PpiList;
- UINTN TotalUfsHcs;
- UINTN UfsHcPciAddr[MAX_UFS_HCS];
+ UINTN Signature;
+ EDKII_UFS_HOST_CONTROLLER_PPI UfsHostControllerPpi;
+ EFI_PEI_PPI_DESCRIPTOR PpiList;
+ UINTN TotalUfsHcs;
+ UINTN UfsHcPciAddr[MAX_UFS_HCS];
} UFS_HC_PEI_PRIVATE_DATA;
#define UFS_HC_PEI_PRIVATE_DATA_FROM_THIS(a) CR (a, UFS_HC_PEI_PRIVATE_DATA, UfsHostControllerPpi, UFS_HC_PEI_SIGNATURE)
@@ -48,9 +48,9 @@ typedef struct { EFI_STATUS
EFIAPI
GetUfsHcMmioBar (
- IN EDKII_UFS_HOST_CONTROLLER_PPI *This,
- IN UINT8 ControllerId,
- OUT UINTN *MmioBar
+ IN EDKII_UFS_HOST_CONTROLLER_PPI *This,
+ IN UINT8 ControllerId,
+ OUT UINTN *MmioBar
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.c index 572c11c287..7c398cb55a 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.c @@ -8,7 +8,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Uhci.h"
-
//
// EFI Component Name Protocol
//
@@ -22,19 +21,17 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName = //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) UhciComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) UhciComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)UhciComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)UhciComponentNameGetControllerName,
"en"
};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUhciDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUhciDriverNameTable[] = {
{ "eng;en", L"Usb Uhci Driver" },
- { NULL, NULL }
+ { NULL, NULL }
};
-
//
// EFI Component Name Functions
//
@@ -166,16 +163,16 @@ UhciComponentNameGetDriverName ( EFI_STATUS
EFIAPI
UhciComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
- USB_HC_DEV *UhciDev;
- EFI_USB2_HC_PROTOCOL *Usb2Hc;
+ EFI_STATUS Status;
+ USB_HC_DEV *UhciDev;
+ EFI_USB2_HC_PROTOCOL *Usb2Hc;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -202,7 +199,7 @@ UhciComponentNameGetControllerName ( Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
gUhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -221,5 +218,4 @@ UhciComponentNameGetControllerName ( ControllerName,
(BOOLEAN)(This == &gUhciComponentName)
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.h b/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.h index c3b5674e9e..7e6ee93869 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/ComponentName.h @@ -57,7 +57,6 @@ UhciComponentNameGetDriverName ( OUT CHAR16 **DriverName
);
-
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -129,11 +128,11 @@ UhciComponentNameGetDriverName ( EFI_STATUS
EFIAPI
UhciComponentNameGetControllerName (
- IN EFI_COMPONENT_NAME_PROTOCOL *This,
- IN EFI_HANDLE ControllerHandle,
- IN EFI_HANDLE ChildHandle OPTIONAL,
- IN CHAR8 *Language,
- OUT CHAR16 **ControllerName
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c index 9f78f3dbd3..48741085e5 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c @@ -9,8 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Uhci.h"
-
-EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding = {
+EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding = {
UhciDriverBindingSupported,
UhciDriverBindingStart,
UhciDriverBindingStop,
@@ -35,15 +34,16 @@ EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding = { EFI_STATUS
EFIAPI
Uhci2Reset (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT16 Attributes
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT16 Attributes
)
{
- USB_HC_DEV *Uhc;
- EFI_TPL OldTpl;
+ USB_HC_DEV *Uhc;
+ EFI_TPL OldTpl;
if ((Attributes == EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG) ||
- (Attributes == EFI_USB_HC_RESET_HOST_WITH_DEBUG)) {
+ (Attributes == EFI_USB_HC_RESET_HOST_WITH_DEBUG))
+ {
return EFI_UNSUPPORTED;
}
@@ -60,38 +60,38 @@ Uhci2Reset ( );
}
- OldTpl = gBS->RaiseTPL (UHCI_TPL);
+ OldTpl = gBS->RaiseTPL (UHCI_TPL);
switch (Attributes) {
- case EFI_USB_HC_RESET_GLOBAL:
- //
- // Stop schedule and set the Global Reset bit in the command register
- //
- UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
- UhciSetRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_GRESET);
+ case EFI_USB_HC_RESET_GLOBAL:
+ //
+ // Stop schedule and set the Global Reset bit in the command register
+ //
+ UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
+ UhciSetRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_GRESET);
- gBS->Stall (UHC_ROOT_PORT_RESET_STALL);
+ gBS->Stall (UHC_ROOT_PORT_RESET_STALL);
- //
- // Clear the Global Reset bit to zero.
- //
- UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_GRESET);
+ //
+ // Clear the Global Reset bit to zero.
+ //
+ UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_GRESET);
- gBS->Stall (UHC_ROOT_PORT_RECOVERY_STALL);
- break;
+ gBS->Stall (UHC_ROOT_PORT_RECOVERY_STALL);
+ break;
- case EFI_USB_HC_RESET_HOST_CONTROLLER:
- //
- // Stop schedule and set Host Controller Reset bit to 1
- //
- UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
- UhciSetRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_HCRESET);
+ case EFI_USB_HC_RESET_HOST_CONTROLLER:
+ //
+ // Stop schedule and set Host Controller Reset bit to 1
+ //
+ UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
+ UhciSetRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_HCRESET);
- gBS->Stall (UHC_ROOT_PORT_RECOVERY_STALL);
- break;
+ gBS->Stall (UHC_ROOT_PORT_RECOVERY_STALL);
+ break;
- default:
- goto ON_INVAILD_PARAMETER;
+ default:
+ goto ON_INVAILD_PARAMETER;
}
//
@@ -113,7 +113,6 @@ ON_INVAILD_PARAMETER: return EFI_INVALID_PARAMETER;
}
-
/**
Retrieves current state of the USB host controller according to UEFI 2.0 spec.
@@ -128,29 +127,27 @@ ON_INVAILD_PARAMETER: EFI_STATUS
EFIAPI
Uhci2GetState (
- IN EFI_USB2_HC_PROTOCOL *This,
- OUT EFI_USB_HC_STATE *State
+ IN EFI_USB2_HC_PROTOCOL *This,
+ OUT EFI_USB_HC_STATE *State
)
{
- USB_HC_DEV *Uhc;
- UINT16 UsbSts;
- UINT16 UsbCmd;
+ USB_HC_DEV *Uhc;
+ UINT16 UsbSts;
+ UINT16 UsbCmd;
if (State == NULL) {
return EFI_INVALID_PARAMETER;
}
- Uhc = UHC_FROM_USB2_HC_PROTO (This);
+ Uhc = UHC_FROM_USB2_HC_PROTO (This);
- UsbCmd = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
- UsbSts = UhciReadReg (Uhc->PciIo, USBSTS_OFFSET);
+ UsbCmd = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
+ UsbSts = UhciReadReg (Uhc->PciIo, USBSTS_OFFSET);
- if ((UsbCmd & USBCMD_EGSM) !=0 ) {
+ if ((UsbCmd & USBCMD_EGSM) != 0 ) {
*State = EfiUsbHcStateSuspend;
-
} else if ((UsbSts & USBSTS_HCH) != 0) {
*State = EfiUsbHcStateHalt;
-
} else {
*State = EfiUsbHcStateOperational;
}
@@ -158,7 +155,6 @@ Uhci2GetState ( return EFI_SUCCESS;
}
-
/**
Sets the USB host controller to a specific state according to UEFI 2.0 spec.
@@ -174,18 +170,18 @@ Uhci2GetState ( EFI_STATUS
EFIAPI
Uhci2SetState (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN EFI_USB_HC_STATE State
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN EFI_USB_HC_STATE State
)
{
- EFI_USB_HC_STATE CurState;
- USB_HC_DEV *Uhc;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
- UINT16 UsbCmd;
+ EFI_USB_HC_STATE CurState;
+ USB_HC_DEV *Uhc;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ UINT16 UsbCmd;
- Uhc = UHC_FROM_USB2_HC_PROTO (This);
- Status = Uhci2GetState (This, &CurState);
+ Uhc = UHC_FROM_USB2_HC_PROTO (This);
+ Status = Uhci2GetState (This, &CurState);
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
@@ -195,69 +191,68 @@ Uhci2SetState ( return EFI_SUCCESS;
}
- Status = EFI_SUCCESS;
- OldTpl = gBS->RaiseTPL (UHCI_TPL);
+ Status = EFI_SUCCESS;
+ OldTpl = gBS->RaiseTPL (UHCI_TPL);
switch (State) {
- case EfiUsbHcStateHalt:
- Status = UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
- break;
-
- case EfiUsbHcStateOperational:
- UsbCmd = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
+ case EfiUsbHcStateHalt:
+ Status = UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
+ break;
- if (CurState == EfiUsbHcStateHalt) {
- //
- // Set Run/Stop bit to 1, also set the bandwidht reclamation
- // point to 64 bytes
- //
- UsbCmd |= USBCMD_RS | USBCMD_MAXP;
- UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);
+ case EfiUsbHcStateOperational:
+ UsbCmd = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
- } else if (CurState == EfiUsbHcStateSuspend) {
- //
- // If FGR(Force Global Resume) bit is 0, set it
- //
- if ((UsbCmd & USBCMD_FGR) == 0) {
- UsbCmd |= USBCMD_FGR;
+ if (CurState == EfiUsbHcStateHalt) {
+ //
+ // Set Run/Stop bit to 1, also set the bandwidht reclamation
+ // point to 64 bytes
+ //
+ UsbCmd |= USBCMD_RS | USBCMD_MAXP;
+ UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);
+ } else if (CurState == EfiUsbHcStateSuspend) {
+ //
+ // If FGR(Force Global Resume) bit is 0, set it
+ //
+ if ((UsbCmd & USBCMD_FGR) == 0) {
+ UsbCmd |= USBCMD_FGR;
+ UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);
+ }
+
+ //
+ // wait 20ms to let resume complete (20ms is specified by UHCI spec)
+ //
+ gBS->Stall (UHC_FORCE_GLOBAL_RESUME_STALL);
+
+ //
+ // Write FGR bit to 0 and EGSM(Enter Global Suspend Mode) bit to 0
+ //
+ UsbCmd &= ~USBCMD_FGR;
+ UsbCmd &= ~USBCMD_EGSM;
+ UsbCmd |= USBCMD_RS;
UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);
}
- //
- // wait 20ms to let resume complete (20ms is specified by UHCI spec)
- //
- gBS->Stall (UHC_FORCE_GLOBAL_RESUME_STALL);
+ break;
+
+ case EfiUsbHcStateSuspend:
+ Status = Uhci2SetState (This, EfiUsbHcStateHalt);
+
+ if (EFI_ERROR (Status)) {
+ Status = EFI_DEVICE_ERROR;
+ goto ON_EXIT;
+ }
//
- // Write FGR bit to 0 and EGSM(Enter Global Suspend Mode) bit to 0
+ // Set Enter Global Suspend Mode bit to 1.
//
- UsbCmd &= ~USBCMD_FGR;
- UsbCmd &= ~USBCMD_EGSM;
- UsbCmd |= USBCMD_RS;
+ UsbCmd = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
+ UsbCmd |= USBCMD_EGSM;
UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);
- }
-
- break;
-
- case EfiUsbHcStateSuspend:
- Status = Uhci2SetState (This, EfiUsbHcStateHalt);
-
- if (EFI_ERROR (Status)) {
- Status = EFI_DEVICE_ERROR;
- goto ON_EXIT;
- }
-
- //
- // Set Enter Global Suspend Mode bit to 1.
- //
- UsbCmd = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
- UsbCmd |= USBCMD_EGSM;
- UhciWriteReg (Uhc->PciIo, USBCMD_OFFSET, UsbCmd);
- break;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
+ default:
+ Status = EFI_INVALID_PARAMETER;
+ break;
}
ON_EXIT:
@@ -289,10 +284,10 @@ Uhci2GetCapability ( OUT UINT8 *Is64BitCapable
)
{
- USB_HC_DEV *Uhc;
- UINT32 Offset;
- UINT16 PortSC;
- UINT32 Index;
+ USB_HC_DEV *Uhc;
+ UINT32 Offset;
+ UINT16 PortSC;
+ UINT32 Index;
Uhc = UHC_FROM_USB2_HC_PROTO (This);
@@ -301,13 +296,13 @@ Uhci2GetCapability ( }
*MaxSpeed = EFI_USB_SPEED_FULL;
- *Is64BitCapable = (UINT8) FALSE;
+ *Is64BitCapable = (UINT8)FALSE;
*PortNumber = 0;
for (Index = 0; Index < USB_MAX_ROOTHUB_PORT; Index++) {
- Offset = USBPORTSC_OFFSET + Index * 2;
- PortSC = UhciReadReg (Uhc->PciIo, Offset);
+ Offset = USBPORTSC_OFFSET + Index * 2;
+ PortSC = UhciReadReg (Uhc->PciIo, Offset);
//
// Port status's bit 7 is reserved and always returns 1 if
@@ -318,6 +313,7 @@ Uhci2GetCapability ( if (((PortSC & 0x80) == 0) || (PortSC == 0xFFFF)) {
break;
}
+
(*PortNumber)++;
}
@@ -327,7 +323,6 @@ Uhci2GetCapability ( return EFI_SUCCESS;
}
-
/**
Retrieves the current status of a USB root hub port according to UEFI 2.0 spec.
@@ -344,14 +339,14 @@ Uhci2GetCapability ( EFI_STATUS
EFIAPI
Uhci2GetRootHubPortStatus (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 PortNumber,
- OUT EFI_USB_PORT_STATUS *PortStatus
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 PortNumber,
+ OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- USB_HC_DEV *Uhc;
- UINT32 Offset;
- UINT16 PortSC;
+ USB_HC_DEV *Uhc;
+ UINT32 Offset;
+ UINT16 PortSC;
Uhc = UHC_FROM_USB2_HC_PROTO (This);
@@ -363,11 +358,11 @@ Uhci2GetRootHubPortStatus ( return EFI_INVALID_PARAMETER;
}
- Offset = USBPORTSC_OFFSET + PortNumber * 2;
- PortStatus->PortStatus = 0;
- PortStatus->PortChangeStatus = 0;
+ Offset = USBPORTSC_OFFSET + PortNumber * 2;
+ PortStatus->PortStatus = 0;
+ PortStatus->PortChangeStatus = 0;
- PortSC = UhciReadReg (Uhc->PciIo, Offset);
+ PortSC = UhciReadReg (Uhc->PciIo, Offset);
if ((PortSC & USBPORTSC_CCS) != 0) {
PortStatus->PortStatus |= USB_PORT_STAT_CONNECTION;
@@ -406,7 +401,6 @@ Uhci2GetRootHubPortStatus ( return EFI_SUCCESS;
}
-
/**
Sets a feature for the specified root hub port according to UEFI 2.0 spec.
@@ -424,16 +418,16 @@ Uhci2GetRootHubPortStatus ( EFI_STATUS
EFIAPI
Uhci2SetRootHubPortFeature (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_HC_DEV *Uhc;
- EFI_TPL OldTpl;
- UINT32 Offset;
- UINT16 PortSC;
- UINT16 Command;
+ USB_HC_DEV *Uhc;
+ EFI_TPL OldTpl;
+ UINT32 Offset;
+ UINT16 PortSC;
+ UINT16 Command;
Uhc = UHC_FROM_USB2_HC_PROTO (This);
@@ -441,42 +435,43 @@ Uhci2SetRootHubPortFeature ( return EFI_INVALID_PARAMETER;
}
- Offset = USBPORTSC_OFFSET + PortNumber * 2;
+ Offset = USBPORTSC_OFFSET + PortNumber * 2;
- OldTpl = gBS->RaiseTPL (UHCI_TPL);
- PortSC = UhciReadReg (Uhc->PciIo, Offset);
+ OldTpl = gBS->RaiseTPL (UHCI_TPL);
+ PortSC = UhciReadReg (Uhc->PciIo, Offset);
switch (PortFeature) {
- case EfiUsbPortSuspend:
- Command = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
- if ((Command & USBCMD_EGSM) == 0) {
- //
- // if global suspend is not active, can set port suspend
- //
- PortSC &= 0xfff5;
- PortSC |= USBPORTSC_SUSP;
- }
- break;
+ case EfiUsbPortSuspend:
+ Command = UhciReadReg (Uhc->PciIo, USBCMD_OFFSET);
+ if ((Command & USBCMD_EGSM) == 0) {
+ //
+ // if global suspend is not active, can set port suspend
+ //
+ PortSC &= 0xfff5;
+ PortSC |= USBPORTSC_SUSP;
+ }
- case EfiUsbPortReset:
- PortSC &= 0xfff5;
- PortSC |= USBPORTSC_PR;
- break;
+ break;
- case EfiUsbPortPower:
- //
- // No action
- //
- break;
+ case EfiUsbPortReset:
+ PortSC &= 0xfff5;
+ PortSC |= USBPORTSC_PR;
+ break;
- case EfiUsbPortEnable:
- PortSC &= 0xfff5;
- PortSC |= USBPORTSC_PED;
- break;
+ case EfiUsbPortPower:
+ //
+ // No action
+ //
+ break;
- default:
- gBS->RestoreTPL (OldTpl);
- return EFI_INVALID_PARAMETER;
+ case EfiUsbPortEnable:
+ PortSC &= 0xfff5;
+ PortSC |= USBPORTSC_PED;
+ break;
+
+ default:
+ gBS->RestoreTPL (OldTpl);
+ return EFI_INVALID_PARAMETER;
}
UhciWriteReg (Uhc->PciIo, Offset, PortSC);
@@ -485,7 +480,6 @@ Uhci2SetRootHubPortFeature ( return EFI_SUCCESS;
}
-
/**
Clears a feature for the specified root hub port according to Uefi 2.0 spec.
@@ -503,15 +497,15 @@ Uhci2SetRootHubPortFeature ( EFI_STATUS
EFIAPI
Uhci2ClearRootHubPortFeature (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_HC_DEV *Uhc;
- EFI_TPL OldTpl;
- UINT32 Offset;
- UINT16 PortSC;
+ USB_HC_DEV *Uhc;
+ EFI_TPL OldTpl;
+ UINT32 Offset;
+ UINT16 PortSC;
Uhc = UHC_FROM_USB2_HC_PROTO (This);
@@ -519,67 +513,67 @@ Uhci2ClearRootHubPortFeature ( return EFI_INVALID_PARAMETER;
}
- Offset = USBPORTSC_OFFSET + PortNumber * 2;
+ Offset = USBPORTSC_OFFSET + PortNumber * 2;
- OldTpl = gBS->RaiseTPL (UHCI_TPL);
- PortSC = UhciReadReg (Uhc->PciIo, Offset);
+ OldTpl = gBS->RaiseTPL (UHCI_TPL);
+ PortSC = UhciReadReg (Uhc->PciIo, Offset);
switch (PortFeature) {
- case EfiUsbPortEnable:
- PortSC &= 0xfff5;
- PortSC &= ~USBPORTSC_PED;
- break;
+ case EfiUsbPortEnable:
+ PortSC &= 0xfff5;
+ PortSC &= ~USBPORTSC_PED;
+ break;
- case EfiUsbPortSuspend:
- //
- // Cause a resume on the specified port if in suspend mode.
- //
- PortSC &= 0xfff5;
- PortSC &= ~USBPORTSC_SUSP;
- break;
+ case EfiUsbPortSuspend:
+ //
+ // Cause a resume on the specified port if in suspend mode.
+ //
+ PortSC &= 0xfff5;
+ PortSC &= ~USBPORTSC_SUSP;
+ break;
- case EfiUsbPortPower:
- //
- // No action
- //
- break;
+ case EfiUsbPortPower:
+ //
+ // No action
+ //
+ break;
- case EfiUsbPortReset:
- PortSC &= 0xfff5;
- PortSC &= ~USBPORTSC_PR;
- break;
+ case EfiUsbPortReset:
+ PortSC &= 0xfff5;
+ PortSC &= ~USBPORTSC_PR;
+ break;
- case EfiUsbPortConnectChange:
- PortSC &= 0xfff5;
- PortSC |= USBPORTSC_CSC;
- break;
+ case EfiUsbPortConnectChange:
+ PortSC &= 0xfff5;
+ PortSC |= USBPORTSC_CSC;
+ break;
- case EfiUsbPortEnableChange:
- PortSC &= 0xfff5;
- PortSC |= USBPORTSC_PEDC;
- break;
+ case EfiUsbPortEnableChange:
+ PortSC &= 0xfff5;
+ PortSC |= USBPORTSC_PEDC;
+ break;
- case EfiUsbPortSuspendChange:
- //
- // Root hub does not support this
- //
- break;
+ case EfiUsbPortSuspendChange:
+ //
+ // Root hub does not support this
+ //
+ break;
- case EfiUsbPortOverCurrentChange:
- //
- // Root hub does not support this
- //
- break;
+ case EfiUsbPortOverCurrentChange:
+ //
+ // Root hub does not support this
+ //
+ break;
- case EfiUsbPortResetChange:
- //
- // Root hub does not support this
- //
- break;
+ case EfiUsbPortResetChange:
+ //
+ // Root hub does not support this
+ //
+ break;
- default:
- gBS->RestoreTPL (OldTpl);
- return EFI_INVALID_PARAMETER;
+ default:
+ gBS->RestoreTPL (OldTpl);
+ return EFI_INVALID_PARAMETER;
}
UhciWriteReg (Uhc->PciIo, Offset, PortSC);
@@ -588,7 +582,6 @@ Uhci2ClearRootHubPortFeature ( return EFI_SUCCESS;
}
-
/**
Submits control transfer to a target USB device according to UEFI 2.0 spec.
@@ -614,45 +607,45 @@ Uhci2ClearRootHubPortFeature ( EFI_STATUS
EFIAPI
Uhci2ControlTransfer (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 DeviceAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN EFI_USB_DATA_DIRECTION TransferDirection,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN UINTN TimeOut,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
- OUT UINT32 *TransferResult
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN EFI_USB_DATA_DIRECTION TransferDirection,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN UINTN TimeOut,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ OUT UINT32 *TransferResult
)
{
- USB_HC_DEV *Uhc;
- UHCI_TD_SW *TDs;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
- UHCI_QH_RESULT QhResult;
- UINT8 PktId;
- UINT8 *RequestPhy;
- VOID *RequestMap;
- UINT8 *DataPhy;
- VOID *DataMap;
- BOOLEAN IsSlowDevice;
- UINTN TransferDataLength;
-
- Uhc = UHC_FROM_USB2_HC_PROTO (This);
- TDs = NULL;
- DataPhy = NULL;
- DataMap = NULL;
- RequestPhy = NULL;
- RequestMap = NULL;
-
- IsSlowDevice = (BOOLEAN) ((EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE);
+ USB_HC_DEV *Uhc;
+ UHCI_TD_SW *TDs;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ UHCI_QH_RESULT QhResult;
+ UINT8 PktId;
+ UINT8 *RequestPhy;
+ VOID *RequestMap;
+ UINT8 *DataPhy;
+ VOID *DataMap;
+ BOOLEAN IsSlowDevice;
+ UINTN TransferDataLength;
+
+ Uhc = UHC_FROM_USB2_HC_PROTO (This);
+ TDs = NULL;
+ DataPhy = NULL;
+ DataMap = NULL;
+ RequestPhy = NULL;
+ RequestMap = NULL;
+
+ IsSlowDevice = (BOOLEAN)((EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE);
//
// Parameters Checking
//
- if (Request == NULL || TransferResult == NULL) {
+ if ((Request == NULL) || (TransferResult == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -661,12 +654,12 @@ Uhci2ControlTransfer ( }
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
- (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {
-
+ (MaximumPacketLength != 32) && (MaximumPacketLength != 64))
+ {
return EFI_INVALID_PARAMETER;
}
- if ((TransferDirection != EfiUsbNoData) && (Data == NULL || DataLength == NULL)) {
+ if ((TransferDirection != EfiUsbNoData) && ((Data == NULL) || (DataLength == NULL))) {
return EFI_INVALID_PARAMETER;
}
@@ -712,12 +705,12 @@ Uhci2ControlTransfer ( Uhc,
DeviceAddress,
PktId,
- (UINT8*)Request,
+ (UINT8 *)Request,
RequestPhy,
- (UINT8*)Data,
+ (UINT8 *)Data,
DataPhy,
TransferDataLength,
- (UINT8) MaximumPacketLength,
+ (UINT8)MaximumPacketLength,
IsSlowDevice
);
@@ -754,7 +747,6 @@ ON_EXIT: return Status;
}
-
/**
Submits bulk transfer to a bulk endpoint of a USB device.
@@ -782,18 +774,18 @@ ON_EXIT: EFI_STATUS
EFIAPI
Uhci2BulkTransfer (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN UINT8 DataBuffersNumber,
- IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
- IN OUT UINTN *DataLength,
- IN OUT UINT8 *DataToggle,
- IN UINTN TimeOut,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
- OUT UINT32 *TransferResult
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN UINT8 DataBuffersNumber,
+ IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
+ IN OUT UINTN *DataLength,
+ IN OUT UINT8 *DataToggle,
+ IN UINTN TimeOut,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ OUT UINT32 *TransferResult
)
{
EFI_USB_DATA_DIRECTION Direction;
@@ -824,7 +816,8 @@ Uhci2BulkTransfer ( }
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
- (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {
+ (MaximumPacketLength != 32) && (MaximumPacketLength != 64))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -869,7 +862,7 @@ Uhci2BulkTransfer ( DataPhy,
*DataLength,
DataToggle,
- (UINT8) MaximumPacketLength,
+ (UINT8)MaximumPacketLength,
FALSE
);
@@ -878,7 +871,6 @@ Uhci2BulkTransfer ( goto ON_EXIT;
}
-
//
// Link the TDs to bulk queue head. According to the platfore
// defintion of UHCI_NO_BW_RECLAMATION, BulkQh is either configured
@@ -904,7 +896,6 @@ ON_EXIT: return Status;
}
-
/**
Submits an asynchronous interrupt transfer to an
interrupt endpoint of a USB device according to UEFI 2.0 spec.
@@ -932,37 +923,37 @@ ON_EXIT: EFI_STATUS
EFIAPI
Uhci2AsyncInterruptTransfer (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN BOOLEAN IsNewTransfer,
- IN OUT UINT8 *DataToggle,
- IN UINTN PollingInterval,
- IN UINTN DataLength,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,
- IN VOID *Context
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN BOOLEAN IsNewTransfer,
+ IN OUT UINT8 *DataToggle,
+ IN UINTN PollingInterval,
+ IN UINTN DataLength,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,
+ IN VOID *Context
)
{
- USB_HC_DEV *Uhc;
- BOOLEAN IsSlowDevice;
- UHCI_QH_SW *Qh;
- UHCI_TD_SW *IntTds;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
- UINT8 *DataPtr;
- UINT8 *DataPhy;
- UINT8 PktId;
-
- Uhc = UHC_FROM_USB2_HC_PROTO (This);
- Qh = NULL;
- IntTds = NULL;
- DataPtr = NULL;
- DataPhy = NULL;
-
- IsSlowDevice = (BOOLEAN) ((EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE);
+ USB_HC_DEV *Uhc;
+ BOOLEAN IsSlowDevice;
+ UHCI_QH_SW *Qh;
+ UHCI_TD_SW *IntTds;
+ EFI_TPL OldTpl;
+ EFI_STATUS Status;
+ UINT8 *DataPtr;
+ UINT8 *DataPhy;
+ UINT8 PktId;
+
+ Uhc = UHC_FROM_USB2_HC_PROTO (This);
+ Qh = NULL;
+ IntTds = NULL;
+ DataPtr = NULL;
+ DataPhy = NULL;
+
+ IsSlowDevice = (BOOLEAN)((EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE);
if ((EndPointAddress & 0x80) == 0) {
return EFI_INVALID_PARAMETER;
@@ -979,7 +970,7 @@ Uhci2AsyncInterruptTransfer ( return Status;
}
- if (PollingInterval < 1 || PollingInterval > 255) {
+ if ((PollingInterval < 1) || (PollingInterval > 255)) {
return EFI_INVALID_PARAMETER;
}
@@ -1016,7 +1007,7 @@ Uhci2AsyncInterruptTransfer ( return EFI_OUT_OF_RESOURCES;
}
- DataPhy = (UINT8 *) (UINTN) UsbHcGetPciAddressForHostMem (Uhc->MemPool, DataPtr, DataLength);
+ DataPhy = (UINT8 *)(UINTN)UsbHcGetPciAddressForHostMem (Uhc->MemPool, DataPtr, DataLength);
OldTpl = gBS->RaiseTPL (UHCI_TPL);
@@ -1036,7 +1027,7 @@ Uhci2AsyncInterruptTransfer ( DataPhy,
DataLength,
DataToggle,
- (UINT8) MaximumPacketLength,
+ (UINT8)MaximumPacketLength,
IsSlowDevice
);
@@ -1113,28 +1104,28 @@ FREE_DATA: EFI_STATUS
EFIAPI
Uhci2SyncInterruptTransfer (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN OUT UINT8 *DataToggle,
- IN UINTN TimeOut,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
- OUT UINT32 *TransferResult
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN OUT UINT8 *DataToggle,
+ IN UINTN TimeOut,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ OUT UINT32 *TransferResult
)
{
- EFI_STATUS Status;
- USB_HC_DEV *Uhc;
- UHCI_TD_SW *TDs;
- UHCI_QH_RESULT QhResult;
- EFI_TPL OldTpl;
- UINT8 *DataPhy;
- VOID *DataMap;
- UINT8 PktId;
- BOOLEAN IsSlowDevice;
+ EFI_STATUS Status;
+ USB_HC_DEV *Uhc;
+ UHCI_TD_SW *TDs;
+ UHCI_QH_RESULT QhResult;
+ EFI_TPL OldTpl;
+ UINT8 *DataPhy;
+ VOID *DataMap;
+ UINT8 PktId;
+ BOOLEAN IsSlowDevice;
Uhc = UHC_FROM_USB2_HC_PROTO (This);
DataPhy = NULL;
@@ -1145,7 +1136,7 @@ Uhci2SyncInterruptTransfer ( return EFI_INVALID_PARAMETER;
}
- IsSlowDevice = (BOOLEAN) ((EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE);
+ IsSlowDevice = (BOOLEAN)((EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE);
if ((DataLength == NULL) || (Data == NULL) || (TransferResult == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -1166,7 +1157,6 @@ Uhci2SyncInterruptTransfer ( *TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
-
UhciAckAllInterrupt (Uhc);
if (!UhciIsHcWorking (Uhc->PciIo)) {
@@ -1202,7 +1192,7 @@ Uhci2SyncInterruptTransfer ( DataPhy,
*DataLength,
DataToggle,
- (UINT8) MaximumPacketLength,
+ (UINT8)MaximumPacketLength,
IsSlowDevice
);
@@ -1213,7 +1203,6 @@ Uhci2SyncInterruptTransfer ( goto ON_EXIT;
}
-
UhciLinkTdToQh (Uhc, Uhc->SyncIntQh, TDs);
Status = UhciExecuteTransfer (Uhc, Uhc->SyncIntQh, TDs, TimeOut, IsSlowDevice, &QhResult);
@@ -1233,7 +1222,6 @@ ON_EXIT: return Status;
}
-
/**
Submits isochronous transfer to a target USB device according to UEFI 2.0 spec.
@@ -1255,22 +1243,21 @@ ON_EXIT: EFI_STATUS
EFIAPI
Uhci2IsochronousTransfer (
- IN EFI_USB2_HC_PROTOCOL *This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN UINT8 DataBuffersNumber,
- IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],
- IN UINTN DataLength,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
- OUT UINT32 *TransferResult
+ IN EFI_USB2_HC_PROTOCOL *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN UINT8 DataBuffersNumber,
+ IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],
+ IN UINTN DataLength,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ OUT UINT32 *TransferResult
)
{
return EFI_UNSUPPORTED;
}
-
/**
Submits Async isochronous transfer to a target USB device according to UEFI 2.0 spec.
@@ -1322,8 +1309,8 @@ Uhci2AsyncIsochronousTransfer ( EFI_STATUS
EFIAPI
UhciDriverEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
return EfiLibInstallDriverBindingComponentName2 (
@@ -1336,7 +1323,6 @@ UhciDriverEntryPoint ( );
}
-
/**
Test to see if this driver supports ControllerHandle. Any
ControllerHandle that has UsbHcProtocol installed will be supported.
@@ -1352,15 +1338,15 @@ UhciDriverEntryPoint ( EFI_STATUS
EFIAPI
UhciDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS OpenStatus;
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- USB_CLASSC UsbClassCReg;
+ EFI_STATUS OpenStatus;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ USB_CLASSC UsbClassCReg;
//
// Test whether there is PCI IO Protocol attached on the controller handle.
@@ -1368,7 +1354,7 @@ UhciDriverBindingSupported ( OpenStatus = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1397,8 +1383,8 @@ UhciDriverBindingSupported ( if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||
(UsbClassCReg.ProgInterface != PCI_IF_UHCI)
- ) {
-
+ )
+ {
Status = EFI_UNSUPPORTED;
}
@@ -1411,10 +1397,8 @@ ON_EXIT: );
return Status;
-
}
-
/**
Allocate and initialize the empty UHCI device.
@@ -1445,22 +1429,22 @@ UhciAllocateDev ( // This driver supports both USB_HC_PROTOCOL and USB2_HC_PROTOCOL.
// USB_HC_PROTOCOL is for EFI 1.1 backward compability.
//
- Uhc->Signature = USB_HC_DEV_SIGNATURE;
- Uhc->Usb2Hc.GetCapability = Uhci2GetCapability;
- Uhc->Usb2Hc.Reset = Uhci2Reset;
- Uhc->Usb2Hc.GetState = Uhci2GetState;
- Uhc->Usb2Hc.SetState = Uhci2SetState;
- Uhc->Usb2Hc.ControlTransfer = Uhci2ControlTransfer;
- Uhc->Usb2Hc.BulkTransfer = Uhci2BulkTransfer;
- Uhc->Usb2Hc.AsyncInterruptTransfer = Uhci2AsyncInterruptTransfer;
- Uhc->Usb2Hc.SyncInterruptTransfer = Uhci2SyncInterruptTransfer;
- Uhc->Usb2Hc.IsochronousTransfer = Uhci2IsochronousTransfer;
- Uhc->Usb2Hc.AsyncIsochronousTransfer = Uhci2AsyncIsochronousTransfer;
- Uhc->Usb2Hc.GetRootHubPortStatus = Uhci2GetRootHubPortStatus;
- Uhc->Usb2Hc.SetRootHubPortFeature = Uhci2SetRootHubPortFeature;
- Uhc->Usb2Hc.ClearRootHubPortFeature = Uhci2ClearRootHubPortFeature;
- Uhc->Usb2Hc.MajorRevision = 0x1;
- Uhc->Usb2Hc.MinorRevision = 0x1;
+ Uhc->Signature = USB_HC_DEV_SIGNATURE;
+ Uhc->Usb2Hc.GetCapability = Uhci2GetCapability;
+ Uhc->Usb2Hc.Reset = Uhci2Reset;
+ Uhc->Usb2Hc.GetState = Uhci2GetState;
+ Uhc->Usb2Hc.SetState = Uhci2SetState;
+ Uhc->Usb2Hc.ControlTransfer = Uhci2ControlTransfer;
+ Uhc->Usb2Hc.BulkTransfer = Uhci2BulkTransfer;
+ Uhc->Usb2Hc.AsyncInterruptTransfer = Uhci2AsyncInterruptTransfer;
+ Uhc->Usb2Hc.SyncInterruptTransfer = Uhci2SyncInterruptTransfer;
+ Uhc->Usb2Hc.IsochronousTransfer = Uhci2IsochronousTransfer;
+ Uhc->Usb2Hc.AsyncIsochronousTransfer = Uhci2AsyncIsochronousTransfer;
+ Uhc->Usb2Hc.GetRootHubPortStatus = Uhci2GetRootHubPortStatus;
+ Uhc->Usb2Hc.SetRootHubPortFeature = Uhci2SetRootHubPortFeature;
+ Uhc->Usb2Hc.ClearRootHubPortFeature = Uhci2ClearRootHubPortFeature;
+ Uhc->Usb2Hc.MajorRevision = 0x1;
+ Uhc->Usb2Hc.MinorRevision = 0x1;
Uhc->PciIo = PciIo;
Uhc->DevicePath = DevicePath;
@@ -1494,7 +1478,6 @@ ON_ERROR: return NULL;
}
-
/**
Free the UHCI device and release its associated resources.
@@ -1503,7 +1486,7 @@ ON_ERROR: **/
VOID
UhciFreeDev (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
)
{
if (Uhc->AsyncIntMonitor != NULL) {
@@ -1525,7 +1508,6 @@ UhciFreeDev ( FreePool (Uhc);
}
-
/**
Uninstall all Uhci Interface.
@@ -1535,26 +1517,25 @@ UhciFreeDev ( **/
VOID
UhciCleanDevUp (
- IN EFI_HANDLE Controller,
- IN EFI_USB2_HC_PROTOCOL *This
+ IN EFI_HANDLE Controller,
+ IN EFI_USB2_HC_PROTOCOL *This
)
{
- USB_HC_DEV *Uhc;
- EFI_STATUS Status;
+ USB_HC_DEV *Uhc;
+ EFI_STATUS Status;
//
// Uninstall the USB_HC and USB_HC2 protocol, then disable the controller
//
Uhc = UHC_FROM_USB2_HC_PROTO (This);
-
Status = gBS->UninstallProtocolInterface (
Controller,
&gEfiUsb2HcProtocolGuid,
&Uhc->Usb2Hc
);
if (EFI_ERROR (Status)) {
- return ;
+ return;
}
UhciStopHc (Uhc, UHC_GENERIC_TIMEOUT);
@@ -1565,11 +1546,11 @@ UhciCleanDevUp ( // Restore original PCI attributes
//
Uhc->PciIo->Attributes (
- Uhc->PciIo,
- EfiPciIoAttributeOperationSet,
- Uhc->OriginalPciAttributes,
- NULL
- );
+ Uhc->PciIo,
+ EfiPciIoAttributeOperationSet,
+ Uhc->OriginalPciAttributes,
+ NULL
+ );
UhciFreeDev (Uhc);
}
@@ -1584,13 +1565,13 @@ UhciCleanDevUp ( VOID
EFIAPI
UhcExitBootService (
- EFI_EVENT Event,
- VOID *Context
+ EFI_EVENT Event,
+ VOID *Context
)
{
- USB_HC_DEV *Uhc;
+ USB_HC_DEV *Uhc;
- Uhc = (USB_HC_DEV *) Context;
+ Uhc = (USB_HC_DEV *)Context;
//
// Stop the Host Controller
@@ -1620,27 +1601,27 @@ UhcExitBootService ( EFI_STATUS
EFIAPI
UhciDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- USB_HC_DEV *Uhc;
- UINT64 Supports;
- UINT64 OriginalPciAttributes;
- BOOLEAN PciAttributesSaved;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ USB_HC_DEV *Uhc;
+ UINT64 Supports;
+ UINT64 OriginalPciAttributes;
+ BOOLEAN PciAttributesSaved;
EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;
//
// Open PCIIO, then enable the EHC device and turn off emulation
//
- Uhc = NULL;
+ Uhc = NULL;
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1654,14 +1635,14 @@ UhciDriverBindingStart ( // Open Device Path Protocol for on USB host controller
//
HcDevicePath = NULL;
- Status = gBS->OpenProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- (VOID **) &HcDevicePath,
- This->DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL
- );
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&HcDevicePath,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
PciAttributesSaved = FALSE;
//
@@ -1677,6 +1658,7 @@ UhciDriverBindingStart ( if (EFI_ERROR (Status)) {
goto CLOSE_PCIIO;
}
+
PciAttributesSaved = TRUE;
//
@@ -1695,12 +1677,12 @@ UhciDriverBindingStart ( );
if (!EFI_ERROR (Status)) {
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
- Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
}
if (EFI_ERROR (Status)) {
@@ -1783,7 +1765,6 @@ UhciDriverBindingStart ( FALSE
);
-
//
// Start the UHCI hardware, also set its reclamation point to 64 bytes
//
@@ -1808,24 +1789,23 @@ CLOSE_PCIIO: // Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ OriginalPciAttributes,
+ NULL
+ );
}
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
return Status;
}
-
/**
Stop this driver on ControllerHandle. Support stopping any child handles
created by this driver.
@@ -1842,19 +1822,19 @@ CLOSE_PCIIO: EFI_STATUS
EFIAPI
UhciDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_USB2_HC_PROTOCOL *Usb2Hc;
EFI_STATUS Status;
- Status = gBS->OpenProtocol (
+ Status = gBS->OpenProtocol (
Controller,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -1872,11 +1852,11 @@ UhciDriverBindingStop ( UhciCleanDevUp (Controller, Usb2Hc);
gBS->CloseProtocol (
- Controller,
- &gEfiPciIoProtocolGuid,
- This->DriverBindingHandle,
- Controller
- );
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
return EFI_SUCCESS;
}
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h index 882f5e55ea..138623ed6b 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_UHCI_H_
#define _EFI_UHCI_H_
-
#include <Uefi.h>
#include <Protocol/Usb2HostController.h>
@@ -31,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <IndustryStandard/Pci.h>
-typedef struct _USB_HC_DEV USB_HC_DEV;
+typedef struct _USB_HC_DEV USB_HC_DEV;
#include "UsbHcMem.h"
#include "UhciQueue.h"
@@ -44,20 +43,20 @@ typedef struct _USB_HC_DEV USB_HC_DEV; // UHC timeout experience values
//
-#define UHC_1_MICROSECOND 1
-#define UHC_1_MILLISECOND (1000 * UHC_1_MICROSECOND)
-#define UHC_1_SECOND (1000 * UHC_1_MILLISECOND)
+#define UHC_1_MICROSECOND 1
+#define UHC_1_MILLISECOND (1000 * UHC_1_MICROSECOND)
+#define UHC_1_SECOND (1000 * UHC_1_MILLISECOND)
//
// UHCI register operation timeout, set by experience
//
-#define UHC_GENERIC_TIMEOUT UHC_1_SECOND
+#define UHC_GENERIC_TIMEOUT UHC_1_SECOND
//
// Wait for force global resume(FGR) complete, refers to
// specification[UHCI11-2.1.1]
//
-#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)
+#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)
//
// Wait for roothub port reset and recovery, reset stall
@@ -71,22 +70,22 @@ typedef struct _USB_HC_DEV USB_HC_DEV; // Sync and Async transfer polling interval, set by experience,
// and the unit of Async is 100us.
//
-#define UHC_SYNC_POLL_INTERVAL (1 * UHC_1_MILLISECOND)
-#define UHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
+#define UHC_SYNC_POLL_INTERVAL (1 * UHC_1_MILLISECOND)
+#define UHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// UHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
-#define UHCI_TPL TPL_NOTIFY
+#define UHCI_TPL TPL_NOTIFY
-#define USB_HC_DEV_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'i')
+#define USB_HC_DEV_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'i')
#pragma pack(1)
typedef struct {
- UINT8 ProgInterface;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 ProgInterface;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
@@ -104,20 +103,20 @@ typedef struct { // device requires this bandwidth reclamation capability.
//
struct _USB_HC_DEV {
- UINT32 Signature;
- EFI_USB2_HC_PROTOCOL Usb2Hc;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- UINT64 OriginalPciAttributes;
+ UINT32 Signature;
+ EFI_USB2_HC_PROTOCOL Usb2Hc;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINT64 OriginalPciAttributes;
//
// Schedule data structures
//
- UINT32 *FrameBase; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
- UINT32 *FrameBaseHostAddr; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
- UHCI_QH_SW *SyncIntQh;
- UHCI_QH_SW *CtrlQh;
- UHCI_QH_SW *BulkQh;
+ UINT32 *FrameBase; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.
+ UINT32 *FrameBaseHostAddr; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.
+ UHCI_QH_SW *SyncIntQh;
+ UHCI_QH_SW *CtrlQh;
+ UHCI_QH_SW *BulkQh;
//
// Structures to maintain asynchronus interrupt transfers.
@@ -127,22 +126,21 @@ struct _USB_HC_DEV { // released in two steps using Recycle and RecycleWait.
// Check the asynchronous interrupt management routines.
//
- LIST_ENTRY AsyncIntList;
- EFI_EVENT AsyncIntMonitor;
- UHCI_ASYNC_REQUEST *Recycle;
- UHCI_ASYNC_REQUEST *RecycleWait;
-
+ LIST_ENTRY AsyncIntList;
+ EFI_EVENT AsyncIntMonitor;
+ UHCI_ASYNC_REQUEST *Recycle;
+ UHCI_ASYNC_REQUEST *RecycleWait;
- UINTN RootPorts;
- USBHC_MEM_POOL *MemPool;
- EFI_UNICODE_STRING_TABLE *CtrlNameTable;
- VOID *FrameMapping;
+ UINTN RootPorts;
+ USBHC_MEM_POOL *MemPool;
+ EFI_UNICODE_STRING_TABLE *CtrlNameTable;
+ VOID *FrameMapping;
//
// ExitBootServicesEvent is used to stop the EHC DMA operation
// after exit boot service.
//
- EFI_EVENT ExitBootServiceEvent;
+ EFI_EVENT ExitBootServiceEvent;
};
extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;
@@ -164,9 +162,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2; EFI_STATUS
EFIAPI
UhciDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -185,9 +183,9 @@ UhciDriverBindingSupported ( EFI_STATUS
EFIAPI
UhciDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -206,10 +204,10 @@ UhciDriverBindingStart ( EFI_STATUS
EFIAPI
UhciDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.c index 3d499c9baf..3dc27eff1a 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.c @@ -17,7 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
UhciDumpQh (
- IN UHCI_QH_SW *QhSw
+ IN UHCI_QH_SW *QhSw
)
{
DEBUG ((DEBUG_VERBOSE, "&QhSw @ 0x%p\n", QhSw));
@@ -28,7 +28,6 @@ UhciDumpQh ( DEBUG ((DEBUG_VERBOSE, " Vertical Link - %x\n\n", QhSw->QhHw.VerticalLink));
}
-
/**
Dump the content of TD structure.
@@ -37,33 +36,33 @@ UhciDumpQh ( **/
VOID
UhciDumpTds (
- IN UHCI_TD_SW *TdSw
+ IN UHCI_TD_SW *TdSw
)
{
- UHCI_TD_SW *CurTdSw;
+ UHCI_TD_SW *CurTdSw;
CurTdSw = TdSw;
while (CurTdSw != NULL) {
- DEBUG ((DEBUG_VERBOSE, "TdSw @ 0x%p\n", CurTdSw));
- DEBUG ((DEBUG_VERBOSE, "TdSw.NextTd - 0x%p\n", CurTdSw->NextTd));
- DEBUG ((DEBUG_VERBOSE, "TdSw.DataLen - %d\n", CurTdSw->DataLen));
- DEBUG ((DEBUG_VERBOSE, "TdSw.Data - 0x%p\n", CurTdSw->Data));
+ DEBUG ((DEBUG_VERBOSE, "TdSw @ 0x%p\n", CurTdSw));
+ DEBUG ((DEBUG_VERBOSE, "TdSw.NextTd - 0x%p\n", CurTdSw->NextTd));
+ DEBUG ((DEBUG_VERBOSE, "TdSw.DataLen - %d\n", CurTdSw->DataLen));
+ DEBUG ((DEBUG_VERBOSE, "TdSw.Data - 0x%p\n", CurTdSw->Data));
DEBUG ((DEBUG_VERBOSE, "TdHw:\n"));
- DEBUG ((DEBUG_VERBOSE, " NextLink - 0x%x\n", CurTdSw->TdHw.NextLink));
- DEBUG ((DEBUG_VERBOSE, " ActualLen - %d\n", CurTdSw->TdHw.ActualLen));
- DEBUG ((DEBUG_VERBOSE, " Status - 0x%x\n", CurTdSw->TdHw.Status));
- DEBUG ((DEBUG_VERBOSE, " IOC - %d\n", CurTdSw->TdHw.IntOnCpl));
- DEBUG ((DEBUG_VERBOSE, " IsIsoCh - %d\n", CurTdSw->TdHw.IsIsoch));
- DEBUG ((DEBUG_VERBOSE, " LowSpeed - %d\n", CurTdSw->TdHw.LowSpeed));
- DEBUG ((DEBUG_VERBOSE, " ErrorCount - %d\n", CurTdSw->TdHw.ErrorCount));
- DEBUG ((DEBUG_VERBOSE, " ShortPacket - %d\n", CurTdSw->TdHw.ShortPacket));
- DEBUG ((DEBUG_VERBOSE, " PidCode - 0x%x\n", CurTdSw->TdHw.PidCode));
- DEBUG ((DEBUG_VERBOSE, " DevAddr - %d\n", CurTdSw->TdHw.DeviceAddr));
- DEBUG ((DEBUG_VERBOSE, " EndPoint - %d\n", CurTdSw->TdHw.EndPoint));
- DEBUG ((DEBUG_VERBOSE, " DataToggle - %d\n", CurTdSw->TdHw.DataToggle));
- DEBUG ((DEBUG_VERBOSE, " MaxPacketLen - %d\n", CurTdSw->TdHw.MaxPacketLen));
- DEBUG ((DEBUG_VERBOSE, " DataBuffer - 0x%x\n\n",CurTdSw->TdHw.DataBuffer));
+ DEBUG ((DEBUG_VERBOSE, " NextLink - 0x%x\n", CurTdSw->TdHw.NextLink));
+ DEBUG ((DEBUG_VERBOSE, " ActualLen - %d\n", CurTdSw->TdHw.ActualLen));
+ DEBUG ((DEBUG_VERBOSE, " Status - 0x%x\n", CurTdSw->TdHw.Status));
+ DEBUG ((DEBUG_VERBOSE, " IOC - %d\n", CurTdSw->TdHw.IntOnCpl));
+ DEBUG ((DEBUG_VERBOSE, " IsIsoCh - %d\n", CurTdSw->TdHw.IsIsoch));
+ DEBUG ((DEBUG_VERBOSE, " LowSpeed - %d\n", CurTdSw->TdHw.LowSpeed));
+ DEBUG ((DEBUG_VERBOSE, " ErrorCount - %d\n", CurTdSw->TdHw.ErrorCount));
+ DEBUG ((DEBUG_VERBOSE, " ShortPacket - %d\n", CurTdSw->TdHw.ShortPacket));
+ DEBUG ((DEBUG_VERBOSE, " PidCode - 0x%x\n", CurTdSw->TdHw.PidCode));
+ DEBUG ((DEBUG_VERBOSE, " DevAddr - %d\n", CurTdSw->TdHw.DeviceAddr));
+ DEBUG ((DEBUG_VERBOSE, " EndPoint - %d\n", CurTdSw->TdHw.EndPoint));
+ DEBUG ((DEBUG_VERBOSE, " DataToggle - %d\n", CurTdSw->TdHw.DataToggle));
+ DEBUG ((DEBUG_VERBOSE, " MaxPacketLen - %d\n", CurTdSw->TdHw.MaxPacketLen));
+ DEBUG ((DEBUG_VERBOSE, " DataBuffer - 0x%x\n\n", CurTdSw->TdHw.DataBuffer));
CurTdSw = CurTdSw->NextTd;
}
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.h index 34f8ea1ff4..27a2ec51a0 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciDebug.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_UHCI_DEBUG_H_
#define _EFI_UHCI_DEBUG_H_
-
/**
Dump the content of QH structure.
@@ -21,10 +20,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
UhciDumpQh (
- IN UHCI_QH_SW *QhSw
+ IN UHCI_QH_SW *QhSw
);
-
/**
Dump the content of TD structure.
@@ -35,7 +33,7 @@ UhciDumpQh ( **/
VOID
UhciDumpTds (
- IN UHCI_TD_SW *TdSw
+ IN UHCI_TD_SW *TdSw
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c index fb97326dc0..bd9703dd13 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c @@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Uhci.h"
-
/**
Map address of request structure buffer.
@@ -24,10 +23,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
UhciMapUserRequest (
- IN USB_HC_DEV *Uhc,
- IN OUT VOID *Request,
- OUT UINT8 **MappedAddr,
- OUT VOID **Map
+ IN USB_HC_DEV *Uhc,
+ IN OUT VOID *Request,
+ OUT UINT8 **MappedAddr,
+ OUT VOID **Map
)
{
EFI_STATUS Status;
@@ -45,13 +44,12 @@ UhciMapUserRequest ( );
if (!EFI_ERROR (Status)) {
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;
}
return Status;
}
-
/**
Map address of user data buffer.
@@ -84,65 +82,64 @@ UhciMapUserData ( Status = EFI_SUCCESS;
switch (Direction) {
- case EfiUsbDataIn:
- //
- // BusMasterWrite means cpu read
- //
- *PktId = INPUT_PACKET_ID;
- Status = Uhc->PciIo->Map (
- Uhc->PciIo,
- EfiPciIoOperationBusMasterWrite,
- Data,
- Len,
- &PhyAddr,
- Map
- );
-
- if (EFI_ERROR (Status)) {
- goto EXIT;
- }
-
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;
- break;
-
- case EfiUsbDataOut:
- *PktId = OUTPUT_PACKET_ID;
- Status = Uhc->PciIo->Map (
- Uhc->PciIo,
- EfiPciIoOperationBusMasterRead,
- Data,
- Len,
- &PhyAddr,
- Map
- );
-
- if (EFI_ERROR (Status)) {
- goto EXIT;
- }
-
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;
- break;
-
- case EfiUsbNoData:
- if ((Len != NULL) && (*Len != 0)) {
- Status = EFI_INVALID_PARAMETER;
- goto EXIT;
- }
-
- *PktId = OUTPUT_PACKET_ID;
- *MappedAddr = NULL;
- *Map = NULL;
- break;
-
- default:
- Status = EFI_INVALID_PARAMETER;
+ case EfiUsbDataIn:
+ //
+ // BusMasterWrite means cpu read
+ //
+ *PktId = INPUT_PACKET_ID;
+ Status = Uhc->PciIo->Map (
+ Uhc->PciIo,
+ EfiPciIoOperationBusMasterWrite,
+ Data,
+ Len,
+ &PhyAddr,
+ Map
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;
+ break;
+
+ case EfiUsbDataOut:
+ *PktId = OUTPUT_PACKET_ID;
+ Status = Uhc->PciIo->Map (
+ Uhc->PciIo,
+ EfiPciIoOperationBusMasterRead,
+ Data,
+ Len,
+ &PhyAddr,
+ Map
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;
+ break;
+
+ case EfiUsbNoData:
+ if ((Len != NULL) && (*Len != 0)) {
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+
+ *PktId = OUTPUT_PACKET_ID;
+ *MappedAddr = NULL;
+ *Map = NULL;
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
EXIT:
return Status;
}
-
/**
Link the TD To QH.
@@ -153,9 +150,9 @@ EXIT: **/
VOID
UhciLinkTdToQh (
- IN USB_HC_DEV *Uhc,
- IN UHCI_QH_SW *Qh,
- IN UHCI_TD_SW *Td
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_QH_SW *Qh,
+ IN UHCI_TD_SW *Td
)
{
EFI_PHYSICAL_ADDRESS PhyAddr;
@@ -165,10 +162,9 @@ UhciLinkTdToQh ( ASSERT ((Qh != NULL) && (Td != NULL));
Qh->QhHw.VerticalLink = QH_VLINK (PhyAddr, FALSE);
- Qh->TDs = (VOID *) Td;
+ Qh->TDs = (VOID *)Td;
}
-
/**
Unlink TD from the QH.
@@ -178,8 +174,8 @@ UhciLinkTdToQh ( **/
VOID
UhciUnlinkTdFromQh (
- IN UHCI_QH_SW *Qh,
- IN UHCI_TD_SW *Td
+ IN UHCI_QH_SW *Qh,
+ IN UHCI_TD_SW *Td
)
{
ASSERT ((Qh != NULL) && (Td != NULL));
@@ -188,7 +184,6 @@ UhciUnlinkTdFromQh ( Qh->TDs = NULL;
}
-
/**
Append a new TD To the previous TD.
@@ -199,9 +194,9 @@ UhciUnlinkTdFromQh ( **/
VOID
UhciAppendTd (
- IN USB_HC_DEV *Uhc,
- IN UHCI_TD_SW *PrevTd,
- IN UHCI_TD_SW *ThisTd
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_TD_SW *PrevTd,
+ IN UHCI_TD_SW *ThisTd
)
{
EFI_PHYSICAL_ADDRESS PhyAddr;
@@ -211,10 +206,9 @@ UhciAppendTd ( ASSERT ((PrevTd != NULL) && (ThisTd != NULL));
PrevTd->TdHw.NextLink = TD_LINK (PhyAddr, TRUE, FALSE);
- PrevTd->NextTd = (VOID *) ThisTd;
+ PrevTd->NextTd = (VOID *)ThisTd;
}
-
/**
Delete a list of TDs.
@@ -226,23 +220,22 @@ UhciAppendTd ( **/
VOID
UhciDestoryTds (
- IN USB_HC_DEV *Uhc,
- IN UHCI_TD_SW *FirstTd
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_TD_SW *FirstTd
)
{
- UHCI_TD_SW *NextTd;
- UHCI_TD_SW *ThisTd;
+ UHCI_TD_SW *NextTd;
+ UHCI_TD_SW *ThisTd;
NextTd = FirstTd;
while (NextTd != NULL) {
- ThisTd = NextTd;
- NextTd = ThisTd->NextTd;
+ ThisTd = NextTd;
+ NextTd = ThisTd->NextTd;
UsbHcFreeMem (Uhc->MemPool, ThisTd, sizeof (UHCI_TD_SW));
}
}
-
/**
Create an initialize a new queue head.
@@ -254,11 +247,11 @@ UhciDestoryTds ( **/
UHCI_QH_SW *
UhciCreateQh (
- IN USB_HC_DEV *Uhc,
- IN UINTN Interval
+ IN USB_HC_DEV *Uhc,
+ IN UINTN Interval
)
{
- UHCI_QH_SW *Qh;
+ UHCI_QH_SW *Qh;
Qh = UsbHcAllocateMem (Uhc->MemPool, sizeof (UHCI_QH_SW));
@@ -268,14 +261,13 @@ UhciCreateQh ( Qh->QhHw.HorizonLink = QH_HLINK (NULL, TRUE);
Qh->QhHw.VerticalLink = QH_VLINK (NULL, TRUE);
- Qh->Interval = UhciConvertPollRate(Interval);
+ Qh->Interval = UhciConvertPollRate (Interval);
Qh->TDs = NULL;
Qh->NextQh = NULL;
return Qh;
}
-
/**
Create and intialize a TD.
@@ -286,12 +278,12 @@ UhciCreateQh ( **/
UHCI_TD_SW *
UhciCreateTd (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
)
{
- UHCI_TD_SW *Td;
+ UHCI_TD_SW *Td;
- Td = UsbHcAllocateMem (Uhc->MemPool, sizeof (UHCI_TD_SW));
+ Td = UsbHcAllocateMem (Uhc->MemPool, sizeof (UHCI_TD_SW));
if (Td == NULL) {
return NULL;
}
@@ -304,7 +296,6 @@ UhciCreateTd ( return Td;
}
-
/**
Create and initialize a TD for Setup Stage of a control transfer.
@@ -319,14 +310,14 @@ UhciCreateTd ( **/
UHCI_TD_SW *
UhciCreateSetupTd (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DevAddr,
- IN UINT8 *Request,
- IN UINT8 *RequestPhy,
- IN BOOLEAN IsLow
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DevAddr,
+ IN UINT8 *Request,
+ IN UINT8 *RequestPhy,
+ IN BOOLEAN IsLow
)
{
- UHCI_TD_SW *Td;
+ UHCI_TD_SW *Td;
Td = UhciCreateTd (Uhc);
@@ -344,17 +335,16 @@ UhciCreateSetupTd ( Td->TdHw.EndPoint = 0;
Td->TdHw.LowSpeed = IsLow ? 1 : 0;
Td->TdHw.DeviceAddr = DevAddr & 0x7F;
- Td->TdHw.MaxPacketLen = (UINT32) (sizeof (EFI_USB_DEVICE_REQUEST) - 1);
+ Td->TdHw.MaxPacketLen = (UINT32)(sizeof (EFI_USB_DEVICE_REQUEST) - 1);
Td->TdHw.PidCode = SETUP_PACKET_ID;
- Td->TdHw.DataBuffer = (UINT32) (UINTN) RequestPhy;
+ Td->TdHw.DataBuffer = (UINT32)(UINTN)RequestPhy;
- Td->Data = Request;
- Td->DataLen = (UINT16) sizeof (EFI_USB_DEVICE_REQUEST);
+ Td->Data = Request;
+ Td->DataLen = (UINT16)sizeof (EFI_USB_DEVICE_REQUEST);
return Td;
}
-
/**
Create a TD for data.
@@ -373,15 +363,15 @@ UhciCreateSetupTd ( **/
UHCI_TD_SW *
UhciCreateDataTd (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DevAddr,
- IN UINT8 Endpoint,
- IN UINT8 *DataPtr,
- IN UINT8 *DataPhyPtr,
- IN UINTN Len,
- IN UINT8 PktId,
- IN UINT8 Toggle,
- IN BOOLEAN IsLow
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DevAddr,
+ IN UINT8 Endpoint,
+ IN UINT8 *DataPtr,
+ IN UINT8 *DataPhyPtr,
+ IN UINTN Len,
+ IN UINT8 PktId,
+ IN UINT8 Toggle,
+ IN BOOLEAN IsLow
)
{
UHCI_TD_SW *Td;
@@ -391,7 +381,7 @@ UhciCreateDataTd ( //
ASSERT (Len <= 0x500);
- Td = UhciCreateTd (Uhc);
+ Td = UhciCreateTd (Uhc);
if (Td == NULL) {
return NULL;
@@ -407,17 +397,16 @@ UhciCreateDataTd ( Td->TdHw.DataToggle = Toggle & 0x01;
Td->TdHw.EndPoint = Endpoint & 0x0F;
Td->TdHw.DeviceAddr = DevAddr & 0x7F;
- Td->TdHw.MaxPacketLen = (UINT32) (Len - 1);
- Td->TdHw.PidCode = (UINT8) PktId;
- Td->TdHw.DataBuffer = (UINT32) (UINTN) DataPhyPtr;
+ Td->TdHw.MaxPacketLen = (UINT32)(Len - 1);
+ Td->TdHw.PidCode = (UINT8)PktId;
+ Td->TdHw.DataBuffer = (UINT32)(UINTN)DataPhyPtr;
- Td->Data = DataPtr;
- Td->DataLen = (UINT16) Len;
+ Td->Data = DataPtr;
+ Td->DataLen = (UINT16)Len;
return Td;
}
-
/**
Create TD for the Status Stage of control transfer.
@@ -431,13 +420,13 @@ UhciCreateDataTd ( **/
UHCI_TD_SW *
UhciCreateStatusTd (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DevAddr,
- IN UINT8 PktId,
- IN BOOLEAN IsLow
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DevAddr,
+ IN UINT8 PktId,
+ IN BOOLEAN IsLow
)
{
- UHCI_TD_SW *Td;
+ UHCI_TD_SW *Td;
Td = UhciCreateTd (Uhc);
@@ -451,21 +440,20 @@ UhciCreateStatusTd ( Td->TdHw.IntOnCpl = FALSE;
Td->TdHw.ErrorCount = 0x03;
Td->TdHw.Status |= USBTD_ACTIVE;
- Td->TdHw.MaxPacketLen = 0x7FF; //0x7FF: there is no data (refer to UHCI spec)
+ Td->TdHw.MaxPacketLen = 0x7FF; // 0x7FF: there is no data (refer to UHCI spec)
Td->TdHw.DataToggle = 1;
Td->TdHw.EndPoint = 0;
Td->TdHw.LowSpeed = IsLow ? 1 : 0;
Td->TdHw.DeviceAddr = DevAddr & 0x7F;
- Td->TdHw.PidCode = (UINT8) PktId;
- Td->TdHw.DataBuffer = (UINT32) (UINTN) NULL;
+ Td->TdHw.PidCode = (UINT8)PktId;
+ Td->TdHw.DataBuffer = (UINT32)(UINTN)NULL;
- Td->Data = NULL;
- Td->DataLen = 0;
+ Td->Data = NULL;
+ Td->DataLen = 0;
return Td;
}
-
/**
Create Tds list for Control Transfer.
@@ -485,27 +473,26 @@ UhciCreateStatusTd ( **/
UHCI_TD_SW *
UhciCreateCtrlTds (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DeviceAddr,
- IN UINT8 DataPktId,
- IN UINT8 *Request,
- IN UINT8 *RequestPhy,
- IN UINT8 *Data,
- IN UINT8 *DataPhy,
- IN UINTN DataLen,
- IN UINT8 MaxPacket,
- IN BOOLEAN IsLow
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DeviceAddr,
+ IN UINT8 DataPktId,
+ IN UINT8 *Request,
+ IN UINT8 *RequestPhy,
+ IN UINT8 *Data,
+ IN UINT8 *DataPhy,
+ IN UINTN DataLen,
+ IN UINT8 MaxPacket,
+ IN BOOLEAN IsLow
)
{
- UHCI_TD_SW *SetupTd;
- UHCI_TD_SW *FirstDataTd;
- UHCI_TD_SW *DataTd;
- UHCI_TD_SW *PrevDataTd;
- UHCI_TD_SW *StatusTd;
- UINT8 DataToggle;
- UINT8 StatusPktId;
- UINTN ThisTdLen;
-
+ UHCI_TD_SW *SetupTd;
+ UHCI_TD_SW *FirstDataTd;
+ UHCI_TD_SW *DataTd;
+ UHCI_TD_SW *PrevDataTd;
+ UHCI_TD_SW *StatusTd;
+ UINT8 DataToggle;
+ UINT8 StatusPktId;
+ UINTN ThisTdLen;
DataTd = NULL;
SetupTd = NULL;
@@ -537,8 +524,8 @@ UhciCreateCtrlTds ( Uhc,
DeviceAddr,
0,
- Data, //cpu memory address
- DataPhy, //Pci memory address
+ Data, // cpu memory address
+ DataPhy, // Pci memory address
ThisTdLen,
DataPktId,
DataToggle,
@@ -557,10 +544,10 @@ UhciCreateCtrlTds ( }
DataToggle ^= 1;
- PrevDataTd = DataTd;
- Data += ThisTdLen;
- DataPhy += ThisTdLen;
- DataLen -= ThisTdLen;
+ PrevDataTd = DataTd;
+ Data += ThisTdLen;
+ DataPhy += ThisTdLen;
+ DataLen -= ThisTdLen;
}
//
@@ -602,7 +589,6 @@ FREE_TD: return NULL;
}
-
/**
Create Tds list for Bulk/Interrupt Transfer.
@@ -622,22 +608,22 @@ FREE_TD: **/
UHCI_TD_SW *
UhciCreateBulkOrIntTds (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DevAddr,
- IN UINT8 EndPoint,
- IN UINT8 PktId,
- IN UINT8 *Data,
- IN UINT8 *DataPhy,
- IN UINTN DataLen,
- IN OUT UINT8 *DataToggle,
- IN UINT8 MaxPacket,
- IN BOOLEAN IsLow
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EndPoint,
+ IN UINT8 PktId,
+ IN UINT8 *Data,
+ IN UINT8 *DataPhy,
+ IN UINTN DataLen,
+ IN OUT UINT8 *DataToggle,
+ IN UINT8 MaxPacket,
+ IN BOOLEAN IsLow
)
{
- UHCI_TD_SW *DataTd;
- UHCI_TD_SW *FirstDataTd;
- UHCI_TD_SW *PrevDataTd;
- UINTN ThisTdLen;
+ UHCI_TD_SW *DataTd;
+ UHCI_TD_SW *FirstDataTd;
+ UHCI_TD_SW *PrevDataTd;
+ UINTN ThisTdLen;
DataTd = NULL;
FirstDataTd = NULL;
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h index 594ea28ee8..a0f483de56 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h @@ -30,9 +30,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \
((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0))
-#define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
+#define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
-#define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))
+#define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))
#pragma pack(1)
//
@@ -41,8 +41,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // This is the same as frame list entry.
//
typedef struct {
- UINT32 HorizonLink;
- UINT32 VerticalLink;
+ UINT32 HorizonLink;
+ UINT32 VerticalLink;
} UHCI_QH_HW;
//
@@ -50,23 +50,23 @@ typedef struct { // Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1
//
typedef struct {
- UINT32 NextLink;
- UINT32 ActualLen : 11;
- UINT32 Reserved1 : 5;
- UINT32 Status : 8;
- UINT32 IntOnCpl : 1;
- UINT32 IsIsoch : 1;
- UINT32 LowSpeed : 1;
- UINT32 ErrorCount : 2;
- UINT32 ShortPacket : 1;
- UINT32 Reserved2 : 2;
- UINT32 PidCode : 8;
- UINT32 DeviceAddr : 7;
- UINT32 EndPoint : 4;
- UINT32 DataToggle : 1;
- UINT32 Reserved3 : 1;
- UINT32 MaxPacketLen: 11;
- UINT32 DataBuffer;
+ UINT32 NextLink;
+ UINT32 ActualLen : 11;
+ UINT32 Reserved1 : 5;
+ UINT32 Status : 8;
+ UINT32 IntOnCpl : 1;
+ UINT32 IsIsoch : 1;
+ UINT32 LowSpeed : 1;
+ UINT32 ErrorCount : 2;
+ UINT32 ShortPacket : 1;
+ UINT32 Reserved2 : 2;
+ UINT32 PidCode : 8;
+ UINT32 DeviceAddr : 7;
+ UINT32 EndPoint : 4;
+ UINT32 DataToggle : 1;
+ UINT32 Reserved3 : 1;
+ UINT32 MaxPacketLen : 11;
+ UINT32 DataBuffer;
} UHCI_TD_HW;
#pragma pack()
@@ -74,20 +74,19 @@ typedef struct _UHCI_TD_SW UHCI_TD_SW; typedef struct _UHCI_QH_SW UHCI_QH_SW;
struct _UHCI_QH_SW {
- UHCI_QH_HW QhHw;
- UHCI_QH_SW *NextQh;
- UHCI_TD_SW *TDs;
- UINTN Interval;
+ UHCI_QH_HW QhHw;
+ UHCI_QH_SW *NextQh;
+ UHCI_TD_SW *TDs;
+ UINTN Interval;
};
struct _UHCI_TD_SW {
- UHCI_TD_HW TdHw;
- UHCI_TD_SW *NextTd;
- UINT8 *Data;
- UINT16 DataLen;
+ UHCI_TD_HW TdHw;
+ UHCI_TD_SW *NextTd;
+ UINT8 *Data;
+ UINT16 DataLen;
};
-
/**
Link the TD To QH.
@@ -98,12 +97,11 @@ struct _UHCI_TD_SW { **/
VOID
UhciLinkTdToQh (
- IN USB_HC_DEV *Uhc,
- IN UHCI_QH_SW *Qh,
- IN UHCI_TD_SW *Td
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_QH_SW *Qh,
+ IN UHCI_TD_SW *Td
);
-
/**
Unlink TD from the QH.
@@ -115,11 +113,10 @@ UhciLinkTdToQh ( **/
VOID
UhciUnlinkTdFromQh (
- IN UHCI_QH_SW *Qh,
- IN UHCI_TD_SW *Td
+ IN UHCI_QH_SW *Qh,
+ IN UHCI_TD_SW *Td
);
-
/**
Map address of request structure buffer.
@@ -134,13 +131,12 @@ UhciUnlinkTdFromQh ( **/
EFI_STATUS
UhciMapUserRequest (
- IN USB_HC_DEV *Uhc,
- IN OUT VOID *Request,
- OUT UINT8 **MappedAddr,
- OUT VOID **Map
+ IN USB_HC_DEV *Uhc,
+ IN OUT VOID *Request,
+ OUT UINT8 **MappedAddr,
+ OUT VOID **Map
);
-
/**
Map address of user data buffer.
@@ -167,7 +163,6 @@ UhciMapUserData ( OUT VOID **Map
);
-
/**
Delete a list of TDs.
@@ -179,11 +174,10 @@ UhciMapUserData ( **/
VOID
UhciDestoryTds (
- IN USB_HC_DEV *Uhc,
- IN UHCI_TD_SW *FirstTd
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_TD_SW *FirstTd
);
-
/**
Create an initialize a new queue head.
@@ -195,11 +189,10 @@ UhciDestoryTds ( **/
UHCI_QH_SW *
UhciCreateQh (
- IN USB_HC_DEV *Uhc,
- IN UINTN Interval
+ IN USB_HC_DEV *Uhc,
+ IN UINTN Interval
);
-
/**
Create Tds list for Control Transfer.
@@ -219,19 +212,18 @@ UhciCreateQh ( **/
UHCI_TD_SW *
UhciCreateCtrlTds (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DeviceAddr,
- IN UINT8 DataPktId,
- IN UINT8 *Request,
- IN UINT8 *RequestPhy,
- IN UINT8 *Data,
- IN UINT8 *DataPhy,
- IN UINTN DataLen,
- IN UINT8 MaxPacket,
- IN BOOLEAN IsLow
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DeviceAddr,
+ IN UINT8 DataPktId,
+ IN UINT8 *Request,
+ IN UINT8 *RequestPhy,
+ IN UINT8 *Data,
+ IN UINT8 *DataPhy,
+ IN UINTN DataLen,
+ IN UINT8 MaxPacket,
+ IN BOOLEAN IsLow
);
-
/**
Create Tds list for Bulk/Interrupt Transfer.
@@ -251,16 +243,16 @@ UhciCreateCtrlTds ( **/
UHCI_TD_SW *
UhciCreateBulkOrIntTds (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DevAddr,
- IN UINT8 EndPoint,
- IN UINT8 PktId,
- IN UINT8 *Data,
- IN UINT8 *DataPhy,
- IN UINTN DataLen,
- IN OUT UINT8 *DataToggle,
- IN UINT8 MaxPacket,
- IN BOOLEAN IsLow
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EndPoint,
+ IN UINT8 PktId,
+ IN UINT8 *Data,
+ IN UINT8 *DataPhy,
+ IN UINTN DataLen,
+ IN OUT UINT8 *DataToggle,
+ IN UINT8 MaxPacket,
+ IN BOOLEAN IsLow
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c index 44bcde4c4e..9aa138fa46 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c @@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Uhci.h"
-
/**
Read a UHCI register.
@@ -21,21 +20,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
UINT16
UhciReadReg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset
)
{
UINT16 Data;
EFI_STATUS Status;
Status = PciIo->Io.Read (
- PciIo,
- EfiPciIoWidthUint16,
- USB_BAR_INDEX,
- Offset,
- 1,
- &Data
- );
+ PciIo,
+ EfiPciIoWidthUint16,
+ USB_BAR_INDEX,
+ Offset,
+ 1,
+ &Data
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));
@@ -46,7 +45,6 @@ UhciReadReg ( return Data;
}
-
/**
Write data to UHCI register.
@@ -57,28 +55,27 @@ UhciReadReg ( **/
VOID
UhciWriteReg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
- IN UINT16 Data
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset,
+ IN UINT16 Data
)
{
EFI_STATUS Status;
Status = PciIo->Io.Write (
- PciIo,
- EfiPciIoWidthUint16,
- USB_BAR_INDEX,
- Offset,
- 1,
- &Data
- );
+ PciIo,
+ EfiPciIoWidthUint16,
+ USB_BAR_INDEX,
+ Offset,
+ 1,
+ &Data
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));
}
}
-
/**
Set a bit of the UHCI Register.
@@ -89,19 +86,18 @@ UhciWriteReg ( **/
VOID
UhciSetRegBit (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
- IN UINT16 Bit
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset,
+ IN UINT16 Bit
)
{
UINT16 Data;
Data = UhciReadReg (PciIo, Offset);
- Data = (UINT16) (Data |Bit);
+ Data = (UINT16)(Data |Bit);
UhciWriteReg (PciIo, Offset, Data);
}
-
/**
Clear a bit of the UHCI Register.
@@ -112,19 +108,18 @@ UhciSetRegBit ( **/
VOID
UhciClearRegBit (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
- IN UINT16 Bit
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset,
+ IN UINT16 Bit
)
{
UINT16 Data;
Data = UhciReadReg (PciIo, Offset);
- Data = (UINT16) (Data & ~Bit);
+ Data = (UINT16)(Data & ~Bit);
UhciWriteReg (PciIo, Offset, Data);
}
-
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@@ -134,7 +129,7 @@ UhciClearRegBit ( **/
VOID
UhciAckAllInterrupt (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
)
{
UhciWriteReg (Uhc->PciIo, USBSTS_OFFSET, 0x3F);
@@ -149,7 +144,6 @@ UhciAckAllInterrupt ( }
}
-
/**
Stop the host controller.
@@ -162,12 +156,12 @@ UhciAckAllInterrupt ( **/
EFI_STATUS
UhciStopHc (
- IN USB_HC_DEV *Uhc,
- IN UINTN Timeout
+ IN USB_HC_DEV *Uhc,
+ IN UINTN Timeout
)
{
- UINT16 UsbSts;
- UINTN Index;
+ UINT16 UsbSts;
+ UINTN Index;
UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_RS);
@@ -188,7 +182,6 @@ UhciStopHc ( return EFI_TIMEOUT;
}
-
/**
Check whether the host controller operates well.
@@ -200,10 +193,10 @@ UhciStopHc ( **/
BOOLEAN
UhciIsHcWorking (
- IN EFI_PCI_IO_PROTOCOL *PciIo
+ IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
- UINT16 UsbSts;
+ UINT16 UsbSts;
UsbSts = UhciReadReg (PciIo, USBSTS_OFFSET);
@@ -215,7 +208,6 @@ UhciIsHcWorking ( return TRUE;
}
-
/**
Set the UHCI frame list base address. It can't use
UhciWriteReg which access memory in UINT16.
@@ -226,20 +218,20 @@ UhciIsHcWorking ( **/
VOID
UhciSetFrameListBaseAddr (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *Addr
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *Addr
)
{
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_STATUS Status;
+ UINT32 Data;
- Data = (UINT32) ((UINTN) Addr & 0xFFFFF000);
+ Data = (UINT32)((UINTN)Addr & 0xFFFFF000);
Status = PciIo->Io.Write (
PciIo,
EfiPciIoWidthUint32,
USB_BAR_INDEX,
- (UINT64) USB_FRAME_BASE_OFFSET,
+ (UINT64)USB_FRAME_BASE_OFFSET,
1,
&Data
);
@@ -249,7 +241,6 @@ UhciSetFrameListBaseAddr ( }
}
-
/**
Disable USB Emulation.
@@ -258,10 +249,10 @@ UhciSetFrameListBaseAddr ( **/
VOID
UhciTurnOffUsbEmulation (
- IN EFI_PCI_IO_PROTOCOL *PciIo
+ IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
- UINT16 Command;
+ UINT16 Command;
Command = 0;
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h index b39dcbbbec..84e2d1bd2a 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h @@ -14,42 +14,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // UHCI register offset
//
-#define UHCI_FRAME_NUM 1024
+#define UHCI_FRAME_NUM 1024
//
// Register offset and PCI related staff
//
-#define USB_BAR_INDEX 4
+#define USB_BAR_INDEX 4
-#define USBCMD_OFFSET 0
-#define USBSTS_OFFSET 2
-#define USBINTR_OFFSET 4
-#define USBPORTSC_OFFSET 0x10
-#define USB_FRAME_NO_OFFSET 6
-#define USB_FRAME_BASE_OFFSET 8
-#define USB_EMULATION_OFFSET 0xC0
+#define USBCMD_OFFSET 0
+#define USBSTS_OFFSET 2
+#define USBINTR_OFFSET 4
+#define USBPORTSC_OFFSET 0x10
+#define USB_FRAME_NO_OFFSET 6
+#define USB_FRAME_BASE_OFFSET 8
+#define USB_EMULATION_OFFSET 0xC0
//
// Packet IDs
//
-#define SETUP_PACKET_ID 0x2D
-#define INPUT_PACKET_ID 0x69
-#define OUTPUT_PACKET_ID 0xE1
-#define ERROR_PACKET_ID 0x55
+#define SETUP_PACKET_ID 0x2D
+#define INPUT_PACKET_ID 0x69
+#define OUTPUT_PACKET_ID 0xE1
+#define ERROR_PACKET_ID 0x55
//
// USB port status and control bit definition.
//
-#define USBPORTSC_CCS BIT0 // Current Connect Status
-#define USBPORTSC_CSC BIT1 // Connect Status Change
-#define USBPORTSC_PED BIT2 // Port Enable / Disable
-#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
-#define USBPORTSC_LSL BIT4 // Line Status Low BIT
-#define USBPORTSC_LSH BIT5 // Line Status High BIT
-#define USBPORTSC_RD BIT6 // Resume Detect
-#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
-#define USBPORTSC_PR BIT9 // Port Reset
-#define USBPORTSC_SUSP BIT12 // Suspend
+#define USBPORTSC_CCS BIT0 // Current Connect Status
+#define USBPORTSC_CSC BIT1 // Connect Status Change
+#define USBPORTSC_PED BIT2 // Port Enable / Disable
+#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
+#define USBPORTSC_LSL BIT4 // Line Status Low BIT
+#define USBPORTSC_LSH BIT5 // Line Status High BIT
+#define USBPORTSC_RD BIT6 // Resume Detect
+#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
+#define USBPORTSC_PR BIT9 // Port Reset
+#define USBPORTSC_SUSP BIT12 // Suspend
//
// UHCI Spec said it must implement 2 ports each host at least,
@@ -61,33 +61,32 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Command register bit definitions
//
-#define USBCMD_RS BIT0 // Run/Stop
-#define USBCMD_HCRESET BIT1 // Host reset
-#define USBCMD_GRESET BIT2 // Global reset
-#define USBCMD_EGSM BIT3 // Global Suspend Mode
-#define USBCMD_FGR BIT4 // Force Global Resume
-#define USBCMD_SWDBG BIT5 // SW Debug mode
-#define USBCMD_CF BIT6 // Config Flag (sw only)
-#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
+#define USBCMD_RS BIT0 // Run/Stop
+#define USBCMD_HCRESET BIT1 // Host reset
+#define USBCMD_GRESET BIT2 // Global reset
+#define USBCMD_EGSM BIT3 // Global Suspend Mode
+#define USBCMD_FGR BIT4 // Force Global Resume
+#define USBCMD_SWDBG BIT5 // SW Debug mode
+#define USBCMD_CF BIT6 // Config Flag (sw only)
+#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
//
// USB Status register bit definitions
//
-#define USBSTS_USBINT BIT0 // Interrupt due to IOC
-#define USBSTS_ERROR BIT1 // Interrupt due to error
-#define USBSTS_RD BIT2 // Resume Detect
-#define USBSTS_HSE BIT3 // Host System Error
-#define USBSTS_HCPE BIT4 // Host Controller Process Error
-#define USBSTS_HCH BIT5 // HC Halted
-
-#define USBTD_ACTIVE BIT7 // TD is still active
-#define USBTD_STALLED BIT6 // TD is stalled
-#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
-#define USBTD_BABBLE BIT4 // Babble condition
-#define USBTD_NAK BIT3 // NAK is received
-#define USBTD_CRC BIT2 // CRC/Time out error
-#define USBTD_BITSTUFF BIT1 // Bit stuff error
-
+#define USBSTS_USBINT BIT0 // Interrupt due to IOC
+#define USBSTS_ERROR BIT1 // Interrupt due to error
+#define USBSTS_RD BIT2 // Resume Detect
+#define USBSTS_HSE BIT3 // Host System Error
+#define USBSTS_HCPE BIT4 // Host Controller Process Error
+#define USBSTS_HCH BIT5 // HC Halted
+
+#define USBTD_ACTIVE BIT7 // TD is still active
+#define USBTD_STALLED BIT6 // TD is stalled
+#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
+#define USBTD_BABBLE BIT4 // Babble condition
+#define USBTD_NAK BIT3 // NAK is received
+#define USBTD_CRC BIT2 // CRC/Time out error
+#define USBTD_BITSTUFF BIT1 // Bit stuff error
/**
Read a UHCI register.
@@ -100,12 +99,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
UINT16
UhciReadReg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset
);
-
-
/**
Write data to UHCI register.
@@ -118,13 +115,11 @@ UhciReadReg ( **/
VOID
UhciWriteReg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
- IN UINT16 Data
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset,
+ IN UINT16 Data
);
-
-
/**
Set a bit of the UHCI Register.
@@ -137,13 +132,11 @@ UhciWriteReg ( **/
VOID
UhciSetRegBit (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
- IN UINT16 Bit
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset,
+ IN UINT16 Bit
);
-
-
/**
Clear a bit of the UHCI Register.
@@ -156,12 +149,11 @@ UhciSetRegBit ( **/
VOID
UhciClearRegBit (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
- IN UINT16 Bit
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset,
+ IN UINT16 Bit
);
-
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@@ -173,10 +165,9 @@ UhciClearRegBit ( **/
VOID
UhciAckAllInterrupt (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
);
-
/**
Stop the host controller.
@@ -189,12 +180,10 @@ UhciAckAllInterrupt ( **/
EFI_STATUS
UhciStopHc (
- IN USB_HC_DEV *Uhc,
- IN UINTN Timeout
+ IN USB_HC_DEV *Uhc,
+ IN UINTN Timeout
);
-
-
/**
Check whether the host controller operates well.
@@ -206,10 +195,9 @@ UhciStopHc ( **/
BOOLEAN
UhciIsHcWorking (
- IN EFI_PCI_IO_PROTOCOL *PciIo
+ IN EFI_PCI_IO_PROTOCOL *PciIo
);
-
/**
Set the UHCI frame list base address. It can't use
UhciWriteReg which access memory in UINT16.
@@ -222,11 +210,10 @@ UhciIsHcWorking ( **/
VOID
UhciSetFrameListBaseAddr (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *Addr
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *Addr
);
-
/**
Disable USB Emulation.
@@ -237,6 +224,7 @@ UhciSetFrameListBaseAddr ( **/
VOID
UhciTurnOffUsbEmulation (
- IN EFI_PCI_IO_PROTOCOL *PciIo
+ IN EFI_PCI_IO_PROTOCOL *PciIo
);
+
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c index 0829bc2a8c..c08f949696 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c @@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Uhci.h"
-
/**
Create Frame List Structure.
@@ -22,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
UhciInitFrameList (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
)
{
EFI_PHYSICAL_ADDRESS MappedAddr;
@@ -70,14 +69,14 @@ UhciInitFrameList ( goto ON_ERROR;
}
- Uhc->FrameBase = (UINT32 *) (UINTN) Buffer;
- Uhc->FrameMapping = Mapping;
+ Uhc->FrameBase = (UINT32 *)(UINTN)Buffer;
+ Uhc->FrameMapping = Mapping;
//
// Tell the Host Controller where the Frame List lies,
// by set the Frame List Base Address Register.
//
- UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *) (UINTN) MappedAddr);
+ UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *)(UINTN)MappedAddr);
//
// Allocate the QH used by sync interrupt/control/bulk transfer.
@@ -85,9 +84,9 @@ UhciInitFrameList ( // can be reclaimed. Notice, LS don't support bulk transfer and
// also doesn't support BW reclamation.
//
- Uhc->SyncIntQh = UhciCreateQh (Uhc, 1);
- Uhc->CtrlQh = UhciCreateQh (Uhc, 1);
- Uhc->BulkQh = UhciCreateQh (Uhc, 1);
+ Uhc->SyncIntQh = UhciCreateQh (Uhc, 1);
+ Uhc->CtrlQh = UhciCreateQh (Uhc, 1);
+ Uhc->BulkQh = UhciCreateQh (Uhc, 1);
if ((Uhc->SyncIntQh == NULL) || (Uhc->CtrlQh == NULL) || (Uhc->BulkQh == NULL)) {
Uhc->PciIo->Unmap (Uhc->PciIo, Mapping);
@@ -102,22 +101,22 @@ UhciInitFrameList ( // Each frame entry is linked to this sequence of QH. These QH
// will remain on the schedul, never got removed
//
- PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_HW));
- Uhc->SyncIntQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
- Uhc->SyncIntQh->NextQh = Uhc->CtrlQh;
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_HW));
+ Uhc->SyncIntQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
+ Uhc->SyncIntQh->NextQh = Uhc->CtrlQh;
- PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_HW));
- Uhc->CtrlQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
- Uhc->CtrlQh->NextQh = Uhc->BulkQh;
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_HW));
+ Uhc->CtrlQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
+ Uhc->CtrlQh->NextQh = Uhc->BulkQh;
//
// Some old platform such as Intel's Tiger 4 has a difficult time
// in supporting the full speed bandwidth reclamation in the previous
// mentioned form. Most new platforms don't suffer it.
//
- Uhc->BulkQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
+ Uhc->BulkQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
- Uhc->BulkQh->NextQh = NULL;
+ Uhc->BulkQh->NextQh = NULL;
Uhc->FrameBaseHostAddr = AllocateZeroPool (4096);
if (Uhc->FrameBaseHostAddr == NULL) {
@@ -127,7 +126,7 @@ UhciInitFrameList ( PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->SyncIntQh, sizeof (UHCI_QH_HW));
for (Index = 0; Index < UHCI_FRAME_NUM; Index++) {
- Uhc->FrameBase[Index] = QH_HLINK (PhyAddr, FALSE);
+ Uhc->FrameBase[Index] = QH_HLINK (PhyAddr, FALSE);
Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Uhc->SyncIntQh;
}
@@ -150,7 +149,6 @@ ON_ERROR: return Status;
}
-
/**
Destory FrameList buffer.
@@ -159,7 +157,7 @@ ON_ERROR: **/
VOID
UhciDestoryFrameList (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
)
{
//
@@ -172,7 +170,7 @@ UhciDestoryFrameList ( Uhc->PciIo->FreeBuffer (
Uhc->PciIo,
EFI_SIZE_TO_PAGES (4096),
- (VOID *) Uhc->FrameBase
+ (VOID *)Uhc->FrameBase
);
if (Uhc->FrameBaseHostAddr != NULL) {
@@ -191,14 +189,13 @@ UhciDestoryFrameList ( UsbHcFreeMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_SW));
}
- Uhc->FrameBase = NULL;
- Uhc->FrameBaseHostAddr = NULL;
- Uhc->SyncIntQh = NULL;
- Uhc->CtrlQh = NULL;
- Uhc->BulkQh = NULL;
+ Uhc->FrameBase = NULL;
+ Uhc->FrameBaseHostAddr = NULL;
+ Uhc->SyncIntQh = NULL;
+ Uhc->CtrlQh = NULL;
+ Uhc->BulkQh = NULL;
}
-
/**
Convert the poll rate to the maxium 2^n that is smaller
than Interval.
@@ -210,10 +207,10 @@ UhciDestoryFrameList ( **/
UINTN
UhciConvertPollRate (
- IN UINTN Interval
+ IN UINTN Interval
)
{
- UINTN BitCount;
+ UINTN BitCount;
ASSERT (Interval != 0);
@@ -230,7 +227,6 @@ UhciConvertPollRate ( return (UINTN)1 << (BitCount - 1);
}
-
/**
Link a queue head (for asynchronous interrupt transfer) to
the frame list.
@@ -241,15 +237,15 @@ UhciConvertPollRate ( **/
VOID
UhciLinkQhToFrameList (
- USB_HC_DEV *Uhc,
- UHCI_QH_SW *Qh
+ USB_HC_DEV *Uhc,
+ UHCI_QH_SW *Qh
)
{
- UINTN Index;
- UHCI_QH_SW *Prev;
- UHCI_QH_SW *Next;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EFI_PHYSICAL_ADDRESS QhPciAddr;
+ UINTN Index;
+ UHCI_QH_SW *Prev;
+ UHCI_QH_SW *Next;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_PHYSICAL_ADDRESS QhPciAddr;
ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));
@@ -261,8 +257,8 @@ UhciLinkQhToFrameList ( // heads on the frame list
//
ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));
- Next = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];
- Prev = NULL;
+ Next = (UHCI_QH_SW *)(UINTN)Uhc->FrameBaseHostAddr[Index];
+ Prev = NULL;
//
// Now, insert the queue head (Qh) into this frame:
@@ -279,8 +275,8 @@ UhciLinkQhToFrameList ( // rate is correct.
//
while (Next->Interval > Qh->Interval) {
- Prev = Next;
- Next = Next->NextQh;
+ Prev = Next;
+ Next = Next->NextQh;
ASSERT (Next != NULL);
}
@@ -305,15 +301,15 @@ UhciLinkQhToFrameList ( //
ASSERT ((Index == 0) && (Qh->NextQh == NULL));
- Prev = Next;
- Next = Next->NextQh;
+ Prev = Next;
+ Next = Next->NextQh;
- Qh->NextQh = Next;
- Prev->NextQh = Qh;
+ Qh->NextQh = Next;
+ Prev->NextQh = Qh;
- Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
+ Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
- Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
+ Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
break;
}
@@ -323,22 +319,21 @@ UhciLinkQhToFrameList ( // guarranted by 2^n polling interval.
//
if (Qh->NextQh == NULL) {
- Qh->NextQh = Next;
- PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Next, sizeof (UHCI_QH_HW));
- Qh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
+ Qh->NextQh = Next;
+ PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Next, sizeof (UHCI_QH_HW));
+ Qh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
}
if (Prev == NULL) {
- Uhc->FrameBase[Index] = QH_HLINK (QhPciAddr, FALSE);
- Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh;
+ Uhc->FrameBase[Index] = QH_HLINK (QhPciAddr, FALSE);
+ Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh;
} else {
- Prev->NextQh = Qh;
- Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
+ Prev->NextQh = Qh;
+ Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
}
}
}
-
/**
Unlink QH from the frame list is easier: find all
the precedence node, and pointer there next to QhSw's
@@ -350,13 +345,13 @@ UhciLinkQhToFrameList ( **/
VOID
UhciUnlinkQhFromFrameList (
- USB_HC_DEV *Uhc,
- UHCI_QH_SW *Qh
+ USB_HC_DEV *Uhc,
+ UHCI_QH_SW *Qh
)
{
- UINTN Index;
- UHCI_QH_SW *Prev;
- UHCI_QH_SW *This;
+ UINTN Index;
+ UHCI_QH_SW *Prev;
+ UHCI_QH_SW *This;
ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));
@@ -366,16 +361,16 @@ UhciUnlinkQhFromFrameList ( // queue heads on the frame list
//
ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));
- This = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];
- Prev = NULL;
+ This = (UHCI_QH_SW *)(UINTN)Uhc->FrameBaseHostAddr[Index];
+ Prev = NULL;
//
// Walk through the frame's QH list to find the
// queue head to remove
//
while ((This != NULL) && (This != Qh)) {
- Prev = This;
- This = This->NextQh;
+ Prev = This;
+ This = This->NextQh;
}
//
@@ -390,16 +385,15 @@ UhciUnlinkQhFromFrameList ( //
// Qh is the first entry in the frame
//
- Uhc->FrameBase[Index] = Qh->QhHw.HorizonLink;
- Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh->NextQh;
+ Uhc->FrameBase[Index] = Qh->QhHw.HorizonLink;
+ Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh->NextQh;
} else {
- Prev->NextQh = Qh->NextQh;
- Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
+ Prev->NextQh = Qh->NextQh;
+ Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
}
}
}
-
/**
Check TDs Results.
@@ -413,18 +407,18 @@ UhciUnlinkQhFromFrameList ( **/
BOOLEAN
UhciCheckTdStatus (
- IN USB_HC_DEV *Uhc,
- IN UHCI_TD_SW *Td,
- IN BOOLEAN IsLow,
- OUT UHCI_QH_RESULT *QhResult
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_TD_SW *Td,
+ IN BOOLEAN IsLow,
+ OUT UHCI_QH_RESULT *QhResult
)
{
- UINTN Len;
- UINT8 State;
- UHCI_TD_HW *TdHw;
- BOOLEAN Finished;
+ UINTN Len;
+ UINT8 State;
+ UHCI_TD_HW *TdHw;
+ BOOLEAN Finished;
- Finished = TRUE;
+ Finished = TRUE;
//
// Initialize the data toggle to that of the first
@@ -457,7 +451,6 @@ UhciCheckTdStatus ( if ((State & USBTD_STALLED) != 0) {
if ((State & USBTD_BABBLE) != 0) {
QhResult->Result |= EFI_USB_ERR_BABBLE;
-
} else if (TdHw->ErrorCount != 0) {
QhResult->Result |= EFI_USB_ERR_STALL;
}
@@ -480,7 +473,6 @@ UhciCheckTdStatus ( Finished = TRUE;
goto ON_EXIT;
-
} else if ((State & USBTD_ACTIVE) != 0) {
//
// The TD is still active, no need to check further.
@@ -489,14 +481,13 @@ UhciCheckTdStatus ( Finished = FALSE;
goto ON_EXIT;
-
} else {
//
// Update the next data toggle, it is always the
// next to the last known-good TD's data toggle if
// any TD is executed OK
//
- QhResult->NextToggle = (UINT8) (1 - (UINT8)TdHw->DataToggle);
+ QhResult->NextToggle = (UINT8)(1 - (UINT8)TdHw->DataToggle);
//
// This TD is finished OK or met short packet read. Update the
@@ -530,7 +521,7 @@ ON_EXIT: //
if (!UhciIsHcWorking (Uhc->PciIo)) {
QhResult->Result |= EFI_USB_ERR_SYSTEM;
- Finished = TRUE;
+ Finished = TRUE;
}
if (Finished) {
@@ -541,7 +532,6 @@ ON_EXIT: return Finished;
}
-
/**
Check the result of the transfer.
@@ -558,19 +548,19 @@ ON_EXIT: **/
EFI_STATUS
UhciExecuteTransfer (
- IN USB_HC_DEV *Uhc,
- IN UHCI_QH_SW *Qh,
- IN UHCI_TD_SW *Td,
- IN UINTN TimeOut,
- IN BOOLEAN IsLow,
- OUT UHCI_QH_RESULT *QhResult
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_QH_SW *Qh,
+ IN UHCI_TD_SW *Td,
+ IN UINTN TimeOut,
+ IN BOOLEAN IsLow,
+ OUT UHCI_QH_RESULT *QhResult
)
{
- UINTN Index;
- UINTN Delay;
- BOOLEAN Finished;
- EFI_STATUS Status;
- BOOLEAN InfiniteLoop;
+ UINTN Index;
+ UINTN Delay;
+ BOOLEAN Finished;
+ EFI_STATUS Status;
+ BOOLEAN InfiniteLoop;
Finished = FALSE;
Status = EFI_SUCCESS;
@@ -605,7 +595,6 @@ UhciExecuteTransfer ( UhciDumpTds (Td);
Status = EFI_TIMEOUT;
-
} else if (QhResult->Result != EFI_USB_NOERROR) {
DEBUG ((DEBUG_ERROR, "UhciExecuteTransfer: execution failed with result %x\n", QhResult->Result));
UhciDumpQh (Qh);
@@ -617,7 +606,6 @@ UhciExecuteTransfer ( return Status;
}
-
/**
Update Async Request, QH and TDs.
@@ -635,12 +623,12 @@ UhciUpdateAsyncReq ( IN UINT32 NextToggle
)
{
- UHCI_QH_SW *Qh;
- UHCI_TD_SW *FirstTd;
- UHCI_TD_SW *Td;
+ UHCI_QH_SW *Qh;
+ UHCI_TD_SW *FirstTd;
+ UHCI_TD_SW *Td;
- Qh = AsyncReq->QhSw;
- FirstTd = AsyncReq->FirstTd;
+ Qh = AsyncReq->QhSw;
+ FirstTd = AsyncReq->FirstTd;
if (Result == EFI_USB_NOERROR) {
//
@@ -659,11 +647,10 @@ UhciUpdateAsyncReq ( }
UhciLinkTdToQh (Uhc, Qh, FirstTd);
- return ;
+ return;
}
}
-
/**
Create Async Request node, and Link to List.
@@ -699,7 +686,7 @@ UhciCreateAsyncReq ( IN BOOLEAN IsLow
)
{
- UHCI_ASYNC_REQUEST *AsyncReq;
+ UHCI_ASYNC_REQUEST *AsyncReq;
AsyncReq = AllocatePool (sizeof (UHCI_ASYNC_REQUEST));
@@ -710,17 +697,17 @@ UhciCreateAsyncReq ( //
// Fill Request field. Data is allocated host memory, not mapped
//
- AsyncReq->Signature = UHCI_ASYNC_INT_SIGNATURE;
- AsyncReq->DevAddr = DevAddr;
- AsyncReq->EndPoint = EndPoint;
- AsyncReq->DataLen = DataLen;
- AsyncReq->Interval = UhciConvertPollRate(Interval);
- AsyncReq->Data = Data;
- AsyncReq->Callback = Callback;
- AsyncReq->Context = Context;
- AsyncReq->QhSw = Qh;
- AsyncReq->FirstTd = FirstTd;
- AsyncReq->IsLow = IsLow;
+ AsyncReq->Signature = UHCI_ASYNC_INT_SIGNATURE;
+ AsyncReq->DevAddr = DevAddr;
+ AsyncReq->EndPoint = EndPoint;
+ AsyncReq->DataLen = DataLen;
+ AsyncReq->Interval = UhciConvertPollRate (Interval);
+ AsyncReq->Data = Data;
+ AsyncReq->Callback = Callback;
+ AsyncReq->Context = Context;
+ AsyncReq->QhSw = Qh;
+ AsyncReq->FirstTd = FirstTd;
+ AsyncReq->IsLow = IsLow;
//
// Insert the new interrupt transfer to the head of the list.
@@ -733,7 +720,6 @@ UhciCreateAsyncReq ( return EFI_SUCCESS;
}
-
/**
Free an asynchronous request's resource such as memory.
@@ -743,8 +729,8 @@ UhciCreateAsyncReq ( **/
VOID
UhciFreeAsyncReq (
- IN USB_HC_DEV *Uhc,
- IN UHCI_ASYNC_REQUEST *AsyncReq
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_ASYNC_REQUEST *AsyncReq
)
{
ASSERT ((Uhc != NULL) && (AsyncReq != NULL));
@@ -759,7 +745,6 @@ UhciFreeAsyncReq ( gBS->FreePool (AsyncReq);
}
-
/**
Unlink an asynchronous request's from UHC's asynchronus list.
also remove the queue head from the frame list. If FreeNow,
@@ -775,9 +760,9 @@ UhciFreeAsyncReq ( **/
VOID
UhciUnlinkAsyncReq (
- IN USB_HC_DEV *Uhc,
- IN UHCI_ASYNC_REQUEST *AsyncReq,
- IN BOOLEAN FreeNow
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_ASYNC_REQUEST *AsyncReq,
+ IN BOOLEAN FreeNow
)
{
ASSERT ((Uhc != NULL) && (AsyncReq != NULL));
@@ -793,12 +778,11 @@ UhciUnlinkAsyncReq ( // then add AsyncReq to UHC's recycle list
//
AsyncReq->QhSw->QhHw.VerticalLink = QH_VLINK (NULL, TRUE);
- AsyncReq->Recycle = Uhc->RecycleWait;
- Uhc->RecycleWait = AsyncReq;
+ AsyncReq->Recycle = Uhc->RecycleWait;
+ Uhc->RecycleWait = AsyncReq;
}
}
-
/**
Delete Async Interrupt QH and TDs.
@@ -814,10 +798,10 @@ UhciUnlinkAsyncReq ( **/
EFI_STATUS
UhciRemoveAsyncReq (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DevAddr,
- IN UINT8 EndPoint,
- OUT UINT8 *Toggle
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EndPoint,
+ OUT UINT8 *Toggle
)
{
EFI_STATUS Status;
@@ -842,14 +826,13 @@ UhciRemoveAsyncReq ( Link = Uhc->AsyncIntList.ForwardLink;
do {
- AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
- Link = Link->ForwardLink;
+ AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
+ Link = Link->ForwardLink;
if ((AsyncReq->DevAddr == DevAddr) && (AsyncReq->EndPoint == EndPoint)) {
Found = TRUE;
break;
}
-
} while (Link != &(Uhc->AsyncIntList));
if (!Found) {
@@ -870,7 +853,6 @@ UhciRemoveAsyncReq ( return Status;
}
-
/**
Recycle the asynchronouse request. When a queue head
is unlinked from frame list, host controller hardware
@@ -889,26 +871,24 @@ UhciRemoveAsyncReq ( **/
VOID
UhciRecycleAsyncReq (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
)
{
- UHCI_ASYNC_REQUEST *Req;
- UHCI_ASYNC_REQUEST *Next;
+ UHCI_ASYNC_REQUEST *Req;
+ UHCI_ASYNC_REQUEST *Next;
Req = Uhc->Recycle;
while (Req != NULL) {
Next = Req->Recycle;
UhciFreeAsyncReq (Uhc, Req);
- Req = Next;
+ Req = Next;
}
Uhc->Recycle = Uhc->RecycleWait;
Uhc->RecycleWait = NULL;
}
-
-
/**
Release all the asynchronous transfers on the lsit.
@@ -917,11 +897,11 @@ UhciRecycleAsyncReq ( **/
VOID
UhciFreeAllAsyncReq (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
)
{
- LIST_ENTRY *Head;
- UHCI_ASYNC_REQUEST *AsyncReq;
+ LIST_ENTRY *Head;
+ UHCI_ASYNC_REQUEST *AsyncReq;
//
// Call UhciRecycleAsyncReq twice. The requests on Recycle
@@ -938,12 +918,11 @@ UhciFreeAllAsyncReq ( }
while (!IsListEmpty (Head)) {
- AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Head->ForwardLink);
+ AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Head->ForwardLink);
UhciUnlinkAsyncReq (Uhc, AsyncReq, TRUE);
}
}
-
/**
Interrupt transfer periodic check handler.
@@ -954,18 +933,18 @@ UhciFreeAllAsyncReq ( VOID
EFIAPI
UhciMonitorAsyncReqList (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- UHCI_ASYNC_REQUEST *AsyncReq;
- LIST_ENTRY *Link;
- USB_HC_DEV *Uhc;
- VOID *Data;
- BOOLEAN Finished;
- UHCI_QH_RESULT QhResult;
+ UHCI_ASYNC_REQUEST *AsyncReq;
+ LIST_ENTRY *Link;
+ USB_HC_DEV *Uhc;
+ VOID *Data;
+ BOOLEAN Finished;
+ UHCI_QH_RESULT QhResult;
- Uhc = (USB_HC_DEV *) Context;
+ Uhc = (USB_HC_DEV *)Context;
//
// Recycle the asynchronous requests expired, and promote
@@ -975,7 +954,7 @@ UhciMonitorAsyncReqList ( UhciRecycleAsyncReq (Uhc);
if (IsListEmpty (&(Uhc->AsyncIntList))) {
- return ;
+ return;
}
//
@@ -984,8 +963,8 @@ UhciMonitorAsyncReqList ( Link = Uhc->AsyncIntList.ForwardLink;
do {
- AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
- Link = Link->ForwardLink;
+ AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
+ Link = Link->ForwardLink;
Finished = UhciCheckTdStatus (Uhc, AsyncReq->FirstTd, AsyncReq->IsLow, &QhResult);
@@ -1004,7 +983,7 @@ UhciMonitorAsyncReqList ( Data = AllocatePool (QhResult.Complete);
if (Data == NULL) {
- return ;
+ return;
}
CopyMem (Data, AsyncReq->FirstTd->Data, QhResult.Complete);
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h index 5bcfad5c6c..2112d13200 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_UHCI_SCHED_H_
#define _EFI_UHCI_SCHED_H_
-
#define UHCI_ASYNC_INT_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'a')
//
// The failure mask for USB transfer return status. If any of
@@ -23,7 +22,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF | \
EFI_USB_ERR_SYSTEM)
-
//
// Structure to return the result of UHCI QH execution.
// Result is the final result of the QH's QTD. NextToggle
@@ -31,49 +29,48 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // length of data transferred.
//
typedef struct {
- UINT32 Result;
- UINT8 NextToggle;
- UINTN Complete;
+ UINT32 Result;
+ UINT8 NextToggle;
+ UINTN Complete;
} UHCI_QH_RESULT;
-typedef struct _UHCI_ASYNC_REQUEST UHCI_ASYNC_REQUEST;
+typedef struct _UHCI_ASYNC_REQUEST UHCI_ASYNC_REQUEST;
//
// Structure used to manager the asynchronous interrupt transfers.
//
-struct _UHCI_ASYNC_REQUEST{
- UINTN Signature;
- LIST_ENTRY Link;
- UHCI_ASYNC_REQUEST *Recycle;
+struct _UHCI_ASYNC_REQUEST {
+ UINTN Signature;
+ LIST_ENTRY Link;
+ UHCI_ASYNC_REQUEST *Recycle;
//
// Endpoint attributes
//
- UINT8 DevAddr;
- UINT8 EndPoint;
- BOOLEAN IsLow;
- UINTN Interval;
+ UINT8 DevAddr;
+ UINT8 EndPoint;
+ BOOLEAN IsLow;
+ UINTN Interval;
//
// Data and UHC structures
//
- UHCI_QH_SW *QhSw;
- UHCI_TD_SW *FirstTd;
- UINT8 *Data; // Allocated host memory, not mapped memory
- UINTN DataLen;
- VOID *Mapping;
+ UHCI_QH_SW *QhSw;
+ UHCI_TD_SW *FirstTd;
+ UINT8 *Data; // Allocated host memory, not mapped memory
+ UINTN DataLen;
+ VOID *Mapping;
//
// User callback and its context
//
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
};
#define UHCI_ASYNC_INT_FROM_LINK(a) \
CR (a, UHCI_ASYNC_REQUEST, Link, UHCI_ASYNC_INT_SIGNATURE)
-
/**
Create Frame List Structure.
@@ -86,7 +83,7 @@ struct _UHCI_ASYNC_REQUEST{ **/
EFI_STATUS
UhciInitFrameList (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
);
/**
@@ -99,10 +96,9 @@ UhciInitFrameList ( **/
VOID
UhciDestoryFrameList (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
);
-
/**
Convert the poll rate to the maxium 2^n that is smaller
than Interval.
@@ -114,10 +110,9 @@ UhciDestoryFrameList ( **/
UINTN
UhciConvertPollRate (
- IN UINTN Interval
+ IN UINTN Interval
);
-
/**
Link a queue head (for asynchronous interrupt transfer) to
the frame list.
@@ -128,11 +123,10 @@ UhciConvertPollRate ( **/
VOID
UhciLinkQhToFrameList (
- USB_HC_DEV *Uhc,
- UHCI_QH_SW *Qh
+ USB_HC_DEV *Uhc,
+ UHCI_QH_SW *Qh
);
-
/**
Unlink QH from the frame list is easier: find all
the precedence node, and pointer there next to QhSw's
@@ -144,11 +138,10 @@ UhciLinkQhToFrameList ( **/
VOID
UhciUnlinkQhFromFrameList (
- USB_HC_DEV *Uhc,
- UHCI_QH_SW *Qh
+ USB_HC_DEV *Uhc,
+ UHCI_QH_SW *Qh
);
-
/**
Check the result of the transfer.
@@ -165,15 +158,14 @@ UhciUnlinkQhFromFrameList ( **/
EFI_STATUS
UhciExecuteTransfer (
- IN USB_HC_DEV *Uhc,
- IN UHCI_QH_SW *Qh,
- IN UHCI_TD_SW *Td,
- IN UINTN TimeOut,
- IN BOOLEAN IsLow,
- OUT UHCI_QH_RESULT *QhResult
+ IN USB_HC_DEV *Uhc,
+ IN UHCI_QH_SW *Qh,
+ IN UHCI_TD_SW *Td,
+ IN UINTN TimeOut,
+ IN BOOLEAN IsLow,
+ OUT UHCI_QH_RESULT *QhResult
);
-
/**
Create Async Request node, and Link to List.
@@ -209,7 +201,6 @@ UhciCreateAsyncReq ( IN BOOLEAN IsLow
);
-
/**
Delete Async Interrupt QH and TDs.
@@ -225,13 +216,12 @@ UhciCreateAsyncReq ( **/
EFI_STATUS
UhciRemoveAsyncReq (
- IN USB_HC_DEV *Uhc,
- IN UINT8 DevAddr,
- IN UINT8 EndPoint,
- OUT UINT8 *Toggle
+ IN USB_HC_DEV *Uhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EndPoint,
+ OUT UINT8 *Toggle
);
-
/**
Release all the asynchronous transfers on the lsit.
@@ -242,10 +232,9 @@ UhciRemoveAsyncReq ( **/
VOID
UhciFreeAllAsyncReq (
- IN USB_HC_DEV *Uhc
+ IN USB_HC_DEV *Uhc
);
-
/**
Interrupt transfer periodic check handler.
@@ -258,8 +247,8 @@ UhciFreeAllAsyncReq ( VOID
EFIAPI
UhciMonitorAsyncReqList (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.c b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.c index a8c098f9c3..d6b9615e49 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.c @@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "Uhci.h"
-
/**
Allocate a block of memory to be used by the buffer pool.
@@ -21,17 +20,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Pages
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Pages
)
{
- USBHC_MEM_BLOCK *Block;
- EFI_PCI_IO_PROTOCOL *PciIo;
- VOID *BufHost;
- VOID *Mapping;
- EFI_PHYSICAL_ADDRESS MappedAddr;
- UINTN Bytes;
- EFI_STATUS Status;
+ USBHC_MEM_BLOCK *Block;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ UINTN Bytes;
+ EFI_STATUS Status;
PciIo = Pool->PciIo;
@@ -46,9 +45,9 @@ UsbHcAllocMemBlock ( //
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
- Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
- Block->Bits = AllocateZeroPool (Block->BitsLen);
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
+ Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
@@ -72,7 +71,7 @@ UsbHcAllocMemBlock ( goto FREE_BITARRAY;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -95,9 +94,9 @@ UsbHcAllocMemBlock ( goto FREE_BUFFER;
}
- Block->BufHost = BufHost;
- Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
- Block->Mapping = Mapping;
+ Block->BufHost = BufHost;
+ Block->Buf = (UINT8 *)((UINTN)MappedAddr);
+ Block->Mapping = Mapping;
return Block;
@@ -110,7 +109,6 @@ FREE_BITARRAY: return NULL;
}
-
/**
Free the memory block from the memory pool.
@@ -120,11 +118,11 @@ FREE_BITARRAY: **/
VOID
UsbHcFreeMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -140,7 +138,6 @@ UsbHcFreeMemBlock ( gBS->FreePool (Block);
}
-
/**
Alloc some memory from the block.
@@ -153,22 +150,22 @@ UsbHcFreeMemBlock ( **/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -184,13 +181,12 @@ UsbHcAllocMemFromBlock ( }
NEXT_BIT (Byte, Bit);
-
} else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -201,13 +197,13 @@ UsbHcAllocMemFromBlock ( //
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | (UINT8)USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -225,16 +221,16 @@ UsbHcAllocMemFromBlock ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -248,7 +244,7 @@ UsbHcGetPciAddressForHostMem ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -257,8 +253,8 @@ UsbHcGetPciAddressForHostMem ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -271,8 +267,8 @@ UsbHcGetPciAddressForHostMem ( **/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -280,7 +276,6 @@ UsbHcInsertMemBlockToPool ( Head->Next = Block;
}
-
/**
Is the memory block empty?
@@ -292,10 +287,10 @@ UsbHcInsertMemBlockToPool ( **/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -306,7 +301,6 @@ UsbHcIsMemBlockEmpty ( return TRUE;
}
-
/**
Unlink the memory block from the pool's list.
@@ -316,11 +310,11 @@ UsbHcIsMemBlockEmpty ( **/
VOID
UsbHcUnlinkMemBlock (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *BlockToUnlink
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -333,7 +327,6 @@ UsbHcUnlinkMemBlock ( }
}
-
/**
Initialize the memory management pool for the host controller.
@@ -353,7 +346,7 @@ UsbHcInitMemPool ( IN UINT32 Which4G
)
{
- USBHC_MEM_POOL *Pool;
+ USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -374,7 +367,6 @@ UsbHcInitMemPool ( return Pool;
}
-
/**
Release the memory management pool.
@@ -386,10 +378,10 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -408,7 +400,6 @@ UsbHcFreeMemPool ( return EFI_SUCCESS;
}
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -421,16 +412,16 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -485,7 +476,6 @@ UsbHcAllocateMem ( return Mem;
}
-
/**
Free the allocated memory back to the memory pool.
@@ -496,22 +486,22 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -522,8 +512,8 @@ UsbHcFreeMem ( //
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -531,7 +521,7 @@ UsbHcFreeMem ( for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -554,5 +544,5 @@ UsbHcFreeMem ( UsbHcFreeMemBlock (Pool, Block);
}
- return ;
+ return;
}
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h index d202669c11..6644cc4d97 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_MEM_H_
#define _EFI_EHCI_MEM_H_
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -18,16 +18,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define USB_HC_HIGH_32BIT(Addr64) \
((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
@@ -36,16 +35,16 @@ struct _USBHC_MEM_BLOCK { // data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- EFI_PCI_IO_PROTOCOL *PciIo;
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -64,7 +63,6 @@ typedef struct _USBHC_MEM_POOL { } \
} while (0)
-
/**
Initialize the memory management pool for the host controller.
@@ -84,7 +82,6 @@ UsbHcInitMemPool ( IN UINT32 Which4G
);
-
/**
Release the memory management pool.
@@ -96,11 +93,9 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
);
-
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -113,12 +108,10 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
);
-
-
/**
Free the allocated memory back to the memory pool.
@@ -131,9 +124,9 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -147,9 +140,9 @@ UsbHcFreeMem ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/UhciPei/DmaMem.c b/MdeModulePkg/Bus/Pci/UhciPei/DmaMem.c index 91e5bf5678..c6ef129235 100644 --- a/MdeModulePkg/Bus/Pci/UhciPei/DmaMem.c +++ b/MdeModulePkg/Bus/Pci/UhciPei/DmaMem.c @@ -39,8 +39,8 @@ IoMmuMap ( OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- UINT64 Attribute;
+ EFI_STATUS Status;
+ UINT64 Attribute;
if (IoMmu != NULL) {
Status = IoMmu->Map (
@@ -54,23 +54,25 @@ IoMmuMap ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
switch (Operation) {
- case EdkiiIoMmuOperationBusMasterRead:
- case EdkiiIoMmuOperationBusMasterRead64:
- Attribute = EDKII_IOMMU_ACCESS_READ;
- break;
- case EdkiiIoMmuOperationBusMasterWrite:
- case EdkiiIoMmuOperationBusMasterWrite64:
- Attribute = EDKII_IOMMU_ACCESS_WRITE;
- break;
- case EdkiiIoMmuOperationBusMasterCommonBuffer:
- case EdkiiIoMmuOperationBusMasterCommonBuffer64:
- Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
- break;
- default:
- ASSERT(FALSE);
- return EFI_INVALID_PARAMETER;
+ case EdkiiIoMmuOperationBusMasterRead:
+ case EdkiiIoMmuOperationBusMasterRead64:
+ Attribute = EDKII_IOMMU_ACCESS_READ;
+ break;
+ case EdkiiIoMmuOperationBusMasterWrite:
+ case EdkiiIoMmuOperationBusMasterWrite64:
+ Attribute = EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ case EdkiiIoMmuOperationBusMasterCommonBuffer:
+ case EdkiiIoMmuOperationBusMasterCommonBuffer64:
+ Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -82,10 +84,11 @@ IoMmuMap ( return Status;
}
} else {
- *DeviceAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
- *Mapping = NULL;
- Status = EFI_SUCCESS;
+ *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
+ *Mapping = NULL;
+ Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -98,8 +101,8 @@ IoMmuMap ( **/
VOID
IoMmuUnmap (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN VOID *Mapping
)
{
if (IoMmu != NULL) {
@@ -140,9 +143,9 @@ IoMmuAllocateBuffer ( UINTN NumberOfBytes;
EFI_PHYSICAL_ADDRESS HostPhyAddress;
- *HostAddress = NULL;
+ *HostAddress = NULL;
*DeviceAddress = 0;
- *Mapping = NULL;
+ *Mapping = NULL;
if (IoMmu != NULL) {
Status = IoMmu->AllocateBuffer (
@@ -157,19 +160,20 @@ IoMmuAllocateBuffer ( }
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
- Status = IoMmu->Map (
- IoMmu,
- EdkiiIoMmuOperationBusMasterCommonBuffer,
- *HostAddress,
- &NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+ Status = IoMmu->Map (
+ IoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ *HostAddress,
+ &NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
*HostAddress = NULL;
return EFI_OUT_OF_RESOURCES;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -178,7 +182,7 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
IoMmu->Unmap (IoMmu, *Mapping);
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
- *Mapping = NULL;
+ *Mapping = NULL;
*HostAddress = NULL;
return Status;
}
@@ -191,15 +195,15 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *) (UINTN) HostPhyAddress;
+
+ *HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
- *Mapping = NULL;
+ *Mapping = NULL;
}
+
return Status;
}
-
-
/**
Initialize IOMMU.
@@ -208,7 +212,7 @@ IoMmuAllocateBuffer ( **/
VOID
IoMmuInit (
- OUT EDKII_IOMMU_PPI **IoMmu
+ OUT EDKII_IOMMU_PPI **IoMmu
)
{
*IoMmu = NULL;
@@ -216,7 +220,6 @@ IoMmuInit ( &gEdkiiIoMmuPpiGuid,
0,
NULL,
- (VOID **) IoMmu
+ (VOID **)IoMmu
);
}
-
diff --git a/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.c b/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.c index a05834da3c..96abf3ab13 100644 --- a/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.c +++ b/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.c @@ -22,15 +22,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
UhciStopHc (
- IN USB_UHC_DEV *Uhc,
- IN UINTN Timeout
+ IN USB_UHC_DEV *Uhc,
+ IN UINTN Timeout
)
{
- UINT16 CommandContent;
- UINT16 UsbSts;
- UINTN Index;
+ UINT16 CommandContent;
+ UINT16 UsbSts;
+ UINTN Index;
- CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD);
+ CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD);
CommandContent &= USBCMD_RS;
USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent);
@@ -70,7 +70,7 @@ UhcEndOfPei ( IN VOID *Ppi
)
{
- USB_UHC_DEV *Uhc;
+ USB_UHC_DEV *Uhc;
Uhc = PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY (NotifyDescriptor);
@@ -95,18 +95,18 @@ UhcEndOfPei ( EFI_STATUS
EFIAPI
UhcPeimEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
- EFI_STATUS Status;
- UINT8 Index;
- UINTN ControllerType;
- UINTN BaseAddress;
- UINTN MemPages;
- USB_UHC_DEV *UhcDev;
- EFI_PHYSICAL_ADDRESS TempPtr;
+ PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
+ EFI_STATUS Status;
+ UINT8 Index;
+ UINTN ControllerType;
+ UINTN BaseAddress;
+ UINTN MemPages;
+ USB_UHC_DEV *UhcDev;
+ EFI_PHYSICAL_ADDRESS TempPtr;
//
// Shadow this PEIM to run from memory
@@ -119,7 +119,7 @@ UhcPeimEntry ( &gPeiUsbControllerPpiGuid,
0,
NULL,
- (VOID **) &ChipSetUsbControllerPpi
+ (VOID **)&ChipSetUsbControllerPpi
);
//
// If failed to locate, it is a bug in dispather as depex has gPeiUsbControllerPpiGuid.
@@ -129,7 +129,7 @@ UhcPeimEntry ( Index = 0;
while (TRUE) {
Status = ChipSetUsbControllerPpi->GetUsbController (
- (EFI_PEI_SERVICES **) PeiServices,
+ (EFI_PEI_SERVICES **)PeiServices,
ChipSetUsbControllerPpi,
Index,
&ControllerType,
@@ -161,10 +161,10 @@ UhcPeimEntry ( return EFI_OUT_OF_RESOURCES;
}
- UhcDev = (USB_UHC_DEV *) ((UINTN) TempPtr);
- UhcDev->Signature = USB_UHC_DEV_SIGNATURE;
+ UhcDev = (USB_UHC_DEV *)((UINTN)TempPtr);
+ UhcDev->Signature = USB_UHC_DEV_SIGNATURE;
IoMmuInit (&UhcDev->IoMmu);
- UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;
+ UhcDev->UsbHostControllerBaseAddress = (UINT32)BaseAddress;
//
// Init local memory management service
@@ -182,12 +182,12 @@ UhcPeimEntry ( return Status;
}
- UhcDev->UsbHostControllerPpi.ControlTransfer = UhcControlTransfer;
- UhcDev->UsbHostControllerPpi.BulkTransfer = UhcBulkTransfer;
- UhcDev->UsbHostControllerPpi.GetRootHubPortNumber = UhcGetRootHubPortNumber;
- UhcDev->UsbHostControllerPpi.GetRootHubPortStatus = UhcGetRootHubPortStatus;
- UhcDev->UsbHostControllerPpi.SetRootHubPortFeature = UhcSetRootHubPortFeature;
- UhcDev->UsbHostControllerPpi.ClearRootHubPortFeature = UhcClearRootHubPortFeature;
+ UhcDev->UsbHostControllerPpi.ControlTransfer = UhcControlTransfer;
+ UhcDev->UsbHostControllerPpi.BulkTransfer = UhcBulkTransfer;
+ UhcDev->UsbHostControllerPpi.GetRootHubPortNumber = UhcGetRootHubPortNumber;
+ UhcDev->UsbHostControllerPpi.GetRootHubPortStatus = UhcGetRootHubPortStatus;
+ UhcDev->UsbHostControllerPpi.SetRootHubPortFeature = UhcSetRootHubPortFeature;
+ UhcDev->UsbHostControllerPpi.ClearRootHubPortFeature = UhcClearRootHubPortFeature;
UhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
UhcDev->PpiDescriptor.Guid = &gPeiUsbHostControllerPpiGuid;
@@ -199,8 +199,8 @@ UhcPeimEntry ( continue;
}
- UhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- UhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
+ UhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+ UhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
UhcDev->EndOfPeiNotifyList.Notify = UhcEndOfPei;
PeiServicesNotifyPpi (&UhcDev->EndOfPeiNotifyList);
@@ -239,46 +239,47 @@ UhcPeimEntry ( EFI_STATUS
EFIAPI
UhcControlTransfer (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 DeviceAddress,
- IN UINT8 DeviceSpeed,
- IN UINT8 MaximumPacketLength,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN EFI_USB_DATA_DIRECTION TransferDirection,
- IN OUT VOID *Data OPTIONAL,
- IN OUT UINTN *DataLength OPTIONAL,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
- )
-{
- USB_UHC_DEV *UhcDev;
- UINT32 StatusReg;
- UINT8 PktID;
- QH_STRUCT *PtrQH;
- TD_STRUCT *PtrTD;
- TD_STRUCT *PtrPreTD;
- TD_STRUCT *PtrSetupTD;
- TD_STRUCT *PtrStatusTD;
- EFI_STATUS Status;
- UINT32 DataLen;
- UINT8 DataToggle;
- UINT8 *RequestPhy;
- VOID *RequestMap;
- UINT8 *DataPhy;
- VOID *DataMap;
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINT8 MaximumPacketLength,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN EFI_USB_DATA_DIRECTION TransferDirection,
+ IN OUT VOID *Data OPTIONAL,
+ IN OUT UINTN *DataLength OPTIONAL,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
+ )
+{
+ USB_UHC_DEV *UhcDev;
+ UINT32 StatusReg;
+ UINT8 PktID;
+ QH_STRUCT *PtrQH;
+ TD_STRUCT *PtrTD;
+ TD_STRUCT *PtrPreTD;
+ TD_STRUCT *PtrSetupTD;
+ TD_STRUCT *PtrStatusTD;
+ EFI_STATUS Status;
+ UINT32 DataLen;
+ UINT8 DataToggle;
+ UINT8 *RequestPhy;
+ VOID *RequestMap;
+ UINT8 *DataPhy;
+ VOID *DataMap;
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
- StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;
+ StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;
- PktID = INPUT_PACKET_ID;
+ PktID = INPUT_PACKET_ID;
- RequestMap = NULL;
+ RequestMap = NULL;
- if (Request == NULL || TransferResult == NULL) {
+ if ((Request == NULL) || (TransferResult == NULL)) {
return EFI_INVALID_PARAMETER;
}
+
//
// if errors exist that cause host controller halt,
// then return EFI_DEVICE_ERROR.
@@ -307,6 +308,7 @@ UhcControlTransfer ( if (RequestMap != NULL) {
IoMmuUnmap (UhcDev->IoMmu, RequestMap);
}
+
return Status;
}
@@ -321,9 +323,9 @@ UhcControlTransfer ( DeviceAddress,
0,
DeviceSpeed,
- (UINT8 *) Request,
+ (UINT8 *)Request,
RequestPhy,
- (UINT8) sizeof (EFI_USB_DEVICE_REQUEST),
+ (UINT8)sizeof (EFI_USB_DEVICE_REQUEST),
&PtrSetupTD
);
@@ -341,22 +343,22 @@ UhcControlTransfer ( if (TransferDirection == EfiUsbNoData) {
DataLen = 0;
} else {
- DataLen = (UINT32) *DataLength;
+ DataLen = (UINT32)*DataLength;
}
- DataToggle = 1;
+ DataToggle = 1;
- PtrTD = PtrSetupTD;
+ PtrTD = PtrSetupTD;
while (DataLen > 0) {
//
// create TD structures and link together
//
- UINT8 PacketSize;
+ UINT8 PacketSize;
//
// PacketSize is the data load size of each TD carries.
//
- PacketSize = (UINT8) DataLen;
+ PacketSize = (UINT8)DataLen;
if (DataLen > MaximumPacketLength) {
PacketSize = MaximumPacketLength;
}
@@ -381,9 +383,9 @@ UhcControlTransfer ( PtrPreTD = PtrTD;
DataToggle ^= 1;
- Data = (VOID *) ((UINT8 *) Data + PacketSize);
- DataPhy += PacketSize;
- DataLen -= PacketSize;
+ Data = (VOID *)((UINT8 *)Data + PacketSize);
+ DataPhy += PacketSize;
+ DataLen -= PacketSize;
}
//
@@ -399,6 +401,7 @@ UhcControlTransfer ( } else {
PktID = OUTPUT_PACKET_ID;
}
+
//
// create Status Stage TD structure
//
@@ -418,17 +421,17 @@ UhcControlTransfer ( // detail status is returned
//
Status = ExecuteControlTransfer (
- UhcDev,
- PtrSetupTD,
- DataLength,
- TimeOut,
- TransferResult
- );
+ UhcDev,
+ PtrSetupTD,
+ DataLength,
+ TimeOut,
+ TransferResult
+ );
//
// TRUE means must search other framelistindex
//
- SetQHVerticalValidorInvalid(PtrQH, FALSE);
+ SetQHVerticalValidorInvalid (PtrQH, FALSE);
DeleteQueuedTDs (UhcDev, PtrSetupTD);
//
@@ -436,7 +439,7 @@ UhcControlTransfer ( //
if (!IsStatusOK (UhcDev, StatusReg)) {
*TransferResult |= EFI_USB_ERR_SYSTEM;
- Status = EFI_DEVICE_ERROR;
+ Status = EFI_DEVICE_ERROR;
}
ClearStatusReg (UhcDev, StatusReg);
@@ -444,6 +447,7 @@ UhcControlTransfer ( if (DataMap != NULL) {
IoMmuUnmap (UhcDev->IoMmu, DataMap);
}
+
if (RequestMap != NULL) {
IoMmuUnmap (UhcDev->IoMmu, RequestMap);
}
@@ -483,42 +487,42 @@ UhcControlTransfer ( EFI_STATUS
EFIAPI
UhcBulkTransfer (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 MaximumPacketLength,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN OUT UINT8 *DataToggle,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 MaximumPacketLength,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN OUT UINT8 *DataToggle,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
)
{
- USB_UHC_DEV *UhcDev;
- UINT32 StatusReg;
+ USB_UHC_DEV *UhcDev;
+ UINT32 StatusReg;
- UINT32 DataLen;
+ UINT32 DataLen;
- QH_STRUCT *PtrQH;
- TD_STRUCT *PtrFirstTD;
- TD_STRUCT *PtrTD;
- TD_STRUCT *PtrPreTD;
+ QH_STRUCT *PtrQH;
+ TD_STRUCT *PtrFirstTD;
+ TD_STRUCT *PtrTD;
+ TD_STRUCT *PtrPreTD;
- UINT8 PktID;
+ UINT8 PktID;
- BOOLEAN IsFirstTD;
+ BOOLEAN IsFirstTD;
- EFI_STATUS Status;
+ EFI_STATUS Status;
EFI_USB_DATA_DIRECTION TransferDirection;
- BOOLEAN ShortPacketEnable;
+ BOOLEAN ShortPacketEnable;
- UINT16 CommandContent;
+ UINT16 CommandContent;
- UINT8 *DataPhy;
- VOID *DataMap;
+ UINT8 *DataPhy;
+ VOID *DataMap;
UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
@@ -533,16 +537,16 @@ UhcBulkTransfer ( USBWritePortW (UhcDev, UhcDev->UsbHostControllerBaseAddress + USBCMD, CommandContent);
}
- StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;
+ StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS;
//
// these code lines are added here per complier's strict demand
//
- PktID = INPUT_PACKET_ID;
- PtrTD = NULL;
- PtrFirstTD = NULL;
- PtrPreTD = NULL;
- DataLen = 0;
+ PktID = INPUT_PACKET_ID;
+ PtrTD = NULL;
+ PtrFirstTD = NULL;
+ PtrPreTD = NULL;
+ DataLen = 0;
ShortPacketEnable = FALSE;
@@ -554,15 +558,16 @@ UhcBulkTransfer ( return EFI_INVALID_PARAMETER;
}
- if (MaximumPacketLength != 8 && MaximumPacketLength != 16
- && MaximumPacketLength != 32 && MaximumPacketLength != 64) {
+ if ( (MaximumPacketLength != 8) && (MaximumPacketLength != 16)
+ && (MaximumPacketLength != 32) && (MaximumPacketLength != 64))
+ {
return EFI_INVALID_PARAMETER;
}
+
//
// if has errors that cause host controller halt, then return EFI_DEVICE_ERROR directly.
//
if (!IsStatusOK (UhcDev, StatusReg)) {
-
ClearStatusReg (UhcDev, StatusReg);
*TransferResult = EFI_USB_ERR_SYSTEM;
return EFI_DEVICE_ERROR;
@@ -586,7 +591,7 @@ UhcBulkTransfer ( return Status;
}
- DataLen = (UINT32) *DataLength;
+ DataLen = (UINT32)*DataLength;
PtrQH = UhcDev->BulkQH;
@@ -595,9 +600,9 @@ UhcBulkTransfer ( //
// create TD structures and link together
//
- UINT8 PacketSize;
+ UINT8 PacketSize;
- PacketSize = (UINT8) DataLen;
+ PacketSize = (UINT8)DataLen;
if (DataLen > MaximumPacketLength) {
PacketSize = MaximumPacketLength;
}
@@ -637,10 +642,11 @@ UhcBulkTransfer ( PtrPreTD = PtrTD;
*DataToggle ^= 1;
- Data = (VOID *) ((UINT8 *) Data + PacketSize);
- DataPhy += PacketSize;
- DataLen -= PacketSize;
+ Data = (VOID *)((UINT8 *)Data + PacketSize);
+ DataPhy += PacketSize;
+ DataLen -= PacketSize;
}
+
//
// link TD structures to QH structure
//
@@ -655,13 +661,13 @@ UhcBulkTransfer ( // of the last successful TD
//
Status = ExecBulkTransfer (
- UhcDev,
- PtrFirstTD,
- DataLength,
- DataToggle,
- TimeOut,
- TransferResult
- );
+ UhcDev,
+ PtrFirstTD,
+ DataLength,
+ DataToggle,
+ TimeOut,
+ TransferResult
+ );
//
// Delete Bulk transfer TD structure
@@ -673,7 +679,7 @@ UhcBulkTransfer ( //
if (!IsStatusOK (UhcDev, StatusReg)) {
*TransferResult |= EFI_USB_ERR_SYSTEM;
- Status = EFI_DEVICE_ERROR;
+ Status = EFI_DEVICE_ERROR;
}
ClearStatusReg (UhcDev, StatusReg);
@@ -700,15 +706,15 @@ UhcBulkTransfer ( EFI_STATUS
EFIAPI
UhcGetRootHubPortNumber (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- OUT UINT8 *PortNumber
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ OUT UINT8 *PortNumber
)
{
- USB_UHC_DEV *UhcDev;
- UINT32 PSAddr;
- UINT16 RHPortControl;
- UINT32 Index;
+ USB_UHC_DEV *UhcDev;
+ UINT32 PSAddr;
+ UINT16 RHPortControl;
+ UINT32 Index;
UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
@@ -719,7 +725,7 @@ UhcGetRootHubPortNumber ( *PortNumber = 0;
for (Index = 0; Index < 2; Index++) {
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2;
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2;
RHPortControl = USBReadPortW (UhcDev, PSAddr);
//
// Port Register content is valid
@@ -748,16 +754,16 @@ UhcGetRootHubPortNumber ( EFI_STATUS
EFIAPI
UhcGetRootHubPortStatus (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- OUT EFI_USB_PORT_STATUS *PortStatus
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- USB_UHC_DEV *UhcDev;
- UINT32 PSAddr;
- UINT16 RHPortStatus;
- UINT8 TotalPortNumber;
+ USB_UHC_DEV *UhcDev;
+ UINT32 PSAddr;
+ UINT16 RHPortStatus;
+ UINT8 TotalPortNumber;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
@@ -768,11 +774,11 @@ UhcGetRootHubPortStatus ( return EFI_INVALID_PARAMETER;
}
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;
- PortStatus->PortStatus = 0;
- PortStatus->PortChangeStatus = 0;
+ PortStatus->PortStatus = 0;
+ PortStatus->PortChangeStatus = 0;
RHPortStatus = USBReadPortW (UhcDev, PSAddr);
@@ -782,30 +788,35 @@ UhcGetRootHubPortStatus ( if ((RHPortStatus & USBPORTSC_CCS) != 0) {
PortStatus->PortStatus |= USB_PORT_STAT_CONNECTION;
}
+
//
// Port Enabled/Disabled
//
if ((RHPortStatus & USBPORTSC_PED) != 0) {
PortStatus->PortStatus |= USB_PORT_STAT_ENABLE;
}
+
//
// Port Suspend
//
if ((RHPortStatus & USBPORTSC_SUSP) != 0) {
PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;
}
+
//
// Port Reset
//
if ((RHPortStatus & USBPORTSC_PR) != 0) {
PortStatus->PortStatus |= USB_PORT_STAT_RESET;
}
+
//
// Low Speed Device Attached
//
if ((RHPortStatus & USBPORTSC_LSDA) != 0) {
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
}
+
//
// Fill Port Status Change bits
//
@@ -815,6 +826,7 @@ UhcGetRootHubPortStatus ( if ((RHPortStatus & USBPORTSC_CSC) != 0) {
PortStatus->PortChangeStatus |= USB_PORT_STAT_C_CONNECTION;
}
+
//
// Port Enabled/Disabled Change
//
@@ -841,59 +853,59 @@ UhcGetRootHubPortStatus ( EFI_STATUS
EFIAPI
UhcSetRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_UHC_DEV *UhcDev;
- UINT32 PSAddr;
- UINT32 CommandRegAddr;
- UINT16 RHPortControl;
- UINT8 TotalPortNumber;
+ USB_UHC_DEV *UhcDev;
+ UINT32 PSAddr;
+ UINT32 CommandRegAddr;
+ UINT16 RHPortControl;
+ UINT8 TotalPortNumber;
UhcGetRootHubPortNumber (PeiServices, This, &TotalPortNumber);
if (PortNumber > TotalPortNumber) {
return EFI_INVALID_PARAMETER;
}
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;
- CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD;
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;
+ CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD;
RHPortControl = USBReadPortW (UhcDev, PSAddr);
switch (PortFeature) {
+ case EfiUsbPortSuspend:
+ if ((USBReadPortW (UhcDev, CommandRegAddr) & USBCMD_EGSM) == 0) {
+ //
+ // if global suspend is not active, can set port suspend
+ //
+ RHPortControl &= 0xfff5;
+ RHPortControl |= USBPORTSC_SUSP;
+ }
- case EfiUsbPortSuspend:
- if ((USBReadPortW (UhcDev, CommandRegAddr) & USBCMD_EGSM) == 0) {
+ break;
+
+ case EfiUsbPortReset:
+ RHPortControl &= 0xfff5;
+ RHPortControl |= USBPORTSC_PR;
//
- // if global suspend is not active, can set port suspend
+ // Set the reset bit
//
- RHPortControl &= 0xfff5;
- RHPortControl |= USBPORTSC_SUSP;
- }
- break;
-
- case EfiUsbPortReset:
- RHPortControl &= 0xfff5;
- RHPortControl |= USBPORTSC_PR;
- //
- // Set the reset bit
- //
- break;
+ break;
- case EfiUsbPortPower:
- break;
+ case EfiUsbPortPower:
+ break;
- case EfiUsbPortEnable:
- RHPortControl &= 0xfff5;
- RHPortControl |= USBPORTSC_PED;
- break;
+ case EfiUsbPortEnable:
+ RHPortControl &= 0xfff5;
+ RHPortControl |= USBPORTSC_PED;
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
USBWritePortW (UhcDev, PSAddr, RHPortControl);
@@ -919,16 +931,16 @@ UhcSetRootHubPortFeature ( EFI_STATUS
EFIAPI
UhcClearRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_UHC_DEV *UhcDev;
- UINT32 PSAddr;
- UINT16 RHPortControl;
- UINT8 TotalPortNumber;
+ USB_UHC_DEV *UhcDev;
+ UINT32 PSAddr;
+ UINT16 RHPortControl;
+ UINT8 TotalPortNumber;
UhcGetRootHubPortNumber (PeiServices, This, &TotalPortNumber);
@@ -936,79 +948,79 @@ UhcClearRootHubPortFeature ( return EFI_INVALID_PARAMETER;
}
- UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
- PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;
+ UhcDev = PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS (This);
+ PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2;
RHPortControl = USBReadPortW (UhcDev, PSAddr);
switch (PortFeature) {
- //
- // clear PORT_ENABLE feature means disable port.
- //
- case EfiUsbPortEnable:
- RHPortControl &= 0xfff5;
- RHPortControl &= ~USBPORTSC_PED;
- break;
+ //
+ // clear PORT_ENABLE feature means disable port.
+ //
+ case EfiUsbPortEnable:
+ RHPortControl &= 0xfff5;
+ RHPortControl &= ~USBPORTSC_PED;
+ break;
- //
- // clear PORT_SUSPEND feature means resume the port.
- // (cause a resume on the specified port if in suspend mode)
- //
- case EfiUsbPortSuspend:
- RHPortControl &= 0xfff5;
- RHPortControl &= ~USBPORTSC_SUSP;
- break;
+ //
+ // clear PORT_SUSPEND feature means resume the port.
+ // (cause a resume on the specified port if in suspend mode)
+ //
+ case EfiUsbPortSuspend:
+ RHPortControl &= 0xfff5;
+ RHPortControl &= ~USBPORTSC_SUSP;
+ break;
- //
- // no operation
- //
- case EfiUsbPortPower:
- break;
+ //
+ // no operation
+ //
+ case EfiUsbPortPower:
+ break;
- //
- // clear PORT_RESET means clear the reset signal.
- //
- case EfiUsbPortReset:
- RHPortControl &= 0xfff5;
- RHPortControl &= ~USBPORTSC_PR;
- break;
+ //
+ // clear PORT_RESET means clear the reset signal.
+ //
+ case EfiUsbPortReset:
+ RHPortControl &= 0xfff5;
+ RHPortControl &= ~USBPORTSC_PR;
+ break;
- //
- // clear connect status change
- //
- case EfiUsbPortConnectChange:
- RHPortControl &= 0xfff5;
- RHPortControl |= USBPORTSC_CSC;
- break;
+ //
+ // clear connect status change
+ //
+ case EfiUsbPortConnectChange:
+ RHPortControl &= 0xfff5;
+ RHPortControl |= USBPORTSC_CSC;
+ break;
- //
- // clear enable/disable status change
- //
- case EfiUsbPortEnableChange:
- RHPortControl &= 0xfff5;
- RHPortControl |= USBPORTSC_PEDC;
- break;
+ //
+ // clear enable/disable status change
+ //
+ case EfiUsbPortEnableChange:
+ RHPortControl &= 0xfff5;
+ RHPortControl |= USBPORTSC_PEDC;
+ break;
- //
- // root hub does not support this request
- //
- case EfiUsbPortSuspendChange:
- break;
+ //
+ // root hub does not support this request
+ //
+ case EfiUsbPortSuspendChange:
+ break;
- //
- // root hub does not support this request
- //
- case EfiUsbPortOverCurrentChange:
- break;
+ //
+ // root hub does not support this request
+ //
+ case EfiUsbPortOverCurrentChange:
+ break;
- //
- // root hub does not support this request
- //
- case EfiUsbPortResetChange:
- break;
+ //
+ // root hub does not support this request
+ //
+ case EfiUsbPortResetChange:
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
USBWritePortW (UhcDev, PSAddr, RHPortControl);
@@ -1027,7 +1039,7 @@ UhcClearRootHubPortFeature ( **/
EFI_STATUS
InitializeUsbHC (
- IN USB_UHC_DEV *UhcDev
+ IN USB_UHC_DEV *UhcDev
)
{
EFI_STATUS Status;
@@ -1043,34 +1055,33 @@ InitializeUsbHC ( return Status;
}
- FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD;
- CommandReg = UhcDev->UsbHostControllerBaseAddress + USBCMD;
+ FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD;
+ CommandReg = UhcDev->UsbHostControllerBaseAddress + USBCMD;
//
// Set Frame List Base Address to the specific register to inform the hardware.
//
- SetFrameListBaseAddress (UhcDev, FrameListBaseAddrReg, (UINT32) (UINTN) (UhcDev->FrameListEntry));
+ SetFrameListBaseAddress (UhcDev, FrameListBaseAddrReg, (UINT32)(UINTN)(UhcDev->FrameListEntry));
- Command = USBReadPortW (UhcDev, CommandReg);
+ Command = USBReadPortW (UhcDev, CommandReg);
Command |= USBCMD_GRESET;
USBWritePortW (UhcDev, CommandReg, Command);
MicroSecondDelay (50 * 1000);
-
Command &= ~USBCMD_GRESET;
USBWritePortW (UhcDev, CommandReg, Command);
//
- //UHCI spec page120 reset recovery time
+ // UHCI spec page120 reset recovery time
//
MicroSecondDelay (20 * 1000);
//
// Set Run/Stop bit to 1.
//
- Command = USBReadPortW (UhcDev, CommandReg);
+ Command = USBReadPortW (UhcDev, CommandReg);
Command |= USBCMD_RS | USBCMD_MAXP;
USBWritePortW (UhcDev, CommandReg, Command);
@@ -1088,7 +1099,7 @@ InitializeUsbHC ( **/
EFI_STATUS
CreateFrameList (
- USB_UHC_DEV *UhcDev
+ USB_UHC_DEV *UhcDev
)
{
EFI_STATUS Status;
@@ -1111,28 +1122,30 @@ CreateFrameList ( }
//
- //Create Control QH and Bulk QH and link them into Framelist Entry
+ // Create Control QH and Bulk QH and link them into Framelist Entry
//
- Status = CreateQH(UhcDev, &UhcDev->ConfigQH);
+ Status = CreateQH (UhcDev, &UhcDev->ConfigQH);
if (Status != EFI_SUCCESS) {
return EFI_OUT_OF_RESOURCES;
}
+
ASSERT (UhcDev->ConfigQH != NULL);
- Status = CreateQH(UhcDev, &UhcDev->BulkQH);
+ Status = CreateQH (UhcDev, &UhcDev->BulkQH);
if (Status != EFI_SUCCESS) {
return EFI_OUT_OF_RESOURCES;
}
+
ASSERT (UhcDev->BulkQH != NULL);
//
- //Set the corresponding QH pointer
+ // Set the corresponding QH pointer
//
- SetQHHorizontalLinkPtr(UhcDev->ConfigQH, UhcDev->BulkQH);
+ SetQHHorizontalLinkPtr (UhcDev->ConfigQH, UhcDev->BulkQH);
SetQHHorizontalQHorTDSelect (UhcDev->ConfigQH, TRUE);
SetQHHorizontalValidorInvalid (UhcDev->ConfigQH, TRUE);
- UhcDev->FrameListEntry = (FRAMELIST_ENTRY *) ((UINTN) FrameListBaseAddr);
+ UhcDev->FrameListEntry = (FRAMELIST_ENTRY *)((UINTN)FrameListBaseAddr);
FrameListPtr = UhcDev->FrameListEntry;
@@ -1141,7 +1154,7 @@ CreateFrameList ( FrameListPtr->FrameListPtr = (UINT32)(UINTN)UhcDev->ConfigQH >> 4;
FrameListPtr->FrameListPtrQSelect = 1;
FrameListPtr->FrameListRsvd = 0;
- FrameListPtr ++;
+ FrameListPtr++;
}
return EFI_SUCCESS;
@@ -1158,8 +1171,8 @@ CreateFrameList ( **/
UINT16
USBReadPortW (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Port
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Port
)
{
return IoRead16 (Port);
@@ -1175,9 +1188,9 @@ USBReadPortW ( **/
VOID
USBWritePortW (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Port,
- IN UINT16 Data
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Port,
+ IN UINT16 Data
)
{
IoWrite16 (Port, Data);
@@ -1193,9 +1206,9 @@ USBWritePortW ( **/
VOID
USBWritePortDW (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Port,
- IN UINT32 Data
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Port,
+ IN UINT32 Data
)
{
IoWrite32 (Port, Data);
@@ -1210,8 +1223,8 @@ USBWritePortDW ( **/
VOID
ClearStatusReg (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 StatusAddr
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 StatusAddr
)
{
//
@@ -1232,8 +1245,8 @@ ClearStatusReg ( **/
BOOLEAN
IsStatusOK (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 StatusRegAddr
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 StatusRegAddr
)
{
UINT16 StatusValue;
@@ -1247,8 +1260,6 @@ IsStatusOK ( }
}
-
-
/**
Set Frame List Base Address.
@@ -1259,15 +1270,15 @@ IsStatusOK ( **/
VOID
SetFrameListBaseAddress (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 FrameListRegAddr,
- IN UINT32 Addr
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 FrameListRegAddr,
+ IN UINT32 Addr
)
{
//
// Sets value in the USB Frame List Base Address register.
//
- USBWritePortDW (UhcDev, FrameListRegAddr, (UINT32) (Addr & 0xFFFFF000));
+ USBWritePortDW (UhcDev, FrameListRegAddr, (UINT32)(Addr & 0xFFFFF000));
}
/**
@@ -1282,8 +1293,8 @@ SetFrameListBaseAddress ( **/
EFI_STATUS
CreateQH (
- IN USB_UHC_DEV *UhcDev,
- OUT QH_STRUCT **PtrQH
+ IN USB_UHC_DEV *UhcDev,
+ OUT QH_STRUCT **PtrQH
)
{
EFI_STATUS Status;
@@ -1291,10 +1302,11 @@ CreateQH ( //
// allocate align memory for QH_STRUCT
//
- Status = AllocateTDorQHStruct (UhcDev, sizeof(QH_STRUCT), (void **)PtrQH);
+ Status = AllocateTDorQHStruct (UhcDev, sizeof (QH_STRUCT), (void **)PtrQH);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// init each field of the QH_STRUCT
//
@@ -1322,11 +1334,9 @@ SetQHHorizontalLinkPtr ( // Only the highest 28bit of the address is valid
// (take 32bit address as an example).
//
- PtrQH->QueueHead.QHHorizontalPtr = (UINT32) (UINTN) PtrNext >> 4;
+ PtrQH->QueueHead.QHHorizontalPtr = (UINT32)(UINTN)PtrNext >> 4;
}
-
-
/**
Set a QH or TD horizontally to be connected with a specific QH.
@@ -1385,7 +1395,7 @@ SetQHVerticalLinkPtr ( // Only the highest 28bit of the address is valid
// (take 32bit address as an example).
//
- PtrQH->QueueHead.QHVerticalPtr = (UINT32) (UINTN) PtrNext >> 4;
+ PtrQH->QueueHead.QHVerticalPtr = (UINT32)(UINTN)PtrNext >> 4;
}
/**
@@ -1428,8 +1438,6 @@ SetQHVerticalValidorInvalid ( PtrQH->QueueHead.QHVerticalTerminate = IsValid ? 0 : 1;
}
-
-
/**
Allocate TD or QH Struct.
@@ -1443,21 +1451,21 @@ SetQHVerticalValidorInvalid ( **/
EFI_STATUS
AllocateTDorQHStruct (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Size,
- OUT VOID **PtrStruct
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Size,
+ OUT VOID **PtrStruct
)
{
EFI_STATUS Status;
- Status = EFI_SUCCESS;
- *PtrStruct = NULL;
+ Status = EFI_SUCCESS;
+ *PtrStruct = NULL;
Status = UhcAllocatePool (
- UhcDev,
- (UINT8 **) PtrStruct,
- Size
- );
+ UhcDev,
+ (UINT8 **)PtrStruct,
+ Size
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1479,15 +1487,16 @@ AllocateTDorQHStruct ( **/
EFI_STATUS
CreateTD (
- IN USB_UHC_DEV *UhcDev,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ OUT TD_STRUCT **PtrTD
)
{
EFI_STATUS Status;
+
//
// create memory for TD_STRUCT, and align the memory.
//
- Status = AllocateTDorQHStruct (UhcDev, sizeof(TD_STRUCT), (void **)PtrTD);
+ Status = AllocateTDorQHStruct (UhcDev, sizeof (TD_STRUCT), (void **)PtrTD);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1518,14 +1527,14 @@ CreateTD ( **/
EFI_STATUS
GenSetupStageTD (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 DevAddr,
- IN UINT8 Endpoint,
- IN UINT8 DeviceSpeed,
- IN UINT8 *DevRequest,
- IN UINT8 *RequestPhy,
- IN UINT8 RequestLen,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 DevAddr,
+ IN UINT8 Endpoint,
+ IN UINT8 DeviceSpeed,
+ IN UINT8 *DevRequest,
+ IN UINT8 *RequestPhy,
+ IN UINT8 RequestLen,
+ OUT TD_STRUCT **PtrTD
)
{
TD_STRUCT *TdStruct;
@@ -1564,14 +1573,15 @@ GenSetupStageTD ( // (TRUE - Slow Device; FALSE - Full Speed Device)
//
switch (DeviceSpeed) {
- case USB_SLOW_SPEED_DEVICE:
- SetTDLoworFullSpeedDevice (TdStruct, TRUE);
- break;
+ case USB_SLOW_SPEED_DEVICE:
+ SetTDLoworFullSpeedDevice (TdStruct, TRUE);
+ break;
- case USB_FULL_SPEED_DEVICE:
- SetTDLoworFullSpeedDevice (TdStruct, FALSE);
- break;
+ case USB_FULL_SPEED_DEVICE:
+ SetTDLoworFullSpeedDevice (TdStruct, FALSE);
+ break;
}
+
//
// Non isochronous transfer TD
//
@@ -1598,13 +1608,13 @@ GenSetupStageTD ( SetTDTokenPacketID (TdStruct, SETUP_PACKET_ID);
- TdStruct->PtrTDBuffer = (UINT8 *) DevRequest;
+ TdStruct->PtrTDBuffer = (UINT8 *)DevRequest;
TdStruct->TDBufferLength = RequestLen;
//
// Set the beginning address of the buffer that will be used
// during the transaction.
//
- TdStruct->TDData.TDBufferPtr = (UINT32) (UINTN) RequestPhy;
+ TdStruct->TDData.TDBufferPtr = (UINT32)(UINTN)RequestPhy;
*PtrTD = TdStruct;
@@ -1631,16 +1641,16 @@ GenSetupStageTD ( **/
EFI_STATUS
GenDataTD (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 DevAddr,
- IN UINT8 Endpoint,
- IN UINT8 *PtrData,
- IN UINT8 *DataPhy,
- IN UINT8 Len,
- IN UINT8 PktID,
- IN UINT8 Toggle,
- IN UINT8 DeviceSpeed,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 DevAddr,
+ IN UINT8 Endpoint,
+ IN UINT8 *PtrData,
+ IN UINT8 *DataPhy,
+ IN UINT8 Len,
+ IN UINT8 PktID,
+ IN UINT8 Toggle,
+ IN UINT8 DeviceSpeed,
+ OUT TD_STRUCT **PtrTD
)
{
TD_STRUCT *TdStruct;
@@ -1683,14 +1693,15 @@ GenDataTD ( // (TRUE - Slow Device; FALSE - Full Speed Device)
//
switch (DeviceSpeed) {
- case USB_SLOW_SPEED_DEVICE:
- SetTDLoworFullSpeedDevice (TdStruct, TRUE);
- break;
+ case USB_SLOW_SPEED_DEVICE:
+ SetTDLoworFullSpeedDevice (TdStruct, TRUE);
+ break;
- case USB_FULL_SPEED_DEVICE:
- SetTDLoworFullSpeedDevice (TdStruct, FALSE);
- break;
+ case USB_FULL_SPEED_DEVICE:
+ SetTDLoworFullSpeedDevice (TdStruct, FALSE);
+ break;
}
+
//
// Non isochronous transfer TD
//
@@ -1721,13 +1732,13 @@ GenDataTD ( SetTDTokenPacketID (TdStruct, PktID);
- TdStruct->PtrTDBuffer = (UINT8 *) PtrData;
+ TdStruct->PtrTDBuffer = (UINT8 *)PtrData;
TdStruct->TDBufferLength = Len;
//
// Set the beginning address of the buffer that will be used
// during the transaction.
//
- TdStruct->TDData.TDBufferPtr = (UINT32) (UINTN) DataPhy;
+ TdStruct->TDData.TDBufferPtr = (UINT32)(UINTN)DataPhy;
*PtrTD = TdStruct;
@@ -1750,12 +1761,12 @@ GenDataTD ( **/
EFI_STATUS
CreateStatusTD (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 DevAddr,
- IN UINT8 Endpoint,
- IN UINT8 PktID,
- IN UINT8 DeviceSpeed,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 DevAddr,
+ IN UINT8 Endpoint,
+ IN UINT8 PktID,
+ IN UINT8 DeviceSpeed,
+ OUT TD_STRUCT **PtrTD
)
{
TD_STRUCT *PtrTDStruct;
@@ -1794,14 +1805,15 @@ CreateStatusTD ( // (TRUE - Slow Device; FALSE - Full Speed Device)
//
switch (DeviceSpeed) {
- case USB_SLOW_SPEED_DEVICE:
- SetTDLoworFullSpeedDevice (PtrTDStruct, TRUE);
- break;
+ case USB_SLOW_SPEED_DEVICE:
+ SetTDLoworFullSpeedDevice (PtrTDStruct, TRUE);
+ break;
- case USB_FULL_SPEED_DEVICE:
- SetTDLoworFullSpeedDevice (PtrTDStruct, FALSE);
- break;
+ case USB_FULL_SPEED_DEVICE:
+ SetTDLoworFullSpeedDevice (PtrTDStruct, FALSE);
+ break;
}
+
//
// Non isochronous transfer TD
//
@@ -1828,7 +1840,7 @@ CreateStatusTD ( SetTDTokenPacketID (PtrTDStruct, PktID);
- PtrTDStruct->PtrTDBuffer = NULL;
+ PtrTDStruct->PtrTDBuffer = NULL;
PtrTDStruct->TDBufferLength = 0;
//
// Set the beginning address of the buffer that will be used
@@ -1850,8 +1862,8 @@ CreateStatusTD ( **/
VOID
SetTDLinkPtrValidorInvalid (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsValid
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsValid
)
{
//
@@ -1870,8 +1882,8 @@ SetTDLinkPtrValidorInvalid ( **/
VOID
SetTDLinkPtrQHorTDSelect (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsQH
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsQH
)
{
//
@@ -1889,8 +1901,8 @@ SetTDLinkPtrQHorTDSelect ( **/
VOID
SetTDLinkPtrDepthorBreadth (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsDepth
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsDepth
)
{
//
@@ -1909,15 +1921,15 @@ SetTDLinkPtrDepthorBreadth ( **/
VOID
SetTDLinkPtr (
- IN TD_STRUCT *PtrTDStruct,
- IN VOID *PtrNext
+ IN TD_STRUCT *PtrTDStruct,
+ IN VOID *PtrNext
)
{
//
// Set TD Link Pointer. Since QH,TD align on 16-byte boundaries,
// only the highest 28 bits are valid. (if take 32bit address as an example)
//
- PtrTDStruct->TDData.TDLinkPtr = (UINT32) (UINTN) PtrNext >> 4;
+ PtrTDStruct->TDData.TDLinkPtr = (UINT32)(UINTN)PtrNext >> 4;
}
/**
@@ -1930,18 +1942,16 @@ SetTDLinkPtr ( **/
VOID *
GetTDLinkPtr (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
//
// Get TD Link Pointer. Restore it back to 32bit
// (if take 32bit address as an example)
//
- return (VOID *) (UINTN) ((PtrTDStruct->TDData.TDLinkPtr) << 4);
+ return (VOID *)(UINTN)((PtrTDStruct->TDData.TDLinkPtr) << 4);
}
-
-
/**
Enable/Disable short packet detection mechanism.
@@ -1951,8 +1961,8 @@ GetTDLinkPtr ( **/
VOID
EnableorDisableTDShortPacket (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsEnable
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsEnable
)
{
//
@@ -1970,8 +1980,8 @@ EnableorDisableTDShortPacket ( **/
VOID
SetTDControlErrorCounter (
- IN TD_STRUCT *PtrTDStruct,
- IN UINT8 MaxErrors
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINT8 MaxErrors
)
{
//
@@ -1993,8 +2003,8 @@ SetTDControlErrorCounter ( **/
VOID
SetTDLoworFullSpeedDevice (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsLowSpeedDevice
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsLowSpeedDevice
)
{
//
@@ -2012,8 +2022,8 @@ SetTDLoworFullSpeedDevice ( **/
VOID
SetTDControlIsochronousorNot (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsIsochronous
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsIsochronous
)
{
//
@@ -2032,8 +2042,8 @@ SetTDControlIsochronousorNot ( **/
VOID
SetorClearTDControlIOC (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsSet
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsSet
)
{
//
@@ -2052,8 +2062,8 @@ SetorClearTDControlIOC ( **/
VOID
SetTDStatusActiveorInactive (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsActive
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsActive
)
{
//
@@ -2077,8 +2087,8 @@ SetTDStatusActiveorInactive ( **/
UINT16
SetTDTokenMaxLength (
- IN TD_STRUCT *PtrTDStruct,
- IN UINT16 MaxLen
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINT16 MaxLen
)
{
//
@@ -2102,7 +2112,7 @@ SetTDTokenMaxLength ( **/
VOID
SetTDTokenDataToggle1 (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
//
@@ -2119,7 +2129,7 @@ SetTDTokenDataToggle1 ( **/
VOID
SetTDTokenDataToggle0 (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
//
@@ -2137,14 +2147,14 @@ SetTDTokenDataToggle0 ( **/
VOID
SetTDTokenEndPoint (
- IN TD_STRUCT *PtrTDStruct,
- IN UINTN EndPoint
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINTN EndPoint
)
{
//
// Set EndPoint Number the TD is targeting at.
//
- PtrTDStruct->TDData.TDTokenEndPt = (UINT8) EndPoint;
+ PtrTDStruct->TDData.TDTokenEndPt = (UINT8)EndPoint;
}
/**
@@ -2156,14 +2166,14 @@ SetTDTokenEndPoint ( **/
VOID
SetTDTokenDeviceAddress (
- IN TD_STRUCT *PtrTDStruct,
- IN UINTN DevAddr
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINTN DevAddr
)
{
//
// Set Device Address the TD is targeting at.
//
- PtrTDStruct->TDData.TDTokenDevAddr = (UINT8) DevAddr;
+ PtrTDStruct->TDData.TDTokenDevAddr = (UINT8)DevAddr;
}
/**
@@ -2175,8 +2185,8 @@ SetTDTokenDeviceAddress ( **/
VOID
SetTDTokenPacketID (
- IN TD_STRUCT *PtrTDStruct,
- IN UINT8 PacketID
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINT8 PacketID
)
{
//
@@ -2195,16 +2205,16 @@ SetTDTokenPacketID ( **/
BOOLEAN
IsTDStatusActive (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
- UINT8 TDStatus;
+ UINT8 TDStatus;
//
// Detect whether the TD is active.
//
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);
- return (BOOLEAN) (TDStatus & 0x80);
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);
+ return (BOOLEAN)(TDStatus & 0x80);
}
/**
@@ -2217,16 +2227,16 @@ IsTDStatusActive ( **/
BOOLEAN
IsTDStatusStalled (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
- UINT8 TDStatus;
+ UINT8 TDStatus;
//
// Detect whether the device/endpoint addressed by this TD is stalled.
//
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);
- return (BOOLEAN) (TDStatus & 0x40);
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);
+ return (BOOLEAN)(TDStatus & 0x40);
}
/**
@@ -2239,16 +2249,16 @@ IsTDStatusStalled ( **/
BOOLEAN
IsTDStatusBufferError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
- UINT8 TDStatus;
+ UINT8 TDStatus;
//
// Detect whether Data Buffer Error is happened.
//
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);
- return (BOOLEAN) (TDStatus & 0x20);
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);
+ return (BOOLEAN)(TDStatus & 0x20);
}
/**
@@ -2261,16 +2271,16 @@ IsTDStatusBufferError ( **/
BOOLEAN
IsTDStatusBabbleError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
- UINT8 TDStatus;
+ UINT8 TDStatus;
//
// Detect whether Babble Error is happened.
//
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);
- return (BOOLEAN) (TDStatus & 0x10);
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);
+ return (BOOLEAN)(TDStatus & 0x10);
}
/**
@@ -2283,16 +2293,16 @@ IsTDStatusBabbleError ( **/
BOOLEAN
IsTDStatusNAKReceived (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
- UINT8 TDStatus;
+ UINT8 TDStatus;
//
// Detect whether NAK is received.
//
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);
- return (BOOLEAN) (TDStatus & 0x08);
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);
+ return (BOOLEAN)(TDStatus & 0x08);
}
/**
@@ -2305,16 +2315,16 @@ IsTDStatusNAKReceived ( **/
BOOLEAN
IsTDStatusCRCTimeOutError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
- UINT8 TDStatus;
+ UINT8 TDStatus;
//
// Detect whether CRC/Time Out Error is encountered.
//
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);
- return (BOOLEAN) (TDStatus & 0x04);
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);
+ return (BOOLEAN)(TDStatus & 0x04);
}
/**
@@ -2327,16 +2337,16 @@ IsTDStatusCRCTimeOutError ( **/
BOOLEAN
IsTDStatusBitStuffError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
- UINT8 TDStatus;
+ UINT8 TDStatus;
//
// Detect whether Bitstuff Error is received.
//
- TDStatus = (UINT8) (PtrTDStruct->TDData.TDStatus);
- return (BOOLEAN) (TDStatus & 0x02);
+ TDStatus = (UINT8)(PtrTDStruct->TDData.TDStatus);
+ return (BOOLEAN)(TDStatus & 0x02);
}
/**
@@ -2349,14 +2359,14 @@ IsTDStatusBitStuffError ( **/
UINT16
GetTDStatusActualLength (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
//
// Retrieve the actual number of bytes that were tansferred.
// the value is encoded as n-1. so return the decoded value.
//
- return (UINT16) ((PtrTDStruct->TDData.TDStatusActualLength) + 1);
+ return (UINT16)((PtrTDStruct->TDData.TDStatusActualLength) + 1);
}
/**
@@ -2369,7 +2379,7 @@ GetTDStatusActualLength ( **/
BOOLEAN
GetTDLinkPtrValidorInvalid (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
)
{
//
@@ -2381,7 +2391,6 @@ GetTDLinkPtrValidorInvalid ( } else {
return TRUE;
}
-
}
/**
@@ -2394,19 +2403,19 @@ GetTDLinkPtrValidorInvalid ( **/
UINTN
CountTDsNumber (
- IN TD_STRUCT *PtrFirstTD
+ IN TD_STRUCT *PtrFirstTD
)
{
- UINTN Number;
- TD_STRUCT *Ptr;
+ UINTN Number;
+ TD_STRUCT *Ptr;
//
// Count the queued TDs number.
//
- Number = 0;
- Ptr = PtrFirstTD;
+ Number = 0;
+ Ptr = PtrFirstTD;
while (Ptr != 0) {
- Ptr = (TD_STRUCT *) Ptr->PtrNextTD;
+ Ptr = (TD_STRUCT *)Ptr->PtrNextTD;
Number++;
}
@@ -2422,13 +2431,14 @@ CountTDsNumber ( **/
VOID
LinkTDToQH (
- IN QH_STRUCT *PtrQH,
- IN TD_STRUCT *PtrTD
+ IN QH_STRUCT *PtrQH,
+ IN TD_STRUCT *PtrTD
)
{
- if (PtrQH == NULL || PtrTD == NULL) {
- return ;
+ if ((PtrQH == NULL) || (PtrTD == NULL)) {
+ return;
}
+
//
// Validate QH Vertical Ptr field
//
@@ -2439,9 +2449,9 @@ LinkTDToQH ( //
SetQHVerticalQHorTDSelect (PtrQH, FALSE);
- SetQHVerticalLinkPtr (PtrQH, (VOID *) PtrTD);
+ SetQHVerticalLinkPtr (PtrQH, (VOID *)PtrTD);
- PtrQH->PtrDown = (VOID *) PtrTD;
+ PtrQH->PtrDown = (VOID *)PtrTD;
}
/**
@@ -2453,13 +2463,14 @@ LinkTDToQH ( **/
VOID
LinkTDToTD (
- IN TD_STRUCT *PtrPreTD,
- IN TD_STRUCT *PtrTD
+ IN TD_STRUCT *PtrPreTD,
+ IN TD_STRUCT *PtrTD
)
{
- if (PtrPreTD == NULL || PtrTD == NULL) {
- return ;
+ if ((PtrPreTD == NULL) || (PtrTD == NULL)) {
+ return;
}
+
//
// Depth first fashion
//
@@ -2477,9 +2488,9 @@ LinkTDToTD ( SetTDLinkPtr (PtrPreTD, PtrTD);
- PtrPreTD->PtrNextTD = (VOID *) PtrTD;
+ PtrPreTD->PtrNextTD = (VOID *)PtrTD;
- PtrTD->PtrNextTD = NULL;
+ PtrTD->PtrNextTD = NULL;
}
/**
@@ -2498,21 +2509,21 @@ LinkTDToTD ( **/
EFI_STATUS
ExecuteControlTransfer (
- IN USB_UHC_DEV *UhcDev,
- IN TD_STRUCT *PtrTD,
- OUT UINTN *ActualLen,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
+ IN USB_UHC_DEV *UhcDev,
+ IN TD_STRUCT *PtrTD,
+ OUT UINTN *ActualLen,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
)
{
- UINTN ErrTDPos;
- UINTN Delay;
- BOOLEAN InfiniteLoop;
+ UINTN ErrTDPos;
+ UINTN Delay;
+ BOOLEAN InfiniteLoop;
- ErrTDPos = 0;
- *TransferResult = EFI_USB_NOERROR;
- *ActualLen = 0;
- InfiniteLoop = FALSE;
+ ErrTDPos = 0;
+ *TransferResult = EFI_USB_NOERROR;
+ *ActualLen = 0;
+ InfiniteLoop = FALSE;
Delay = TimeOut * STALL_1_MILLI_SECOND;
//
@@ -2524,7 +2535,6 @@ ExecuteControlTransfer ( }
do {
-
CheckTDsResults (PtrTD, TransferResult, &ErrTDPos, ActualLen);
//
@@ -2533,9 +2543,9 @@ ExecuteControlTransfer ( if ((*TransferResult & EFI_USB_ERR_NOTEXECUTE) != EFI_USB_ERR_NOTEXECUTE) {
break;
}
+
MicroSecondDelay (STALL_1_MICRO_SECOND);
Delay--;
-
} while (InfiniteLoop || (Delay != 0));
if (*TransferResult != EFI_USB_NOERROR) {
@@ -2562,23 +2572,23 @@ ExecuteControlTransfer ( **/
EFI_STATUS
ExecBulkTransfer (
- IN USB_UHC_DEV *UhcDev,
- IN TD_STRUCT *PtrTD,
- IN OUT UINTN *ActualLen,
- IN UINT8 *DataToggle,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
+ IN USB_UHC_DEV *UhcDev,
+ IN TD_STRUCT *PtrTD,
+ IN OUT UINTN *ActualLen,
+ IN UINT8 *DataToggle,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
)
{
- UINTN ErrTDPos;
- UINTN ScrollNum;
- UINTN Delay;
- BOOLEAN InfiniteLoop;
+ UINTN ErrTDPos;
+ UINTN ScrollNum;
+ UINTN Delay;
+ BOOLEAN InfiniteLoop;
- ErrTDPos = 0;
- *TransferResult = EFI_USB_NOERROR;
- *ActualLen = 0;
- InfiniteLoop = FALSE;
+ ErrTDPos = 0;
+ *TransferResult = EFI_USB_NOERROR;
+ *ActualLen = 0;
+ InfiniteLoop = FALSE;
Delay = TimeOut * STALL_1_MILLI_SECOND;
//
@@ -2590,7 +2600,6 @@ ExecBulkTransfer ( }
do {
-
CheckTDsResults (PtrTD, TransferResult, &ErrTDPos, ActualLen);
//
// TD is inactive, thus meaning bulk transfer's end.
@@ -2598,9 +2607,9 @@ ExecBulkTransfer ( if ((*TransferResult & EFI_USB_ERR_NOTEXECUTE) != EFI_USB_ERR_NOTEXECUTE) {
break;
}
+
MicroSecondDelay (STALL_1_MICRO_SECOND);
Delay--;
-
} while (InfiniteLoop || (Delay != 0));
//
@@ -2615,9 +2624,9 @@ ExecBulkTransfer ( *DataToggle ^= 1;
}
- //
- // If error, wait 100ms to retry by upper layer
- //
+ //
+ // If error, wait 100ms to retry by upper layer
+ //
MicroSecondDelay (100 * 1000);
return EFI_DEVICE_ERROR;
}
@@ -2634,20 +2643,19 @@ ExecBulkTransfer ( **/
VOID
DeleteQueuedTDs (
- IN USB_UHC_DEV *UhcDev,
- IN TD_STRUCT *PtrFirstTD
+ IN USB_UHC_DEV *UhcDev,
+ IN TD_STRUCT *PtrFirstTD
)
{
- TD_STRUCT *Tptr1;
+ TD_STRUCT *Tptr1;
- TD_STRUCT *Tptr2;
+ TD_STRUCT *Tptr2;
Tptr1 = PtrFirstTD;
//
// Delete all the TDs in a queue.
//
while (Tptr1 != NULL) {
-
Tptr2 = Tptr1;
if (!GetTDLinkPtrValidorInvalid (Tptr2)) {
@@ -2659,10 +2667,10 @@ DeleteQueuedTDs ( Tptr1 = GetTDLinkPtr (Tptr2);
}
- UhcFreePool (UhcDev, (UINT8 *) Tptr2, sizeof (TD_STRUCT));
+ UhcFreePool (UhcDev, (UINT8 *)Tptr2, sizeof (TD_STRUCT));
}
- return ;
+ return;
}
/**
@@ -2678,13 +2686,13 @@ DeleteQueuedTDs ( **/
BOOLEAN
CheckTDsResults (
- IN TD_STRUCT *PtrTD,
- OUT UINT32 *Result,
- OUT UINTN *ErrTDPos,
- OUT UINTN *ActualTransferSize
+ IN TD_STRUCT *PtrTD,
+ OUT UINT32 *Result,
+ OUT UINTN *ErrTDPos,
+ OUT UINTN *ActualTransferSize
)
{
- UINTN Len;
+ UINTN Len;
*Result = EFI_USB_NOERROR;
*ErrTDPos = 0;
@@ -2695,7 +2703,6 @@ CheckTDsResults ( *ActualTransferSize = 0;
while (PtrTD != NULL) {
-
if (IsTDStatusActive (PtrTD)) {
*Result |= EFI_USB_ERR_NOTEXECUTE;
}
@@ -2723,10 +2730,11 @@ CheckTDsResults ( if (IsTDStatusBitStuffError (PtrTD)) {
*Result |= EFI_USB_ERR_BITSTUFF;
}
+
//
// Accumulate actual transferred data length in each TD.
//
- Len = GetTDStatusActualLength (PtrTD) & 0x7FF;
+ Len = GetTDStatusActualLength (PtrTD) & 0x7FF;
*ActualTransferSize += Len;
//
@@ -2736,7 +2744,7 @@ CheckTDsResults ( return FALSE;
}
- PtrTD = (TD_STRUCT *) (PtrTD->PtrNextTD);
+ PtrTD = (TD_STRUCT *)(PtrTD->PtrNextTD);
//
// Record the first Error TD's position in the queue,
// this value is zero-based.
@@ -2777,13 +2785,13 @@ CreateMemoryBlock ( // memory management header and bit array use 1 page
//
MemPages = MemoryBlockSizeInPages + 1;
- Status = IoMmuAllocateBuffer (
- UhcDev->IoMmu,
- MemPages,
- (VOID **) &TempPtr,
- &MappedAddr,
- &Mapping
- );
+ Status = IoMmuAllocateBuffer (
+ UhcDev->IoMmu,
+ MemPages,
+ (VOID **)&TempPtr,
+ &MappedAddr,
+ &Mapping
+ );
if (EFI_ERROR (Status) || (TempPtr == NULL)) {
return EFI_OUT_OF_RESOURCES;
}
@@ -2792,7 +2800,7 @@ CreateMemoryBlock ( ZeroMem (Ptr, MemPages * EFI_PAGE_SIZE);
- *MemoryHeader = (MEMORY_MANAGE_HEADER *) Ptr;
+ *MemoryHeader = (MEMORY_MANAGE_HEADER *)Ptr;
//
// adjust Ptr pointer to the next empty memory
//
@@ -2800,15 +2808,15 @@ CreateMemoryBlock ( //
// Set Bit Array initial address
//
- (*MemoryHeader)->BitArrayPtr = Ptr;
+ (*MemoryHeader)->BitArrayPtr = Ptr;
- (*MemoryHeader)->Next = NULL;
+ (*MemoryHeader)->Next = NULL;
//
// Memory block initial address
//
- Ptr = TempPtr;
- Ptr += EFI_PAGE_SIZE;
+ Ptr = TempPtr;
+ Ptr += EFI_PAGE_SIZE;
(*MemoryHeader)->MemoryBlockPtr = Ptr;
//
// set Memory block size
@@ -2833,15 +2841,15 @@ CreateMemoryBlock ( **/
EFI_STATUS
InitializeMemoryManagement (
- IN USB_UHC_DEV *UhcDev
+ IN USB_UHC_DEV *UhcDev
)
{
MEMORY_MANAGE_HEADER *MemoryHeader;
EFI_STATUS Status;
UINTN MemPages;
- MemPages = NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES;
- Status = CreateMemoryBlock (UhcDev, &MemoryHeader, MemPages);
+ MemPages = NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES;
+ Status = CreateMemoryBlock (UhcDev, &MemoryHeader, MemPages);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -2864,9 +2872,9 @@ InitializeMemoryManagement ( **/
EFI_STATUS
UhcAllocatePool (
- IN USB_UHC_DEV *UhcDev,
- OUT UINT8 **Pool,
- IN UINTN AllocSize
+ IN USB_UHC_DEV *UhcDev,
+ OUT UINT8 **Pool,
+ IN UINTN AllocSize
)
{
MEMORY_MANAGE_HEADER *MemoryHeader;
@@ -2891,16 +2899,16 @@ UhcAllocatePool ( Status = EFI_NOT_FOUND;
for (TempHeaderPtr = MemoryHeader; TempHeaderPtr != NULL; TempHeaderPtr = TempHeaderPtr->Next) {
-
Status = AllocMemInMemoryBlock (
- TempHeaderPtr,
- (VOID **) Pool,
- RealAllocSize / 32
- );
+ TempHeaderPtr,
+ (VOID **)Pool,
+ RealAllocSize / 32
+ );
if (!EFI_ERROR (Status)) {
return EFI_SUCCESS;
}
}
+
//
// There is no enough memory,
// Create a new Memory Block
@@ -2919,16 +2927,17 @@ UhcAllocatePool ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Link the new Memory Block to the Memory Header list
//
InsertMemoryHeaderToList (MemoryHeader, NewMemoryHeader);
Status = AllocMemInMemoryBlock (
- NewMemoryHeader,
- (VOID **) Pool,
- RealAllocSize / 32
- );
+ NewMemoryHeader,
+ (VOID **)Pool,
+ RealAllocSize / 32
+ );
return Status;
}
@@ -2950,21 +2959,21 @@ AllocMemInMemoryBlock ( IN UINTN NumberOfMemoryUnit
)
{
- UINTN TempBytePos;
- UINTN FoundBytePos;
- UINT8 Index;
- UINT8 FoundBitPos;
- UINT8 ByteValue;
- UINT8 BitValue;
- UINTN NumberOfZeros;
- UINTN Count;
+ UINTN TempBytePos;
+ UINTN FoundBytePos;
+ UINT8 Index;
+ UINT8 FoundBitPos;
+ UINT8 ByteValue;
+ UINT8 BitValue;
+ UINTN NumberOfZeros;
+ UINTN Count;
- FoundBytePos = 0;
- FoundBitPos = 0;
+ FoundBytePos = 0;
+ FoundBitPos = 0;
ByteValue = MemoryHeader->BitArrayPtr[0];
NumberOfZeros = 0;
- Index = 0;
+ Index = 0;
for (TempBytePos = 0; TempBytePos < MemoryHeader->BitArraySizeInBytes;) {
//
// Pop out BitValue from a byte in TempBytePos.
@@ -3001,10 +3010,11 @@ AllocMemInMemoryBlock ( //
// reset the (FoundBytePos,FoundBitPos) to the position of '1'
//
- FoundBytePos = TempBytePos;
- FoundBitPos = Index;
+ FoundBytePos = TempBytePos;
+ FoundBitPos = Index;
}
}
+
//
// right shift the byte
//
@@ -3020,14 +3030,15 @@ AllocMemInMemoryBlock ( // and reset the bit pos.
//
TempBytePos += 1;
- ByteValue = MemoryHeader->BitArrayPtr[TempBytePos];
- Index = 0;
+ ByteValue = MemoryHeader->BitArrayPtr[TempBytePos];
+ Index = 0;
}
}
if (NumberOfZeros < NumberOfMemoryUnit) {
return EFI_NOT_FOUND;
}
+
//
// Found enough free space.
//
@@ -3042,23 +3053,24 @@ AllocMemInMemoryBlock ( if ((MemoryHeader->BitArrayPtr[0] & BIT0) != 0) {
FoundBitPos += 1;
}
+
//
// Have the (FoundBytePos,FoundBitPos) make sense.
//
if (FoundBitPos > 7) {
FoundBytePos += 1;
- FoundBitPos -= 8;
+ FoundBitPos -= 8;
}
+
//
// Set the memory as allocated
//
for (TempBytePos = FoundBytePos, Index = FoundBitPos, Count = 0; Count < NumberOfMemoryUnit; Count++) {
-
- MemoryHeader->BitArrayPtr[TempBytePos] = (UINT8) (MemoryHeader->BitArrayPtr[TempBytePos] | (1 << Index));
+ MemoryHeader->BitArrayPtr[TempBytePos] = (UINT8)(MemoryHeader->BitArrayPtr[TempBytePos] | (1 << Index));
Index++;
if (Index == 8) {
TempBytePos += 1;
- Index = 0;
+ Index = 0;
}
}
@@ -3077,9 +3089,9 @@ AllocMemInMemoryBlock ( **/
VOID
UhcFreePool (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 *Pool,
- IN UINTN AllocSize
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 *Pool,
+ IN UINTN AllocSize
)
{
MEMORY_MANAGE_HEADER *MemoryHeader;
@@ -3103,38 +3115,37 @@ UhcFreePool ( }
for (TempHeaderPtr = MemoryHeader; TempHeaderPtr != NULL;
- TempHeaderPtr = TempHeaderPtr->Next) {
-
+ TempHeaderPtr = TempHeaderPtr->Next)
+ {
if ((Pool >= TempHeaderPtr->MemoryBlockPtr) &&
((Pool + RealAllocSize) <= (TempHeaderPtr->MemoryBlockPtr +
- TempHeaderPtr->MemoryBlockSizeInBytes))) {
-
+ TempHeaderPtr->MemoryBlockSizeInBytes)))
+ {
//
// Pool is in the Memory Block area,
// find the start byte and bit in the bit array
//
- StartBytePos = ((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) / 8;
- StartBitPos = (UINT8) (((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) % 8);
+ StartBytePos = ((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) / 8;
+ StartBitPos = (UINT8)(((Pool - TempHeaderPtr->MemoryBlockPtr) / 32) % 8);
//
// reset associated bits in bit array
//
for (Index = StartBytePos, Index2 = StartBitPos, Count = 0; Count < (RealAllocSize / 32); Count++) {
-
- TempHeaderPtr->BitArrayPtr[Index] = (UINT8) (TempHeaderPtr->BitArrayPtr[Index] ^ (1 << Index2));
+ TempHeaderPtr->BitArrayPtr[Index] = (UINT8)(TempHeaderPtr->BitArrayPtr[Index] ^ (1 << Index2));
Index2++;
if (Index2 == 8) {
Index += 1;
Index2 = 0;
}
}
+
//
// break the loop
//
break;
}
}
-
}
/**
@@ -3160,10 +3171,6 @@ InsertMemoryHeaderToList ( }
}
-
-
-
-
/**
Map address of request structure buffer.
@@ -3178,10 +3185,10 @@ InsertMemoryHeaderToList ( **/
EFI_STATUS
UhciMapUserRequest (
- IN USB_UHC_DEV *Uhc,
- IN OUT VOID *Request,
- OUT UINT8 **MappedAddr,
- OUT VOID **Map
+ IN USB_UHC_DEV *Uhc,
+ IN OUT VOID *Request,
+ OUT UINT8 **MappedAddr,
+ OUT VOID **Map
)
{
EFI_STATUS Status;
@@ -3199,7 +3206,7 @@ UhciMapUserRequest ( );
if (!EFI_ERROR (Status)) {
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;
}
return Status;
@@ -3237,61 +3244,60 @@ UhciMapUserData ( Status = EFI_SUCCESS;
switch (Direction) {
- case EfiUsbDataIn:
- //
- // BusMasterWrite means cpu read
- //
- *PktId = INPUT_PACKET_ID;
- Status = IoMmuMap (
- Uhc->IoMmu,
- EdkiiIoMmuOperationBusMasterWrite,
- Data,
- Len,
- &PhyAddr,
- Map
- );
-
- if (EFI_ERROR (Status)) {
- goto EXIT;
- }
+ case EfiUsbDataIn:
+ //
+ // BusMasterWrite means cpu read
+ //
+ *PktId = INPUT_PACKET_ID;
+ Status = IoMmuMap (
+ Uhc->IoMmu,
+ EdkiiIoMmuOperationBusMasterWrite,
+ Data,
+ Len,
+ &PhyAddr,
+ Map
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;
- break;
-
- case EfiUsbDataOut:
- *PktId = OUTPUT_PACKET_ID;
- Status = IoMmuMap (
- Uhc->IoMmu,
- EdkiiIoMmuOperationBusMasterRead,
- Data,
- Len,
- &PhyAddr,
- Map
- );
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;
+ break;
- if (EFI_ERROR (Status)) {
- goto EXIT;
- }
+ case EfiUsbDataOut:
+ *PktId = OUTPUT_PACKET_ID;
+ Status = IoMmuMap (
+ Uhc->IoMmu,
+ EdkiiIoMmuOperationBusMasterRead,
+ Data,
+ Len,
+ &PhyAddr,
+ Map
+ );
+
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
- *MappedAddr = (UINT8 *) (UINTN) PhyAddr;
- break;
+ *MappedAddr = (UINT8 *)(UINTN)PhyAddr;
+ break;
- case EfiUsbNoData:
- if ((Len != NULL) && (*Len != 0)) {
- Status = EFI_INVALID_PARAMETER;
- goto EXIT;
- }
+ case EfiUsbNoData:
+ if ((Len != NULL) && (*Len != 0)) {
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
- *PktId = OUTPUT_PACKET_ID;
- *MappedAddr = NULL;
- *Map = NULL;
- break;
+ *PktId = OUTPUT_PACKET_ID;
+ *MappedAddr = NULL;
+ *Map = NULL;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
EXIT:
return Status;
}
-
diff --git a/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.h b/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.h index 9100cbeabd..5b135f2558 100644 --- a/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.h +++ b/MdeModulePkg/Bus/Pci/UhciPei/UhcPeim.h @@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _RECOVERY_UHC_H_
#define _RECOVERY_UHC_H_
-
#include <PiPei.h>
#include <Ppi/UsbController.h>
@@ -26,39 +25,39 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/IoLib.h>
#include <Library/PeiServicesLib.h>
-#define USB_SLOW_SPEED_DEVICE 0x01
-#define USB_FULL_SPEED_DEVICE 0x02
+#define USB_SLOW_SPEED_DEVICE 0x01
+#define USB_FULL_SPEED_DEVICE 0x02
//
// One memory block uses 16 page
//
-#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16
-
-#define USBCMD 0 /* Command Register Offset 00-01h */
-#define USBCMD_RS BIT0 /* Run/Stop */
-#define USBCMD_HCRESET BIT1 /* Host reset */
-#define USBCMD_GRESET BIT2 /* Global reset */
-#define USBCMD_EGSM BIT3 /* Global Suspend Mode */
-#define USBCMD_FGR BIT4 /* Force Global Resume */
-#define USBCMD_SWDBG BIT5 /* SW Debug mode */
-#define USBCMD_CF BIT6 /* Config Flag (sw only) */
-#define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */
+#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16
+
+#define USBCMD 0 /* Command Register Offset 00-01h */
+#define USBCMD_RS BIT0 /* Run/Stop */
+#define USBCMD_HCRESET BIT1 /* Host reset */
+#define USBCMD_GRESET BIT2 /* Global reset */
+#define USBCMD_EGSM BIT3 /* Global Suspend Mode */
+#define USBCMD_FGR BIT4 /* Force Global Resume */
+#define USBCMD_SWDBG BIT5 /* SW Debug mode */
+#define USBCMD_CF BIT6 /* Config Flag (sw only) */
+#define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */
/* Status register */
-#define USBSTS 2 /* Status Register Offset 02-03h */
-#define USBSTS_USBINT BIT0 /* Interrupt due to IOC */
-#define USBSTS_ERROR BIT1 /* Interrupt due to error */
-#define USBSTS_RD BIT2 /* Resume Detect */
-#define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */
-#define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */
-#define USBSTS_HCH BIT5 /* HC Halted */
+#define USBSTS 2 /* Status Register Offset 02-03h */
+#define USBSTS_USBINT BIT0 /* Interrupt due to IOC */
+#define USBSTS_ERROR BIT1 /* Interrupt due to error */
+#define USBSTS_RD BIT2 /* Resume Detect */
+#define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */
+#define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */
+#define USBSTS_HCH BIT5 /* HC Halted */
/* Interrupt enable register */
-#define USBINTR 4 /* Interrupt Enable Register 04-05h */
-#define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */
-#define USBINTR_RESUME BIT1 /* Resume interrupt enable */
-#define USBINTR_IOC BIT2 /* Interrupt On Complete enable */
-#define USBINTR_SP BIT3 /* Short packet interrupt enable */
+#define USBINTR 4 /* Interrupt Enable Register 04-05h */
+#define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */
+#define USBINTR_RESUME BIT1 /* Resume interrupt enable */
+#define USBINTR_IOC BIT2 /* Interrupt On Complete enable */
+#define USBINTR_SP BIT3 /* Short packet interrupt enable */
/* Frame Number Register Offset 06-08h */
#define USBFRNUM 6
@@ -70,90 +69,89 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define USBSOF 0x0c
/* USB port status and control registers */
-#define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
-#define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
-
-#define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */
-#define USBPORTSC_CSC BIT1 /* Connect Status Change */
-#define USBPORTSC_PED BIT2 /* Port Enable / Disable */
-#define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */
-#define USBPORTSC_LSL BIT4 /* Line Status Low bit*/
-#define USBPORTSC_LSH BIT5 /* Line Status High bit*/
-#define USBPORTSC_RD BIT6 /* Resume Detect */
-#define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */
-#define USBPORTSC_PR BIT9 /* Port Reset */
-#define USBPORTSC_SUSP BIT12 /* Suspend */
-
-#define SETUP_PACKET_ID 0x2D
-#define INPUT_PACKET_ID 0x69
-#define OUTPUT_PACKET_ID 0xE1
-#define ERROR_PACKET_ID 0x55
+#define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
+#define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
+
+#define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */
+#define USBPORTSC_CSC BIT1 /* Connect Status Change */
+#define USBPORTSC_PED BIT2 /* Port Enable / Disable */
+#define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */
+#define USBPORTSC_LSL BIT4 /* Line Status Low bit*/
+#define USBPORTSC_LSH BIT5 /* Line Status High bit*/
+#define USBPORTSC_RD BIT6 /* Resume Detect */
+#define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */
+#define USBPORTSC_PR BIT9 /* Port Reset */
+#define USBPORTSC_SUSP BIT12 /* Suspend */
+
+#define SETUP_PACKET_ID 0x2D
+#define INPUT_PACKET_ID 0x69
+#define OUTPUT_PACKET_ID 0xE1
+#define ERROR_PACKET_ID 0x55
#define STALL_1_MICRO_SECOND 1
#define STALL_1_MILLI_SECOND 1000
-
#pragma pack(1)
typedef struct {
- UINT32 FrameListPtrTerminate : 1;
- UINT32 FrameListPtrQSelect : 1;
- UINT32 FrameListRsvd : 2;
- UINT32 FrameListPtr : 28;
+ UINT32 FrameListPtrTerminate : 1;
+ UINT32 FrameListPtrQSelect : 1;
+ UINT32 FrameListRsvd : 2;
+ UINT32 FrameListPtr : 28;
} FRAMELIST_ENTRY;
typedef struct {
- UINT32 QHHorizontalTerminate : 1;
- UINT32 QHHorizontalQSelect : 1;
- UINT32 QHHorizontalRsvd : 2;
- UINT32 QHHorizontalPtr : 28;
- UINT32 QHVerticalTerminate : 1;
- UINT32 QHVerticalQSelect : 1;
- UINT32 QHVerticalRsvd : 2;
- UINT32 QHVerticalPtr : 28;
+ UINT32 QHHorizontalTerminate : 1;
+ UINT32 QHHorizontalQSelect : 1;
+ UINT32 QHHorizontalRsvd : 2;
+ UINT32 QHHorizontalPtr : 28;
+ UINT32 QHVerticalTerminate : 1;
+ UINT32 QHVerticalQSelect : 1;
+ UINT32 QHVerticalRsvd : 2;
+ UINT32 QHVerticalPtr : 28;
} QUEUE_HEAD;
typedef struct {
- QUEUE_HEAD QueueHead;
- UINT32 Reserved1;
- UINT32 Reserved2;
- VOID *PtrNext;
- VOID *PtrDown;
- VOID *Reserved3;
- UINT32 Reserved4;
+ QUEUE_HEAD QueueHead;
+ UINT32 Reserved1;
+ UINT32 Reserved2;
+ VOID *PtrNext;
+ VOID *PtrDown;
+ VOID *Reserved3;
+ UINT32 Reserved4;
} QH_STRUCT;
typedef struct {
- UINT32 TDLinkPtrTerminate : 1;
- UINT32 TDLinkPtrQSelect : 1;
- UINT32 TDLinkPtrDepthSelect : 1;
- UINT32 TDLinkPtrRsvd : 1;
- UINT32 TDLinkPtr : 28;
- UINT32 TDStatusActualLength : 11;
- UINT32 TDStatusRsvd : 5;
- UINT32 TDStatus : 8;
- UINT32 TDStatusIOC : 1;
- UINT32 TDStatusIOS : 1;
- UINT32 TDStatusLS : 1;
- UINT32 TDStatusErr : 2;
- UINT32 TDStatusSPD : 1;
- UINT32 TDStatusRsvd2 : 2;
- UINT32 TDTokenPID : 8;
- UINT32 TDTokenDevAddr : 7;
- UINT32 TDTokenEndPt : 4;
- UINT32 TDTokenDataToggle : 1;
- UINT32 TDTokenRsvd : 1;
- UINT32 TDTokenMaxLen : 11;
- UINT32 TDBufferPtr;
+ UINT32 TDLinkPtrTerminate : 1;
+ UINT32 TDLinkPtrQSelect : 1;
+ UINT32 TDLinkPtrDepthSelect : 1;
+ UINT32 TDLinkPtrRsvd : 1;
+ UINT32 TDLinkPtr : 28;
+ UINT32 TDStatusActualLength : 11;
+ UINT32 TDStatusRsvd : 5;
+ UINT32 TDStatus : 8;
+ UINT32 TDStatusIOC : 1;
+ UINT32 TDStatusIOS : 1;
+ UINT32 TDStatusLS : 1;
+ UINT32 TDStatusErr : 2;
+ UINT32 TDStatusSPD : 1;
+ UINT32 TDStatusRsvd2 : 2;
+ UINT32 TDTokenPID : 8;
+ UINT32 TDTokenDevAddr : 7;
+ UINT32 TDTokenEndPt : 4;
+ UINT32 TDTokenDataToggle : 1;
+ UINT32 TDTokenRsvd : 1;
+ UINT32 TDTokenMaxLen : 11;
+ UINT32 TDBufferPtr;
} TD;
typedef struct {
- TD TDData;
- UINT8 *PtrTDBuffer;
- VOID *PtrNextTD;
- VOID *PtrNextQH;
- UINT16 TDBufferLength;
- UINT16 Reserved;
+ TD TDData;
+ UINT8 *PtrTDBuffer;
+ VOID *PtrNextTD;
+ VOID *PtrNextQH;
+ UINT16 TDBufferLength;
+ UINT16 Reserved;
} TD_STRUCT;
#pragma pack()
@@ -161,38 +159,37 @@ typedef struct { typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;
struct _MEMORY_MANAGE_HEADER {
- UINT8 *BitArrayPtr;
- UINTN BitArraySizeInBytes;
- UINT8 *MemoryBlockPtr;
- UINTN MemoryBlockSizeInBytes;
- MEMORY_MANAGE_HEADER *Next;
+ UINT8 *BitArrayPtr;
+ UINTN BitArraySizeInBytes;
+ UINT8 *MemoryBlockPtr;
+ UINTN MemoryBlockSizeInBytes;
+ MEMORY_MANAGE_HEADER *Next;
};
-#define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')
+#define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')
typedef struct {
- UINTN Signature;
- PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;
- EDKII_IOMMU_PPI *IoMmu;
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ UINTN Signature;
+ PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;
+ EDKII_IOMMU_PPI *IoMmu;
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
//
// EndOfPei callback is used to stop the UHC DMA operation
// after exit PEI phase.
//
- EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
- UINT32 UsbHostControllerBaseAddress;
- FRAMELIST_ENTRY *FrameListEntry;
- QH_STRUCT *ConfigQH;
- QH_STRUCT *BulkQH;
+ UINT32 UsbHostControllerBaseAddress;
+ FRAMELIST_ENTRY *FrameListEntry;
+ QH_STRUCT *ConfigQH;
+ QH_STRUCT *BulkQH;
//
// Header1 used for QH,TD memory blocks management
//
- MEMORY_MANAGE_HEADER *Header1;
-
+ MEMORY_MANAGE_HEADER *Header1;
} USB_UHC_DEV;
-#define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)
-#define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)
/**
Submits control transfer to a target USB device.
@@ -220,17 +217,17 @@ typedef struct { EFI_STATUS
EFIAPI
UhcControlTransfer (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI * This,
- IN UINT8 DeviceAddress,
- IN UINT8 DeviceSpeed,
- IN UINT8 MaximumPacketLength,
- IN EFI_USB_DEVICE_REQUEST * Request,
- IN EFI_USB_DATA_DIRECTION TransferDirection,
- IN OUT VOID *Data OPTIONAL,
- IN OUT UINTN *DataLength OPTIONAL,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINT8 MaximumPacketLength,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN EFI_USB_DATA_DIRECTION TransferDirection,
+ IN OUT VOID *Data OPTIONAL,
+ IN OUT UINTN *DataLength OPTIONAL,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
);
/**
@@ -263,16 +260,16 @@ UhcControlTransfer ( EFI_STATUS
EFIAPI
UhcBulkTransfer (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 MaximumPacketLength,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN OUT UINT8 *DataToggle,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 MaximumPacketLength,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN OUT UINT8 *DataToggle,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
);
/**
@@ -290,9 +287,9 @@ UhcBulkTransfer ( EFI_STATUS
EFIAPI
UhcGetRootHubPortNumber (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- OUT UINT8 *PortNumber
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ OUT UINT8 *PortNumber
);
/**
@@ -311,10 +308,10 @@ UhcGetRootHubPortNumber ( EFI_STATUS
EFIAPI
UhcGetRootHubPortStatus (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- OUT EFI_USB_PORT_STATUS *PortStatus
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ OUT EFI_USB_PORT_STATUS *PortStatus
);
/**
@@ -333,10 +330,10 @@ UhcGetRootHubPortStatus ( EFI_STATUS
EFIAPI
UhcSetRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
);
/**
@@ -357,10 +354,10 @@ UhcSetRootHubPortFeature ( EFI_STATUS
EFIAPI
UhcClearRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
);
/**
@@ -374,7 +371,7 @@ UhcClearRootHubPortFeature ( **/
EFI_STATUS
InitializeUsbHC (
- IN USB_UHC_DEV *UhcDev
+ IN USB_UHC_DEV *UhcDev
);
/**
@@ -388,7 +385,7 @@ InitializeUsbHC ( **/
EFI_STATUS
CreateFrameList (
- USB_UHC_DEV *UhcDev
+ USB_UHC_DEV *UhcDev
);
/**
@@ -402,8 +399,8 @@ CreateFrameList ( **/
UINT16
USBReadPortW (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Port
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Port
);
/**
@@ -416,9 +413,9 @@ USBReadPortW ( **/
VOID
USBWritePortW (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Port,
- IN UINT16 Data
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Port,
+ IN UINT16 Data
);
/**
@@ -431,9 +428,9 @@ USBWritePortW ( **/
VOID
USBWritePortDW (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Port,
- IN UINT32 Data
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Port,
+ IN UINT32 Data
);
/**
@@ -445,8 +442,8 @@ USBWritePortDW ( **/
VOID
ClearStatusReg (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 StatusAddr
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 StatusAddr
);
/**
@@ -461,8 +458,8 @@ ClearStatusReg ( **/
BOOLEAN
IsStatusOK (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 StatusRegAddr
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 StatusRegAddr
);
/**
@@ -475,9 +472,9 @@ IsStatusOK ( **/
VOID
SetFrameListBaseAddress (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 FrameListRegAddr,
- IN UINT32 Addr
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 FrameListRegAddr,
+ IN UINT32 Addr
);
/**
@@ -574,7 +571,6 @@ SetQHVerticalValidorInvalid ( IN BOOLEAN IsValid
);
-
/**
Allocate TD or QH Struct.
@@ -588,9 +584,9 @@ SetQHVerticalValidorInvalid ( **/
EFI_STATUS
AllocateTDorQHStruct (
- IN USB_UHC_DEV *UhcDev,
- IN UINT32 Size,
- OUT VOID **PtrStruct
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT32 Size,
+ OUT VOID **PtrStruct
);
/**
@@ -605,8 +601,8 @@ AllocateTDorQHStruct ( **/
EFI_STATUS
CreateTD (
- IN USB_UHC_DEV *UhcDev,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ OUT TD_STRUCT **PtrTD
);
/**
@@ -627,14 +623,14 @@ CreateTD ( **/
EFI_STATUS
GenSetupStageTD (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 DevAddr,
- IN UINT8 Endpoint,
- IN UINT8 DeviceSpeed,
- IN UINT8 *DevRequest,
- IN UINT8 *RequestPhy,
- IN UINT8 RequestLen,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 DevAddr,
+ IN UINT8 Endpoint,
+ IN UINT8 DeviceSpeed,
+ IN UINT8 *DevRequest,
+ IN UINT8 *RequestPhy,
+ IN UINT8 RequestLen,
+ OUT TD_STRUCT **PtrTD
);
/**
@@ -657,16 +653,16 @@ GenSetupStageTD ( **/
EFI_STATUS
GenDataTD (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 DevAddr,
- IN UINT8 Endpoint,
- IN UINT8 *PtrData,
- IN UINT8 *DataPhy,
- IN UINT8 Len,
- IN UINT8 PktID,
- IN UINT8 Toggle,
- IN UINT8 DeviceSpeed,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 DevAddr,
+ IN UINT8 Endpoint,
+ IN UINT8 *PtrData,
+ IN UINT8 *DataPhy,
+ IN UINT8 Len,
+ IN UINT8 PktID,
+ IN UINT8 Toggle,
+ IN UINT8 DeviceSpeed,
+ OUT TD_STRUCT **PtrTD
);
/**
@@ -685,12 +681,12 @@ GenDataTD ( **/
EFI_STATUS
CreateStatusTD (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 DevAddr,
- IN UINT8 Endpoint,
- IN UINT8 PktID,
- IN UINT8 DeviceSpeed,
- OUT TD_STRUCT **PtrTD
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 DevAddr,
+ IN UINT8 Endpoint,
+ IN UINT8 PktID,
+ IN UINT8 DeviceSpeed,
+ OUT TD_STRUCT **PtrTD
);
/**
@@ -702,8 +698,8 @@ CreateStatusTD ( **/
VOID
SetTDLinkPtrValidorInvalid (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsValid
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsValid
);
/**
@@ -715,8 +711,8 @@ SetTDLinkPtrValidorInvalid ( **/
VOID
SetTDLinkPtrQHorTDSelect (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsQH
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsQH
);
/**
@@ -728,8 +724,8 @@ SetTDLinkPtrQHorTDSelect ( **/
VOID
SetTDLinkPtrDepthorBreadth (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsDepth
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsDepth
);
/**
@@ -741,8 +737,8 @@ SetTDLinkPtrDepthorBreadth ( **/
VOID
SetTDLinkPtr (
- IN TD_STRUCT *PtrTDStruct,
- IN VOID *PtrNext
+ IN TD_STRUCT *PtrTDStruct,
+ IN VOID *PtrNext
);
/**
@@ -753,12 +749,11 @@ SetTDLinkPtr ( @retval Get TD Link Pointer in TD.
**/
-VOID*
+VOID *
GetTDLinkPtr (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
-
/**
Enable/Disable short packet detection mechanism.
@@ -768,8 +763,8 @@ GetTDLinkPtr ( **/
VOID
EnableorDisableTDShortPacket (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsEnable
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsEnable
);
/**
@@ -781,8 +776,8 @@ EnableorDisableTDShortPacket ( **/
VOID
SetTDControlErrorCounter (
- IN TD_STRUCT *PtrTDStruct,
- IN UINT8 MaxErrors
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINT8 MaxErrors
);
/**
@@ -794,8 +789,8 @@ SetTDControlErrorCounter ( **/
VOID
SetTDLoworFullSpeedDevice (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsLowSpeedDevice
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsLowSpeedDevice
);
/**
@@ -807,8 +802,8 @@ SetTDLoworFullSpeedDevice ( **/
VOID
SetTDControlIsochronousorNot (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsIsochronous
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsIsochronous
);
/**
@@ -821,8 +816,8 @@ SetTDControlIsochronousorNot ( **/
VOID
SetorClearTDControlIOC (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsSet
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsSet
);
/**
@@ -834,8 +829,8 @@ SetorClearTDControlIOC ( **/
VOID
SetTDStatusActiveorInactive (
- IN TD_STRUCT *PtrTDStruct,
- IN BOOLEAN IsActive
+ IN TD_STRUCT *PtrTDStruct,
+ IN BOOLEAN IsActive
);
/**
@@ -848,8 +843,8 @@ SetTDStatusActiveorInactive ( **/
UINT16
SetTDTokenMaxLength (
- IN TD_STRUCT *PtrTDStruct,
- IN UINT16 MaxLen
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINT16 MaxLen
);
/**
@@ -860,7 +855,7 @@ SetTDTokenMaxLength ( **/
VOID
SetTDTokenDataToggle1 (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -871,7 +866,7 @@ SetTDTokenDataToggle1 ( **/
VOID
SetTDTokenDataToggle0 (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -883,8 +878,8 @@ SetTDTokenDataToggle0 ( **/
VOID
SetTDTokenEndPoint (
- IN TD_STRUCT *PtrTDStruct,
- IN UINTN EndPoint
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINTN EndPoint
);
/**
@@ -896,8 +891,8 @@ SetTDTokenEndPoint ( **/
VOID
SetTDTokenDeviceAddress (
- IN TD_STRUCT *PtrTDStruct,
- IN UINTN DevAddr
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINTN DevAddr
);
/**
@@ -909,8 +904,8 @@ SetTDTokenDeviceAddress ( **/
VOID
SetTDTokenPacketID (
- IN TD_STRUCT *PtrTDStruct,
- IN UINT8 PacketID
+ IN TD_STRUCT *PtrTDStruct,
+ IN UINT8 PacketID
);
/**
@@ -922,7 +917,7 @@ SetTDTokenPacketID ( **/
VOID
SetTDDataBuffer (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -935,7 +930,7 @@ SetTDDataBuffer ( **/
BOOLEAN
IsTDStatusActive (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -948,7 +943,7 @@ IsTDStatusActive ( **/
BOOLEAN
IsTDStatusStalled (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -961,7 +956,7 @@ IsTDStatusStalled ( **/
BOOLEAN
IsTDStatusBufferError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -974,7 +969,7 @@ IsTDStatusBufferError ( **/
BOOLEAN
IsTDStatusBabbleError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -987,7 +982,7 @@ IsTDStatusBabbleError ( **/
BOOLEAN
IsTDStatusNAKReceived (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -1000,7 +995,7 @@ IsTDStatusNAKReceived ( **/
BOOLEAN
IsTDStatusCRCTimeOutError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -1013,7 +1008,7 @@ IsTDStatusCRCTimeOutError ( **/
BOOLEAN
IsTDStatusBitStuffError (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -1026,7 +1021,7 @@ IsTDStatusBitStuffError ( **/
UINT16
GetTDStatusActualLength (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -1039,7 +1034,7 @@ GetTDStatusActualLength ( **/
BOOLEAN
GetTDLinkPtrValidorInvalid (
- IN TD_STRUCT *PtrTDStruct
+ IN TD_STRUCT *PtrTDStruct
);
/**
@@ -1052,7 +1047,7 @@ GetTDLinkPtrValidorInvalid ( **/
UINTN
CountTDsNumber (
- IN TD_STRUCT *PtrFirstTD
+ IN TD_STRUCT *PtrFirstTD
);
/**
@@ -1064,8 +1059,8 @@ CountTDsNumber ( **/
VOID
LinkTDToQH (
- IN QH_STRUCT *PtrQH,
- IN TD_STRUCT *PtrTD
+ IN QH_STRUCT *PtrQH,
+ IN TD_STRUCT *PtrTD
);
/**
@@ -1077,8 +1072,8 @@ LinkTDToQH ( **/
VOID
LinkTDToTD (
- IN TD_STRUCT *PtrPreTD,
- IN TD_STRUCT *PtrTD
+ IN TD_STRUCT *PtrPreTD,
+ IN TD_STRUCT *PtrTD
);
/**
@@ -1097,11 +1092,11 @@ LinkTDToTD ( **/
EFI_STATUS
ExecuteControlTransfer (
- IN USB_UHC_DEV *UhcDev,
- IN TD_STRUCT *PtrTD,
- OUT UINTN *ActualLen,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
+ IN USB_UHC_DEV *UhcDev,
+ IN TD_STRUCT *PtrTD,
+ OUT UINTN *ActualLen,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
);
/**
@@ -1121,12 +1116,12 @@ ExecuteControlTransfer ( **/
EFI_STATUS
ExecBulkTransfer (
- IN USB_UHC_DEV *UhcDev,
- IN TD_STRUCT *PtrTD,
- IN OUT UINTN *ActualLen,
- IN UINT8 *DataToggle,
- IN UINTN TimeOut,
- OUT UINT32 *TransferResult
+ IN USB_UHC_DEV *UhcDev,
+ IN TD_STRUCT *PtrTD,
+ IN OUT UINTN *ActualLen,
+ IN UINT8 *DataToggle,
+ IN UINTN TimeOut,
+ OUT UINT32 *TransferResult
);
/**
@@ -1138,8 +1133,8 @@ ExecBulkTransfer ( **/
VOID
DeleteQueuedTDs (
- IN USB_UHC_DEV *UhcDev,
- IN TD_STRUCT *PtrFirstTD
+ IN USB_UHC_DEV *UhcDev,
+ IN TD_STRUCT *PtrFirstTD
);
/**
@@ -1155,10 +1150,10 @@ DeleteQueuedTDs ( **/
BOOLEAN
CheckTDsResults (
- IN TD_STRUCT *PtrTD,
- OUT UINT32 *Result,
- OUT UINTN *ErrTDPos,
- OUT UINTN *ActualTransferSize
+ IN TD_STRUCT *PtrTD,
+ OUT UINT32 *Result,
+ OUT UINTN *ErrTDPos,
+ OUT UINTN *ActualTransferSize
);
/**
@@ -1190,7 +1185,7 @@ CreateMemoryBlock ( **/
EFI_STATUS
InitializeMemoryManagement (
- IN USB_UHC_DEV *UhcDev
+ IN USB_UHC_DEV *UhcDev
);
/**
@@ -1206,9 +1201,9 @@ InitializeMemoryManagement ( **/
EFI_STATUS
UhcAllocatePool (
- IN USB_UHC_DEV *UhcDev,
- OUT UINT8 **Pool,
- IN UINTN AllocSize
+ IN USB_UHC_DEV *UhcDev,
+ OUT UINT8 **Pool,
+ IN UINTN AllocSize
);
/**
@@ -1239,9 +1234,9 @@ AllocMemInMemoryBlock ( **/
VOID
UhcFreePool (
- IN USB_UHC_DEV *UhcDev,
- IN UINT8 *Pool,
- IN UINTN AllocSize
+ IN USB_UHC_DEV *UhcDev,
+ IN UINT8 *Pool,
+ IN UINTN AllocSize
);
/**
@@ -1257,7 +1252,6 @@ InsertMemoryHeaderToList ( IN MEMORY_MANAGE_HEADER *NewMemoryHeader
);
-
/**
Map address of request structure buffer.
@@ -1272,10 +1266,10 @@ InsertMemoryHeaderToList ( **/
EFI_STATUS
UhciMapUserRequest (
- IN USB_UHC_DEV *Uhc,
- IN OUT VOID *Request,
- OUT UINT8 **MappedAddr,
- OUT VOID **Map
+ IN USB_UHC_DEV *Uhc,
+ IN OUT VOID *Request,
+ OUT UINT8 **MappedAddr,
+ OUT VOID **Map
);
/**
@@ -1343,8 +1337,8 @@ IoMmuMap ( **/
VOID
IoMmuUnmap (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN VOID *Mapping
);
/**
@@ -1375,7 +1369,6 @@ IoMmuAllocateBuffer ( OUT VOID **Mapping
);
-
/**
Initialize IOMMU.
@@ -1384,7 +1377,7 @@ IoMmuAllocateBuffer ( **/
VOID
IoMmuInit (
- OUT EDKII_IOMMU_PPI **IoMmu
+ OUT EDKII_IOMMU_PPI **IoMmu
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c index 9e2697b822..e3af49c8c9 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c @@ -21,15 +21,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName = //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) XhciComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) XhciComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)XhciComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)XhciComponentNameGetControllerName,
"en"
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
{ "eng;en", L"Usb Xhci Driver" },
- { NULL , NULL }
+ { NULL, NULL }
};
/**
@@ -166,9 +166,9 @@ XhciComponentNameGetControllerName ( OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
- EFI_USB2_HC_PROTOCOL *Usb2Hc;
- USB_XHCI_INSTANCE *XhciDev;
+ EFI_STATUS Status;
+ EFI_USB2_HC_PROTOCOL *Usb2Hc;
+ USB_XHCI_INSTANCE *XhciDev;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -195,7 +195,7 @@ XhciComponentNameGetControllerName ( Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
gXhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -213,5 +213,4 @@ XhciComponentNameGetControllerName ( ControllerName,
(BOOLEAN)(This == &gXhciComponentName)
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h index 13fbde1658..103ad60575 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h @@ -57,7 +57,6 @@ XhciComponentNameGetDriverName ( OUT CHAR16 **DriverName
);
-
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -137,4 +136,3 @@ XhciComponentNameGetControllerName ( );
#endif
-
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c index 005820e011..99fb3521d5 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c @@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#include "Xhci.h"
-
/**
Allocate a block of memory to be used by the buffer pool.
@@ -22,17 +20,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Pages
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Pages
)
{
- USBHC_MEM_BLOCK *Block;
- EFI_PCI_IO_PROTOCOL *PciIo;
- VOID *BufHost;
- VOID *Mapping;
- EFI_PHYSICAL_ADDRESS MappedAddr;
- UINTN Bytes;
- EFI_STATUS Status;
+ USBHC_MEM_BLOCK *Block;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ UINTN Bytes;
+ EFI_STATUS Status;
PciIo = Pool->PciIo;
@@ -47,9 +45,9 @@ UsbHcAllocMemBlock ( //
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
- Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
- Block->Bits = AllocateZeroPool (Block->BitsLen);
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
+ Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
@@ -73,7 +71,7 @@ UsbHcAllocMemBlock ( goto FREE_BITARRAY;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -87,9 +85,9 @@ UsbHcAllocMemBlock ( goto FREE_BUFFER;
}
- Block->BufHost = BufHost;
- Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
- Block->Mapping = Mapping;
+ Block->BufHost = BufHost;
+ Block->Buf = (UINT8 *)((UINTN)MappedAddr);
+ Block->Mapping = Mapping;
return Block;
@@ -102,7 +100,6 @@ FREE_BITARRAY: return NULL;
}
-
/**
Free the memory block from the memory pool.
@@ -112,11 +109,11 @@ FREE_BITARRAY: **/
VOID
UsbHcFreeMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -132,7 +129,6 @@ UsbHcFreeMemBlock ( gBS->FreePool (Block);
}
-
/**
Alloc some memory from the block.
@@ -145,22 +141,22 @@ UsbHcFreeMemBlock ( **/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -176,13 +172,12 @@ UsbHcAllocMemFromBlock ( }
NEXT_BIT (Byte, Bit);
-
} else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -193,13 +188,13 @@ UsbHcAllocMemFromBlock ( //
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -218,16 +213,16 @@ UsbHcAllocMemFromBlock ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -241,7 +236,7 @@ UsbHcGetPciAddrForHostAddr ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -250,8 +245,8 @@ UsbHcGetPciAddrForHostAddr ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -267,16 +262,16 @@ UsbHcGetPciAddrForHostAddr ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS HostAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS HostAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -290,7 +285,7 @@ UsbHcGetHostAddrForPciAddr ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->Buf <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
+ if ((Block->Buf <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
break;
}
}
@@ -299,8 +294,8 @@ UsbHcGetHostAddrForPciAddr ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->Buf;
- HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->BufHost + Offset);
+ Offset = (UINT8 *)Mem - Block->Buf;
+ HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->BufHost + Offset);
return HostAddr;
}
@@ -313,8 +308,8 @@ UsbHcGetHostAddrForPciAddr ( **/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -322,7 +317,6 @@ UsbHcInsertMemBlockToPool ( Head->Next = Block;
}
-
/**
Is the memory block empty?
@@ -334,10 +328,10 @@ UsbHcInsertMemBlockToPool ( **/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -348,7 +342,6 @@ UsbHcIsMemBlockEmpty ( return TRUE;
}
-
/**
Unlink the memory block from the pool's list.
@@ -358,11 +351,11 @@ UsbHcIsMemBlockEmpty ( **/
VOID
UsbHcUnlinkMemBlock (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *BlockToUnlink
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -375,7 +368,6 @@ UsbHcUnlinkMemBlock ( }
}
-
/**
Initialize the memory management pool for the host controller.
@@ -390,7 +382,7 @@ UsbHcInitMemPool ( IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
- USBHC_MEM_POOL *Pool;
+ USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -398,8 +390,8 @@ UsbHcInitMemPool ( return Pool;
}
- Pool->PciIo = PciIo;
- Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
+ Pool->PciIo = PciIo;
+ Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
if (Pool->Head == NULL) {
gBS->FreePool (Pool);
@@ -409,7 +401,6 @@ UsbHcInitMemPool ( return Pool;
}
-
/**
Release the memory management pool.
@@ -421,10 +412,10 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -443,7 +434,6 @@ UsbHcFreeMemPool ( return EFI_SUCCESS;
}
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -456,16 +446,16 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -520,7 +510,6 @@ UsbHcAllocateMem ( return Mem;
}
-
/**
Free the allocated memory back to the memory pool.
@@ -531,22 +520,22 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -557,8 +546,8 @@ UsbHcFreeMem ( //
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -566,7 +555,7 @@ UsbHcFreeMem ( for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -589,7 +578,7 @@ UsbHcFreeMem ( UsbHcFreeMemBlock (Pool, Block);
}
- return ;
+ return;
}
/**
@@ -621,13 +610,13 @@ UsbHcAllocateAlignedPages ( OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- VOID *Memory;
- UINTN AlignedMemory;
- UINTN AlignmentMask;
- UINTN UnalignedPages;
- UINTN RealPages;
- UINTN Bytes;
+ EFI_STATUS Status;
+ VOID *Memory;
+ UINTN AlignedMemory;
+ UINTN AlignmentMask;
+ UINTN UnalignedPages;
+ UINTN RealPages;
+ UINTN Bytes;
//
// Alignment must be a power of two or zero.
@@ -641,12 +630,13 @@ UsbHcAllocateAlignedPages ( if (Pages == 0) {
return EFI_INVALID_PARAMETER;
}
+
if (Alignment > EFI_PAGE_SIZE) {
//
// Calculate the total number of pages since alignment is larger than page size.
//
- AlignmentMask = Alignment - 1;
- RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
+ AlignmentMask = Alignment - 1;
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
//
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
//
@@ -663,8 +653,9 @@ UsbHcAllocateAlignedPages ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
+
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
@@ -672,6 +663,7 @@ UsbHcAllocateAlignedPages ( Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
ASSERT_EFI_ERROR (Status);
}
+
Memory = (VOID *)(UINTN)(AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@@ -696,25 +688,26 @@ UsbHcAllocateAlignedPages ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- AlignedMemory = (UINTN) Memory;
+
+ AlignedMemory = (UINTN)Memory;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
- (VOID *) AlignedMemory,
+ (VOID *)AlignedMemory,
&Bytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
- Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *) AlignedMemory);
+ Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *)AlignedMemory);
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *) AlignedMemory;
+ *HostAddress = (VOID *)AlignedMemory;
return EFI_SUCCESS;
}
@@ -730,13 +723,13 @@ UsbHcAllocateAlignedPages ( **/
VOID
UsbHcFreeAlignedPages (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *HostAddress,
- IN UINTN Pages,
- VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ VOID *Mapping
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Pages != 0);
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h index 319110da3a..48ae86141c 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h @@ -10,20 +10,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_XHCI_MEM_H_
#define _EFI_XHCI_MEM_H_
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
@@ -32,16 +32,16 @@ struct _USBHC_MEM_BLOCK { // data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- EFI_PCI_IO_PROTOCOL *PciIo;
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -60,8 +60,6 @@ typedef struct _USBHC_MEM_POOL { } \
} while (0)
-
-
/**
Initialize the memory management pool for the host controller.
@@ -76,7 +74,6 @@ UsbHcInitMemPool ( IN EFI_PCI_IO_PROTOCOL *PciIo
);
-
/**
Release the memory management pool.
@@ -88,10 +85,9 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
);
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -104,11 +100,10 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
);
-
/**
Free the allocated memory back to the memory pool.
@@ -119,9 +114,9 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -136,9 +131,9 @@ UsbHcFreeMem ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -153,9 +148,9 @@ UsbHcGetPciAddrForHostAddr ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -198,10 +193,10 @@ UsbHcAllocateAlignedPages ( **/
VOID
UsbHcFreeAlignedPages (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *HostAddress,
- IN UINTN Pages,
- VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ VOID *Mapping
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c index 5a1f907ff0..b79499e225 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -13,46 +13,46 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
- {XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
- {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
- {XHC_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_PORTSC_PRC, EfiUsbPortResetChange}
+USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
+ { XHC_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_PORTSC_PRC, EfiUsbPortResetChange }
};
USB_PORT_STATE_MAP mUsbHubPortStateMap[] = {
- {XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbHubPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},
- {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}
+USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
+ { XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange },
+ { XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange }
};
EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding = {
@@ -67,7 +67,7 @@ EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding = { //
// Template for Xhci's Usb2 Host Controller Protocol Instance.
//
-EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {
+EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {
XhcGetCapability,
XhcReset,
XhcGetState,
@@ -114,12 +114,12 @@ XhcGetCapability ( return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (XHC_TPL);
+ OldTpl = gBS->RaiseTPL (XHC_TPL);
Xhc = XHC_FROM_THIS (This);
*MaxSpeed = EFI_USB_SPEED_SUPER;
- *PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts);
- *Is64BitCapable = (UINT8) Xhc->Support64BitDma;
+ *PortNumber = (UINT8)(Xhc->HcSParams1.Data.MaxPorts);
+ *Is64BitCapable = (UINT8)Xhc->Support64BitDma;
DEBUG ((DEBUG_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
gBS->RestoreTPL (OldTpl);
@@ -127,7 +127,6 @@ XhcGetCapability ( return EFI_SUCCESS;
}
-
/**
Provides software reset for the USB host controller.
@@ -168,51 +167,54 @@ XhcReset ( OldTpl = gBS->RaiseTPL (XHC_TPL);
switch (Attributes) {
- case EFI_USB_HC_RESET_GLOBAL:
- //
- // Flow through, same behavior as Host Controller Reset
- //
- case EFI_USB_HC_RESET_HOST_CONTROLLER:
- if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
- Status = EFI_SUCCESS;
- goto ON_EXIT;
- }
+ case EFI_USB_HC_RESET_GLOBAL:
//
- // Host Controller must be Halt when Reset it
+ // Flow through, same behavior as Host Controller Reset
//
- if (!XhcIsHalt (Xhc)) {
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
+ case EFI_USB_HC_RESET_HOST_CONTROLLER:
+ if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0))
+ {
+ Status = EFI_SUCCESS;
+ goto ON_EXIT;
+ }
+
+ //
+ // Host Controller must be Halt when Reset it
+ //
+ if (!XhcIsHalt (Xhc)) {
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
+
+ if (EFI_ERROR (Status)) {
+ Status = EFI_DEVICE_ERROR;
+ goto ON_EXIT;
+ }
+ }
+
+ Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);
+ ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));
if (EFI_ERROR (Status)) {
- Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
- }
-
- Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);
- ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));
- if (EFI_ERROR (Status)) {
- goto ON_EXIT;
- }
- //
- // Clean up the asynchronous transfers, currently only
- // interrupt supports asynchronous operation.
- //
- XhciDelAllAsyncIntTransfers (Xhc);
- XhcFreeSched (Xhc);
+ //
+ // Clean up the asynchronous transfers, currently only
+ // interrupt supports asynchronous operation.
+ //
+ XhciDelAllAsyncIntTransfers (Xhc);
+ XhcFreeSched (Xhc);
- XhcInitSched (Xhc);
- break;
+ XhcInitSched (Xhc);
+ break;
- case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
- case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
- Status = EFI_UNSUPPORTED;
- break;
+ case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
+ case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
+ Status = EFI_UNSUPPORTED;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -222,7 +224,6 @@ ON_EXIT: return Status;
}
-
/**
Retrieve the current state of the USB host controller.
@@ -252,7 +253,7 @@ XhcGetState ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
*State = EfiUsbHcStateHalt;
@@ -285,10 +286,10 @@ XhcSetState ( IN EFI_USB_HC_STATE State
)
{
- USB_XHCI_INSTANCE *Xhc;
- EFI_STATUS Status;
- EFI_USB_HC_STATE CurState;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ EFI_USB_HC_STATE CurState;
+ EFI_TPL OldTpl;
Status = XhcGetState (This, &CurState);
@@ -302,38 +303,38 @@ XhcSetState ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
switch (State) {
- case EfiUsbHcStateHalt:
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
- break;
-
- case EfiUsbHcStateOperational:
- if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {
- Status = EFI_DEVICE_ERROR;
+ case EfiUsbHcStateHalt:
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
break;
- }
- //
- // Software must not write a one to this field unless the host controller
- // is in the Halted state. Doing so will yield undefined results.
- // refers to Spec[XHCI1.0-2.3.1]
- //
- if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
- Status = EFI_DEVICE_ERROR;
- break;
- }
+ case EfiUsbHcStateOperational:
+ if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
- break;
+ //
+ // Software must not write a one to this field unless the host controller
+ // is in the Halted state. Doing so will yield undefined results.
+ // refers to Spec[XHCI1.0-2.3.1]
+ //
+ if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
- case EfiUsbHcStateSuspend:
- Status = EFI_UNSUPPORTED;
- break;
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ case EfiUsbHcStateSuspend:
+ Status = EFI_UNSUPPORTED;
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
DEBUG ((DEBUG_INFO, "XhcSetState: status %r\n", Status));
@@ -364,15 +365,15 @@ XhcGetRootHubPortStatus ( OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- UINTN Index;
- UINTN MapSize;
- EFI_STATUS Status;
- USB_DEV_ROUTE ParentRouteChart;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ UINTN Index;
+ UINTN MapSize;
+ EFI_STATUS Status;
+ USB_DEV_ROUTE ParentRouteChart;
+ EFI_TPL OldTpl;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
@@ -380,8 +381,8 @@ XhcGetRootHubPortStatus ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ Xhc = XHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = Xhc->HcSParams1.Data.MaxPorts;
@@ -390,7 +391,7 @@ XhcGetRootHubPortStatus ( goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
PortStatus->PortStatus = 0;
PortStatus->PortChangeStatus = 0;
@@ -401,21 +402,21 @@ XhcGetRootHubPortStatus ( // bit 10~13 of the root port status register identifies the speed of the attached device.
//
switch ((State & XHC_PORTSC_PS) >> 10) {
- case 2:
- PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
- break;
+ case 2:
+ PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
+ break;
- case 3:
- PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
- break;
+ case 3:
+ PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
+ break;
- case 4:
- case 5:
- PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
- break;
+ case 4:
+ case 5:
+ PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
+ break;
- default:
- break;
+ default:
+ break;
}
//
@@ -425,9 +426,10 @@ XhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
+
//
// Bit5~8 reflects its current link state.
//
@@ -439,7 +441,7 @@ XhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -463,7 +465,6 @@ ON_EXIT: return Status;
}
-
/**
Sets a feature for the specified root hub port.
@@ -484,12 +485,12 @@ XhcSetRootHubPortFeature ( IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
@@ -503,71 +504,71 @@ XhcSetRootHubPortFeature ( goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
State = XhcReadOpReg (Xhc, Offset);
//
// Mask off the port status change bits, these bits are
// write clean bit
//
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
- // A port may be disabled by software writing a '1' to this flag.
- //
- Status = EFI_SUCCESS;
- break;
-
- case EfiUsbPortSuspend:
- State |= XHC_PORTSC_LWS;
- XhcWriteOpReg (Xhc, Offset, State);
- State &= ~XHC_PORTSC_PLS;
- State |= (3 << 5) ;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
-
- case EfiUsbPortReset:
- DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));
- //
- // Make sure Host Controller not halt before reset it
- //
- if (XhcIsHalt (Xhc)) {
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
+ case EfiUsbPortEnable:
+ //
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
+ // A port may be disabled by software writing a '1' to this flag.
+ //
+ Status = EFI_SUCCESS;
+ break;
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
- break;
+ case EfiUsbPortSuspend:
+ State |= XHC_PORTSC_LWS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ State &= ~XHC_PORTSC_PLS;
+ State |= (3 << 5);
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
+
+ case EfiUsbPortReset:
+ DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));
+ //
+ // Make sure Host Controller not halt before reset it
+ //
+ if (XhcIsHalt (Xhc)) {
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
+ break;
+ }
}
- }
- //
- // 4.3.1 Resetting a Root Hub Port
- // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
- //
- State |= XHC_PORTSC_RESET;
- XhcWriteOpReg (Xhc, Offset, State);
- XhcWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
- break;
+ //
+ // 4.3.1 Resetting a Root Hub Port
+ // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
+ //
+ State |= XHC_PORTSC_RESET;
+ XhcWriteOpReg (Xhc, Offset, State);
+ XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
+ break;
- case EfiUsbPortPower:
- //
- // Not supported, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortPower:
+ //
+ // Not supported, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- case EfiUsbPortOwner:
- //
- // XHCI root hub port don't has the owner bit, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortOwner:
+ //
+ // XHCI root hub port don't has the owner bit, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -577,7 +578,6 @@ ON_EXIT: return Status;
}
-
/**
Clears a feature for the specified root hub port.
@@ -601,17 +601,17 @@ XhcClearRootHubPortFeature ( IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ Xhc = XHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Xhc->HcSParams1.Data.MaxPorts);
@@ -627,82 +627,82 @@ XhcClearRootHubPortFeature ( // write clean bit
//
State = XhcReadOpReg (Xhc, Offset);
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
- // A port may be disabled by software writing a '1' to this flag.
- //
- State |= XHC_PORTSC_PED;
- State &= ~XHC_PORTSC_RESET;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
-
- case EfiUsbPortSuspend:
- State |= XHC_PORTSC_LWS;
- XhcWriteOpReg (Xhc, Offset, State);
- State &= ~XHC_PORTSC_PLS;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
-
- case EfiUsbPortReset:
- //
- // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:
- // Register bits indicate status when read, a clear bit may be set by
- // writing a '1'. Writing a '0' to RW1S bits has no effect.
- //
- break;
+ case EfiUsbPortEnable:
+ //
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
+ // A port may be disabled by software writing a '1' to this flag.
+ //
+ State |= XHC_PORTSC_PED;
+ State &= ~XHC_PORTSC_RESET;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortOwner:
- //
- // XHCI root hub port don't has the owner bit, ignore the operation
- //
- break;
+ case EfiUsbPortSuspend:
+ State |= XHC_PORTSC_LWS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ State &= ~XHC_PORTSC_PLS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortConnectChange:
- //
- // Clear connect status change
- //
- State |= XHC_PORTSC_CSC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortReset:
+ //
+ // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:
+ // Register bits indicate status when read, a clear bit may be set by
+ // writing a '1'. Writing a '0' to RW1S bits has no effect.
+ //
+ break;
- case EfiUsbPortEnableChange:
- //
- // Clear enable status change
- //
- State |= XHC_PORTSC_PEC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortOwner:
+ //
+ // XHCI root hub port don't has the owner bit, ignore the operation
+ //
+ break;
- case EfiUsbPortOverCurrentChange:
- //
- // Clear PortOverCurrent change
- //
- State |= XHC_PORTSC_OCC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortConnectChange:
+ //
+ // Clear connect status change
+ //
+ State |= XHC_PORTSC_CSC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortResetChange:
- //
- // Clear Port Reset change
- //
- State |= XHC_PORTSC_PRC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortEnableChange:
+ //
+ // Clear enable status change
+ //
+ State |= XHC_PORTSC_PEC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortPower:
- case EfiUsbPortSuspendChange:
- //
- // Not supported or not related operation
- //
- break;
+ case EfiUsbPortOverCurrentChange:
+ //
+ // Clear PortOverCurrent change
+ //
+ State |= XHC_PORTSC_OCC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
+ case EfiUsbPortResetChange:
+ //
+ // Clear Port Reset change
+ //
+ State |= XHC_PORTSC_PRC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
+
+ case EfiUsbPortPower:
+ case EfiUsbPortSuspendChange:
+ //
+ // Not supported or not related operation
+ //
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
+ break;
}
ON_EXIT:
@@ -737,22 +737,22 @@ ON_EXIT: **/
EFI_STATUS
XhcTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN UINTN Timeout,
- OUT UINT32 *TransferResult
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN UINTN Timeout,
+ OUT UINT32 *TransferResult
)
{
- EFI_STATUS Status;
- EFI_STATUS RecoveryStatus;
- URB *Urb;
+ EFI_STATUS Status;
+ EFI_STATUS RecoveryStatus;
+ URB *Urb;
ASSERT ((Type == XHC_CTRL_TRANSFER) || (Type == XHC_BULK_TRANSFER) || (Type == XHC_INT_TRANSFER_SYNC));
Urb = XhcCreateUrb (
@@ -780,7 +780,7 @@ XhcTransfer ( //
// The transfer timed out. Abort the transfer by dequeueing of the TD.
//
- RecoveryStatus = XhcDequeueTrbFromEndpoint(Xhc, Urb);
+ RecoveryStatus = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (RecoveryStatus == EFI_ALREADY_STARTED) {
//
// The URB is finished just before stopping endpoint.
@@ -789,8 +789,8 @@ XhcTransfer ( ASSERT (Urb->Result == EFI_USB_NOERROR);
Status = EFI_SUCCESS;
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: pending URB is finished, Length = %d.\n", Type, Urb->Completed));
- } else if (EFI_ERROR(RecoveryStatus)) {
- DEBUG((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));
+ } else if (EFI_ERROR (RecoveryStatus)) {
+ DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));
}
}
@@ -799,7 +799,7 @@ XhcTransfer ( if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {
ASSERT (Status == EFI_DEVICE_ERROR);
- RecoveryStatus = XhcRecoverHaltedEndpoint(Xhc, Urb);
+ RecoveryStatus = XhcRecoverHaltedEndpoint (Xhc, Urb);
if (EFI_ERROR (RecoveryStatus)) {
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcRecoverHaltedEndpoint failed!\n", Type));
}
@@ -876,24 +876,28 @@ XhcControlTransfer ( if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
- (TransferDirection != EfiUsbNoData)) {
+ (TransferDirection != EfiUsbNoData))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
- ((Data != NULL) || (*DataLength != 0))) {
+ ((Data != NULL) || (*DataLength != 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
- ((Data == NULL) || (*DataLength == 0))) {
+ ((Data == NULL) || (*DataLength == 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
(MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&
(MaximumPacketLength != 512)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
@@ -907,7 +911,7 @@ XhcControlTransfer ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
@@ -931,7 +935,8 @@ XhcControlTransfer ( // According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.
//
if ((Request->Request == USB_REQ_SET_ADDRESS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.
// This way is used to clean the history to avoid using wrong device address by XhcAsyncInterruptTransfer().
@@ -939,7 +944,8 @@ XhcControlTransfer ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId == 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value))
+ {
Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;
}
}
@@ -948,6 +954,7 @@ XhcControlTransfer ( Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
+
//
// The actual device address has been assigned by XHCI during initializing the device slot.
// So we just need establish the mapping relationship between the device address requested from UsbBus
@@ -955,7 +962,7 @@ XhcControlTransfer ( // can find out the actual device address by it.
//
Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8)Request->Value;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
goto ON_EXIT;
}
@@ -966,20 +973,20 @@ XhcControlTransfer ( // endpoint is bidirectional. XhcCreateUrb expects this
// combination of Ep addr and its direction.
//
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
- Status = XhcTransfer (
- Xhc,
- DeviceAddress,
- Endpoint,
- DeviceSpeed,
- MaximumPacketLength,
- XHC_CTRL_TRANSFER,
- Request,
- Data,
- DataLength,
- Timeout,
- TransferResult
- );
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
+ Status = XhcTransfer (
+ Xhc,
+ DeviceAddress,
+ Endpoint,
+ DeviceSpeed,
+ MaximumPacketLength,
+ XHC_CTRL_TRANSFER,
+ Request,
+ Data,
+ DataLength,
+ Timeout,
+ TransferResult
+ );
if (EFI_ERROR (Status)) {
goto ON_EXIT;
@@ -992,28 +999,30 @@ XhcControlTransfer ( //
if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||
- ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {
+ ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE)))))
+ {
DescriptorType = (UINT8)(Request->Value >> 8);
if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {
- ASSERT (Data != NULL);
+ ASSERT (Data != NULL);
+ //
+ // Store a copy of device scriptor as hub device need this info to configure endpoint.
+ //
+ CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);
+ if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {
//
- // Store a copy of device scriptor as hub device need this info to configure endpoint.
+ // If it's a usb3.0 device, then its max packet size is a 2^n.
//
- CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);
- if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {
- //
- // If it's a usb3.0 device, then its max packet size is a 2^n.
- //
- MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
- } else {
- MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
- }
- Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
- if (Xhc->HcCParams.Data.Csz == 0) {
- Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
- } else {
- Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
- }
+ MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
+ } else {
+ MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
+ }
+
+ Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
+ if (Xhc->HcCParams.Data.Csz == 0) {
+ Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
+ } else {
+ Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
+ }
} else if (DescriptorType == USB_DESC_TYPE_CONFIG) {
ASSERT (Data != NULL);
if (*DataLength == ((UINT16 *)Data)[1]) {
@@ -1022,7 +1031,7 @@ XhcControlTransfer ( //
Index = (UINT8)Request->Value;
ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);
- Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool(*DataLength);
+ Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);
CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);
//
// Default to use AlternateSetting 0 for all interfaces.
@@ -1030,7 +1039,8 @@ XhcControlTransfer ( Xhc->UsbDevContext[SlotId].ActiveAlternateSetting = AllocateZeroPool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->NumInterfaces * sizeof (UINT8));
}
} else if (((DescriptorType == USB_DESC_TYPE_HUB) ||
- (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {
+ (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2))
+ {
ASSERT (Data != NULL);
HubDesc = (EFI_USB_HUB_DESCRIPTOR *)Data;
ASSERT (HubDesc->NumPorts <= 15);
@@ -1055,7 +1065,8 @@ XhcControlTransfer ( }
}
} else if ((Request->Request == USB_REQ_SET_CONFIG) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Hook Set_Config request from UsbBus as we need configure device endpoint.
//
@@ -1066,17 +1077,19 @@ XhcControlTransfer ( } else {
Status = XhcSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
}
+
break;
}
}
} else if ((Request->Request == USB_REQ_SET_INTERFACE) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE)))
+ {
//
// Hook Set_Interface request from UsbBus as we need configure interface setting.
// Request->Value indicates AlterlateSetting to set
// Request->Index indicates Interface to set
//
- if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] != (UINT8) Request->Value) {
+ if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] != (UINT8)Request->Value) {
if (Xhc->HcCParams.Data.Csz == 0) {
Status = XhcSetInterface (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Xhc->UsbDevContext[SlotId].ActiveConfiguration - 1], Request);
} else {
@@ -1084,7 +1097,8 @@ XhcControlTransfer ( }
}
} else if ((Request->Request == USB_REQ_GET_STATUS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER)))
+ {
ASSERT (Data != NULL);
//
// Hook Get_Status request from UsbBus to keep track of the port status change.
@@ -1117,14 +1131,14 @@ XhcControlTransfer ( MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {
- PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
+ PortStatus.PortStatus = (UINT16)(PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
}
}
MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {
- PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
+ PortStatus.PortChangeStatus = (UINT16)(PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
}
}
@@ -1133,11 +1147,11 @@ XhcControlTransfer ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {
ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));
- ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
- ClearPortRequest.Request = (UINT8) USB_REQ_CLEAR_FEATURE;
- ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
- ClearPortRequest.Index = Request->Index;
- ClearPortRequest.Length = 0;
+ ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
+ ClearPortRequest.Request = (UINT8)USB_REQ_CLEAR_FEATURE;
+ ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
+ ClearPortRequest.Index = Request->Index;
+ ClearPortRequest.Length = 0;
XhcControlTransfer (
This,
@@ -1157,7 +1171,7 @@ XhcControlTransfer ( XhcPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);
- *(UINT32 *)Data = *(UINT32*)&PortStatus;
+ *(UINT32 *)Data = *(UINT32 *)&PortStatus;
}
ON_EXIT:
@@ -1170,7 +1184,6 @@ ON_EXIT: return Status;
}
-
/**
Submits bulk transfer to a bulk endpoint of a USB device.
@@ -1218,16 +1231,17 @@ XhcBulkTransfer ( OUT UINT32 *TransferResult
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1238,13 +1252,14 @@ XhcBulkTransfer ( if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)) ||
- ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024))) {
+ ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024)))
+ {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -1284,6 +1299,7 @@ ON_EXIT: if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
+
gBS->RestoreTPL (OldTpl);
return Status;
@@ -1335,12 +1351,12 @@ XhcAsyncInterruptTransfer ( IN VOID *Context OPTIONAL
)
{
- USB_XHCI_INSTANCE *Xhc;
- URB *Urb;
- EFI_STATUS Status;
- UINT8 SlotId;
- UINT8 Index;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ URB *Urb;
+ EFI_STATUS Status;
+ UINT8 SlotId;
+ UINT8 Index;
+ EFI_TPL OldTpl;
//
// Validate parameters
@@ -1365,7 +1381,7 @@ XhcAsyncInterruptTransfer ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
//
// Delete Async interrupt transfer request.
@@ -1433,7 +1449,6 @@ ON_EXIT: return Status;
}
-
/**
Submits synchronous interrupt transfer to an interrupt endpoint
of a USB device.
@@ -1477,16 +1492,17 @@ XhcSyncInterruptTransfer ( OUT UINT32 *TransferResult
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
//
// Validates parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1496,13 +1512,14 @@ XhcSyncInterruptTransfer ( if (((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072))) {
+ ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072)))
+ {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -1538,12 +1555,12 @@ ON_EXIT: if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
+
gBS->RestoreTPL (OldTpl);
return Status;
}
-
/**
Submits isochronous transfer to a target USB device.
@@ -1583,7 +1600,6 @@ XhcIsochronousTransfer ( return EFI_UNSUPPORTED;
}
-
/**
Submits Async isochronous transfer to a target USB device.
@@ -1639,8 +1655,8 @@ XhcAsyncIsochronousTransfer ( EFI_STATUS
EFIAPI
XhcDriverEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
return EfiLibInstallDriverBindingComponentName2 (
@@ -1653,7 +1669,6 @@ XhcDriverEntryPoint ( );
}
-
/**
Test to see if this driver supports ControllerHandle. Any
ControllerHandle that has Usb2HcProtocol installed will
@@ -1670,14 +1685,14 @@ XhcDriverEntryPoint ( EFI_STATUS
EFIAPI
XhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- USB_CLASSC UsbClassCReg;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ USB_CLASSC UsbClassCReg;
//
// Test whether there is PCI IO Protocol attached on the controller handle.
@@ -1685,7 +1700,7 @@ XhcDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1713,7 +1728,8 @@ XhcDriverBindingSupported ( //
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||
- (UsbClassCReg.ProgInterface != PCI_IF_XHCI)) {
+ (UsbClassCReg.ProgInterface != PCI_IF_XHCI))
+ {
Status = EFI_UNSUPPORTED;
}
@@ -1739,18 +1755,18 @@ ON_EXIT: otherwise NULL.
**/
-USB_XHCI_INSTANCE*
+USB_XHCI_INSTANCE *
XhcCreateUsbHc (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINT64 OriginalPciAttributes
)
{
- USB_XHCI_INSTANCE *Xhc;
- EFI_STATUS Status;
- UINT32 PageSize;
- UINT16 ExtCapReg;
- UINT8 ReleaseNumber;
+ USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ UINT32 PageSize;
+ UINT16 ExtCapReg;
+ UINT8 ReleaseNumber;
Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE));
@@ -1797,12 +1813,12 @@ XhcCreateUsbHc ( // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
// if bit 0 is Set, the xHC supports 4k byte page sizes.
//
- PageSize = XhcReadOpReg(Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
- Xhc->PageSize = 1 << (HighBitSet32(PageSize) + 12);
+ PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
+ Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
- ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
- Xhc->ExtCapRegBase = ExtCapReg << 2;
- Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
+ ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);
+ Xhc->ExtCapRegBase = ExtCapReg << 2;
+ Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
@@ -1854,7 +1870,7 @@ XhcExitBootService ( USB_XHCI_INSTANCE *Xhc;
EFI_PCI_IO_PROTOCOL *PciIo;
- Xhc = (USB_XHCI_INSTANCE*) Context;
+ Xhc = (USB_XHCI_INSTANCE *)Context;
PciIo = Xhc->PciIo;
//
@@ -1874,11 +1890,11 @@ XhcExitBootService ( // Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- Xhc->OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ Xhc->OriginalPciAttributes,
+ NULL
+ );
}
/**
@@ -1897,17 +1913,17 @@ XhcExitBootService ( EFI_STATUS
EFIAPI
XhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Supports;
- UINT64 OriginalPciAttributes;
- BOOLEAN PciAttributesSaved;
- USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Supports;
+ UINT64 OriginalPciAttributes;
+ BOOLEAN PciAttributesSaved;
+ USB_XHCI_INSTANCE *Xhc;
EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;
//
@@ -1916,7 +1932,7 @@ XhcDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1930,14 +1946,14 @@ XhcDriverBindingStart ( // Open Device Path Protocol for on USB host controller
//
HcDevicePath = NULL;
- Status = gBS->OpenProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- (VOID **) &HcDevicePath,
- This->DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL
- );
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&HcDevicePath,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
PciAttributesSaved = FALSE;
//
@@ -1953,6 +1969,7 @@ XhcDriverBindingStart ( if (EFI_ERROR (Status)) {
goto CLOSE_PCIIO;
}
+
PciAttributesSaved = TRUE;
Status = PciIo->Attributes (
@@ -1963,12 +1980,12 @@ XhcDriverBindingStart ( );
if (!EFI_ERROR (Status)) {
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
- Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
}
if (EFI_ERROR (Status)) {
@@ -2000,9 +2017,13 @@ XhcDriverBindingStart ( if (!EFI_ERROR (Status)) {
Xhc->Support64BitDma = TRUE;
} else {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
- __FUNCTION__, Controller, Status));
+ __FUNCTION__,
+ Controller,
+ Status
+ ));
}
}
@@ -2025,7 +2046,7 @@ XhcDriverBindingStart ( //
// Start the Host Controller
//
- XhcRunHC(Xhc, XHC_GENERIC_TIMEOUT);
+ XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
//
// Start the asynchronous interrupt monitor
@@ -2096,11 +2117,11 @@ CLOSE_PCIIO: // Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ OriginalPciAttributes,
+ NULL
+ );
}
gBS->CloseProtocol (
@@ -2113,7 +2134,6 @@ CLOSE_PCIIO: return Status;
}
-
/**
Stop this driver on ControllerHandle. Support stopping any child handles
created by this driver.
@@ -2130,10 +2150,10 @@ CLOSE_PCIIO: EFI_STATUS
EFIAPI
XhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -2150,7 +2170,7 @@ XhcDriverBindingStop ( Status = gBS->OpenProtocol (
Controller,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -2185,9 +2205,11 @@ XhcDriverBindingStop ( //
for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
- (Xhc->UsbDevContext[Index + 1].SlotId == 0)) {
+ (Xhc->UsbDevContext[Index + 1].SlotId == 0))
+ {
continue;
}
+
if (Xhc->HcCParams.Data.Csz == 0) {
XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
} else {
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h index 3285eb8798..5054d796b1 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h @@ -29,8 +29,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <IndustryStandard/Pci.h>
-typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
-typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
+typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
+typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "XhciReg.h"
#include "XhciSched.h"
@@ -40,62 +40,62 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT; //
// The unit is microsecond, setting it as 1us.
//
-#define XHC_1_MICROSECOND (1)
+#define XHC_1_MICROSECOND (1)
//
// The unit is microsecond, setting it as 1ms.
//
-#define XHC_1_MILLISECOND (1000)
+#define XHC_1_MILLISECOND (1000)
//
// XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
-#define XHC_GENERIC_TIMEOUT (10 * 1000)
+#define XHC_GENERIC_TIMEOUT (10 * 1000)
//
// XHC reset timeout experience values.
// The unit is millisecond, setting it as 1s.
//
-#define XHC_RESET_TIMEOUT (1000)
+#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
-#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
+#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// XHC async transfer timer interval, set by experience.
// The unit is 100us, takes 1ms as interval.
//
-#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
+#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// XHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
-#define XHC_TPL TPL_NOTIFY
+#define XHC_TPL TPL_NOTIFY
-#define CMD_RING_TRB_NUMBER 0x100
-#define TR_RING_TRB_NUMBER 0x100
-#define ERST_NUMBER 0x01
-#define EVENT_RING_TRB_NUMBER 0x200
+#define CMD_RING_TRB_NUMBER 0x100
+#define TR_RING_TRB_NUMBER 0x100
+#define ERST_NUMBER 0x01
+#define EVENT_RING_TRB_NUMBER 0x200
-#define CMD_INTER 0
-#define CTRL_INTER 1
-#define BULK_INTER 2
-#define INT_INTER 3
-#define INT_INTER_ASYNC 4
+#define CMD_INTER 0
+#define CTRL_INTER 1
+#define BULK_INTER 2
+#define INT_INTER 3
+#define INT_INTER_ASYNC 4
-#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
+#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
-#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
-#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
-#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
+#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
+#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(Xhc, Offset, Bit) \
(XHC_BIT_IS_SET(XhcReadOpReg ((Xhc), (Offset)), (Bit)))
-#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
+#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
-#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
-#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
+#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
+#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
#define USB_DESC_TYPE_HUB 0x29
#define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a
@@ -113,19 +113,19 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT; //
#pragma pack(1)
typedef struct {
- UINT8 ProgInterface;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 ProgInterface;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
typedef struct {
- UINT8 Length;
- UINT8 DescType;
- UINT8 NumPorts;
- UINT16 HubCharacter;
- UINT8 PwrOn2PwrGood;
- UINT8 HubContrCurrent;
- UINT8 Filler[16];
+ UINT8 Length;
+ UINT8 DescType;
+ UINT8 NumPorts;
+ UINT16 HubCharacter;
+ UINT8 PwrOn2PwrGood;
+ UINT8 HubContrCurrent;
+ UINT8 Filler[16];
} EFI_USB_HUB_DESCRIPTOR;
#pragma pack()
@@ -133,23 +133,23 @@ struct _USB_DEV_CONTEXT { //
// Whether this entry in UsbDevContext array is used or not.
//
- BOOLEAN Enabled;
+ BOOLEAN Enabled;
//
// The slot id assigned to the new device through XHCI's Enable_Slot cmd.
//
- UINT8 SlotId;
+ UINT8 SlotId;
//
// The route string presented an attached usb device.
//
- USB_DEV_ROUTE RouteString;
+ USB_DEV_ROUTE RouteString;
//
// The route string of parent device if it exists. Otherwise it's zero.
//
- USB_DEV_ROUTE ParentRouteString;
+ USB_DEV_ROUTE ParentRouteString;
//
// The actual device address assigned by XHCI through Address_Device command.
//
- UINT8 XhciDevAddr;
+ UINT8 XhciDevAddr;
//
// The requested device address from UsbBus driver through Set_Address standard usb request.
// As XHCI spec replaces this request with Address_Device command, we have to record the
@@ -158,23 +158,23 @@ struct _USB_DEV_CONTEXT { // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
// device address and access the actual device.
//
- UINT8 BusDevAddr;
+ UINT8 BusDevAddr;
//
// The pointer to the input device context.
//
- VOID *InputContext;
+ VOID *InputContext;
//
// The pointer to the output device context.
//
- VOID *OutputContext;
+ VOID *OutputContext;
//
// The transfer queue for every endpoint.
//
- VOID *EndpointTransferRing[31];
+ VOID *EndpointTransferRing[31];
//
// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
//
- EFI_USB_DEVICE_DESCRIPTOR DevDesc;
+ EFI_USB_DEVICE_DESCRIPTOR DevDesc;
//
// As a usb device may include multiple configuration descriptors, we dynamically allocate an array
// to store them.
@@ -182,81 +182,80 @@ struct _USB_DEV_CONTEXT { // such as Interface descriptor, Endpoint descriptor, and so on.
// These information is used to support XHCI's Config_Endpoint cmd.
//
- EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
+ EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
//
// A device has an active Configuration.
//
- UINT8 ActiveConfiguration;
+ UINT8 ActiveConfiguration;
//
// Every interface has an active AlternateSetting.
//
- UINT8 *ActiveAlternateSetting;
+ UINT8 *ActiveAlternateSetting;
};
struct _USB_XHCI_INSTANCE {
- UINT32 Signature;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 OriginalPciAttributes;
- USBHC_MEM_POOL *MemPool;
+ UINT32 Signature;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 OriginalPciAttributes;
+ USBHC_MEM_POOL *MemPool;
- EFI_USB2_HC_PROTOCOL Usb2Hc;
+ EFI_USB2_HC_PROTOCOL Usb2Hc;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
//
// ExitBootServicesEvent is used to set OS semaphore and
// stop the XHC DMA operation after exit boot service.
//
- EFI_EVENT ExitBootServiceEvent;
- EFI_EVENT PollTimer;
- LIST_ENTRY AsyncIntTransfers;
-
- UINT8 CapLength; ///< Capability Register Length
- XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
- XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
- XHC_HCCPARAMS HcCParams; ///< Capability Parameters
- UINT32 DBOff; ///< Doorbell Offset
- UINT32 RTSOff; ///< Runtime Register Space Offset
- UINT16 MaxInterrupt;
- UINT32 PageSize;
- UINT64 *ScratchBuf;
- VOID *ScratchMap;
- UINT32 MaxScratchpadBufs;
- UINT64 *ScratchEntry;
- UINTN *ScratchEntryMap;
- UINT32 ExtCapRegBase;
- UINT32 UsbLegSupOffset;
- UINT32 DebugCapSupOffset;
- UINT64 *DCBAA;
- VOID *DCBAAMap;
- UINT32 MaxSlotsEn;
- URB *PendingUrb;
+ EFI_EVENT ExitBootServiceEvent;
+ EFI_EVENT PollTimer;
+ LIST_ENTRY AsyncIntTransfers;
+
+ UINT8 CapLength; ///< Capability Register Length
+ XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
+ XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
+ XHC_HCCPARAMS HcCParams; ///< Capability Parameters
+ UINT32 DBOff; ///< Doorbell Offset
+ UINT32 RTSOff; ///< Runtime Register Space Offset
+ UINT16 MaxInterrupt;
+ UINT32 PageSize;
+ UINT64 *ScratchBuf;
+ VOID *ScratchMap;
+ UINT32 MaxScratchpadBufs;
+ UINT64 *ScratchEntry;
+ UINTN *ScratchEntryMap;
+ UINT32 ExtCapRegBase;
+ UINT32 UsbLegSupOffset;
+ UINT32 DebugCapSupOffset;
+ UINT64 *DCBAA;
+ VOID *DCBAAMap;
+ UINT32 MaxSlotsEn;
+ URB *PendingUrb;
//
// Cmd Transfer Ring
//
- TRANSFER_RING CmdRing;
+ TRANSFER_RING CmdRing;
//
// EventRing
//
- EVENT_RING EventRing;
+ EVENT_RING EventRing;
//
// Misc
//
- EFI_UNICODE_STRING_TABLE *ControllerNameTable;
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// Store device contexts managed by XHCI instance
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
- USB_DEV_CONTEXT UsbDevContext[256];
+ USB_DEV_CONTEXT UsbDevContext[256];
- BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
+ BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};
-
-extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
-extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
/**
Test to see if this driver supports ControllerHandle. Any
@@ -274,9 +273,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2; EFI_STATUS
EFIAPI
XhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -295,9 +294,9 @@ XhcDriverBindingSupported ( EFI_STATUS
EFIAPI
XhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -316,10 +315,10 @@ XhcDriverBindingStart ( EFI_STATUS
EFIAPI
XhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
/**
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index 70102a7fcf..80be3311d4 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -21,18 +21,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
UINT8
XhcReadCapReg8 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT8 Data;
- EFI_STATUS Status;
+ UINT8 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint8,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -57,18 +57,18 @@ XhcReadCapReg8 ( **/
UINT32
XhcReadCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -93,12 +93,12 @@ XhcReadCapReg ( **/
UINT32
XhcReadOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -129,12 +129,12 @@ XhcReadOpReg ( **/
VOID
XhcWriteOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -152,10 +152,6 @@ XhcWriteOpReg ( }
}
-
-
-
-
/**
Write the data to the XHCI door bell register.
@@ -166,12 +162,12 @@ XhcWriteOpReg ( **/
VOID
XhcWriteDoorBellReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->DBOff != 0);
@@ -200,12 +196,12 @@ XhcWriteDoorBellReg ( **/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -236,12 +232,12 @@ XhcReadRuntimeReg ( **/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -270,12 +266,12 @@ XhcWriteRuntimeReg ( **/
UINT32
XhcReadExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -306,12 +302,12 @@ XhcReadExtCapReg ( **/
VOID
XhcWriteExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -329,7 +325,6 @@ XhcWriteExtCapReg ( }
}
-
/**
Set one bit of the runtime register while keeping other bits.
@@ -340,12 +335,12 @@ XhcWriteExtCapReg ( **/
VOID
XhcSetRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data |= Bit;
@@ -362,12 +357,12 @@ XhcSetRuntimeRegBit ( **/
VOID
XhcClearRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data &= ~Bit;
@@ -384,19 +379,18 @@ XhcClearRuntimeRegBit ( **/
VOID
XhcSetOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data |= Bit;
XhcWriteOpReg (Xhc, Offset, Data);
}
-
/**
Clear one bit of the operational register while keeping other bits.
@@ -407,12 +401,12 @@ XhcSetOpRegBit ( **/
VOID
XhcClearOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data &= ~Bit;
@@ -436,15 +430,15 @@ XhcClearOpRegBit ( **/
EFI_STATUS
XhcWaitOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
- EFI_EVENT TimeoutEvent;
+ EFI_STATUS Status;
+ EFI_EVENT TimeoutEvent;
TimeoutEvent = NULL;
@@ -460,15 +454,17 @@ XhcWaitOpRegBit ( &TimeoutEvent
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto DONE;
}
- Status = gBS->SetTimer (TimeoutEvent,
- TimerRelative,
- EFI_TIMER_PERIOD_MILLISECONDS(Timeout));
+ Status = gBS->SetTimer (
+ TimeoutEvent,
+ TimerRelative,
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
+ );
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto DONE;
}
@@ -479,7 +475,7 @@ XhcWaitOpRegBit ( }
gBS->Stall (XHC_1_MICROSECOND);
- } while (EFI_ERROR(gBS->CheckEvent (TimeoutEvent)));
+ } while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
Status = EFI_TIMEOUT;
@@ -499,10 +495,10 @@ DONE: **/
VOID
XhcSetBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
@@ -523,10 +519,10 @@ XhcSetBiosOwnership ( **/
VOID
XhcClearBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
@@ -550,13 +546,13 @@ XhcClearBiosOwnership ( **/
UINT32
XhcGetCapabilityAddr (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 CapId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
)
{
- UINT32 ExtCapOffset;
- UINT8 NextExtCapReg;
- UINT32 Data;
+ UINT32 ExtCapOffset;
+ UINT8 NextExtCapReg;
+ UINT32 Data;
ExtCapOffset = 0;
@@ -568,6 +564,7 @@ XhcGetCapabilityAddr ( if ((Data & 0xFF) == CapId) {
return ExtCapOffset;
}
+
//
// If not, then traverse all of the ext capability registers till finding out it.
//
@@ -589,13 +586,12 @@ XhcGetCapabilityAddr ( **/
BOOLEAN
XhcIsHalt (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
}
-
/**
Whether system error occurred.
@@ -607,7 +603,7 @@ XhcIsHalt ( **/
BOOLEAN
XhcIsSysError (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
@@ -627,11 +623,11 @@ XhcSetHsee ( IN USB_XHCI_INSTANCE *Xhc
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 XhciCmd;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 XhciCmd;
- PciIo = Xhc->PciIo;
+ PciIo = Xhc->PciIo;
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@@ -658,11 +654,11 @@ XhcSetHsee ( **/
EFI_STATUS
XhcResetHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EFI_SUCCESS;
@@ -679,7 +675,8 @@ XhcResetHC ( }
if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0))
+ {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
//
// Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
@@ -701,7 +698,6 @@ XhcResetHC ( return Status;
}
-
/**
Halt the XHCI host controller.
@@ -714,18 +710,17 @@ XhcResetHC ( **/
EFI_STATUS
XhcHaltHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
return Status;
}
-
/**
Set the XHCI host controller to run.
@@ -738,11 +733,11 @@ XhcHaltHC ( **/
EFI_STATUS
XhcRunHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h index cc5c1bf09a..4950eed272 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h @@ -10,124 +10,124 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_XHCI_REG_H_
#define _EFI_XHCI_REG_H_
-#define PCI_IF_XHCI 0x30
+#define PCI_IF_XHCI 0x30
//
// PCI Configuration Registers
//
-#define XHC_BAR_INDEX 0x00
+#define XHC_BAR_INDEX 0x00
-#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
-#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
+#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
+#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
-#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
+#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
-#define USB_HUB_CLASS_CODE 0x09
-#define USB_HUB_SUBCLASS_CODE 0x00
+#define USB_HUB_CLASS_CODE 0x09
+#define USB_HUB_SUBCLASS_CODE 0x00
-#define XHC_CAP_USB_LEGACY 0x01
-#define XHC_CAP_USB_DEBUG 0x0A
+#define XHC_CAP_USB_LEGACY 0x01
+#define XHC_CAP_USB_DEBUG 0x0A
-//============================================//
+// ============================================//
// XHCI register offset //
-//============================================//
+// ============================================//
//
// Capability registers offset
//
-#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
-#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
-#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
-#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
-#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
-#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
-#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
-#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
+#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
+#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
+#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
+#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
+#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
+#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
+#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
+#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
//
// Operational registers offset
//
-#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
-#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
-#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
-#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
-#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
-#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
-#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
-#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
+#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
+#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
+#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
+#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
+#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
+#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
+#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
+#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
//
// Runtime registers offset
//
-#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
-#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
-#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
-#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
-#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
-#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
+#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
+#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
+#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
+#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
+#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
+#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
//
// Debug registers offset
//
-#define XHC_DC_DCCTRL 0x20
+#define XHC_DC_DCCTRL 0x20
-#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
-#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
+#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
+#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
#pragma pack (1)
typedef struct {
- UINT8 MaxSlots; // Number of Device Slots
- UINT16 MaxIntrs:11; // Number of Interrupters
- UINT16 Rsvd:5;
- UINT8 MaxPorts; // Number of Ports
+ UINT8 MaxSlots; // Number of Device Slots
+ UINT16 MaxIntrs : 11; // Number of Interrupters
+ UINT16 Rsvd : 5;
+ UINT8 MaxPorts; // Number of Ports
} HCSPARAMS1;
//
// Structural Parameters 1 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS1 Data;
+ UINT32 Dword;
+ HCSPARAMS1 Data;
} XHC_HCSPARAMS1;
typedef struct {
- UINT32 Ist:4; // Isochronous Scheduling Threshold
- UINT32 Erst:4; // Event Ring Segment Table Max
- UINT32 Rsvd:13;
- UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
- UINT32 Spr:1; // Scratchpad Restore
- UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
+ UINT32 Ist : 4; // Isochronous Scheduling Threshold
+ UINT32 Erst : 4; // Event Ring Segment Table Max
+ UINT32 Rsvd : 13;
+ UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi
+ UINT32 Spr : 1; // Scratchpad Restore
+ UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo
} HCSPARAMS2;
//
// Structural Parameters 2 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS2 Data;
+ UINT32 Dword;
+ HCSPARAMS2 Data;
} XHC_HCSPARAMS2;
typedef struct {
- UINT16 Ac64:1; // 64-bit Addressing Capability
- UINT16 Bnc:1; // BW Negotiation Capability
- UINT16 Csz:1; // Context Size
- UINT16 Ppc:1; // Port Power Control
- UINT16 Pind:1; // Port Indicators
- UINT16 Lhrc:1; // Light HC Reset Capability
- UINT16 Ltc:1; // Latency Tolerance Messaging Capability
- UINT16 Nss:1; // No Secondary SID Support
- UINT16 Pae:1; // Parse All Event Data
- UINT16 Rsvd:3;
- UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
- UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
+ UINT16 Ac64 : 1; // 64-bit Addressing Capability
+ UINT16 Bnc : 1; // BW Negotiation Capability
+ UINT16 Csz : 1; // Context Size
+ UINT16 Ppc : 1; // Port Power Control
+ UINT16 Pind : 1; // Port Indicators
+ UINT16 Lhrc : 1; // Light HC Reset Capability
+ UINT16 Ltc : 1; // Latency Tolerance Messaging Capability
+ UINT16 Nss : 1; // No Secondary SID Support
+ UINT16 Pae : 1; // Parse All Event Data
+ UINT16 Rsvd : 3;
+ UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size
+ UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
} HCCPARAMS;
//
// Capability Parameters Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCCPARAMS Data;
+ UINT32 Dword;
+ HCCPARAMS Data;
} XHC_HCCPARAMS;
#pragma pack ()
@@ -135,62 +135,62 @@ typedef union { //
// Register Bit Definition
//
-#define XHC_USBCMD_RUN BIT0 // Run/Stop
-#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
-#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
-#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
-
-#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
-#define XHC_USBSTS_HSE BIT2 // Host System Error
-#define XHC_USBSTS_EINT BIT3 // Event Interrupt
-#define XHC_USBSTS_PCD BIT4 // Port Change Detect
-#define XHC_USBSTS_SSS BIT8 // Save State Status
-#define XHC_USBSTS_RSS BIT9 // Restore State Status
-#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
-#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
-#define XHC_USBSTS_HCE BIT12 // Host Controller Error
-
-#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
-
-#define XHC_CRCR_RCS BIT0 // Ring Cycle State
-#define XHC_CRCR_CS BIT1 // Command Stop
-#define XHC_CRCR_CA BIT2 // Command Abort
-#define XHC_CRCR_CRR BIT3 // Command Ring Running
-
-#define XHC_CONFIG_MASK 0xFF // Command Ring Running
-
-#define XHC_PORTSC_CCS BIT0 // Current Connect Status
-#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
-#define XHC_PORTSC_OCA BIT3 // Over-current Active
-#define XHC_PORTSC_RESET BIT4 // Port Reset
-#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
-#define XHC_PORTSC_PP BIT9 // Port Power
-#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
-#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
-#define XHC_PORTSC_CSC BIT17 // Connect Status Change
-#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
-#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
-#define XHC_PORTSC_OCC BIT20 // Over-Current Change
-#define XHC_PORTSC_PRC BIT21 // Port Reset Change
-#define XHC_PORTSC_PLC BIT22 // Port Link State Change
-#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
-#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
-
-#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
-#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
-#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
-#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
-#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
-#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
-#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
-#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
-#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
-#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
-#define XHC_IMAN_IP BIT0 // Interrupt Pending
-#define XHC_IMAN_IE BIT1 // Interrupt Enable
-
-#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
-#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
+#define XHC_USBCMD_RUN BIT0 // Run/Stop
+#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
+#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
+#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
+
+#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
+#define XHC_USBSTS_HSE BIT2 // Host System Error
+#define XHC_USBSTS_EINT BIT3 // Event Interrupt
+#define XHC_USBSTS_PCD BIT4 // Port Change Detect
+#define XHC_USBSTS_SSS BIT8 // Save State Status
+#define XHC_USBSTS_RSS BIT9 // Restore State Status
+#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
+#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
+#define XHC_USBSTS_HCE BIT12 // Host Controller Error
+
+#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
+
+#define XHC_CRCR_RCS BIT0 // Ring Cycle State
+#define XHC_CRCR_CS BIT1 // Command Stop
+#define XHC_CRCR_CA BIT2 // Command Abort
+#define XHC_CRCR_CRR BIT3 // Command Ring Running
+
+#define XHC_CONFIG_MASK 0xFF // Command Ring Running
+
+#define XHC_PORTSC_CCS BIT0 // Current Connect Status
+#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
+#define XHC_PORTSC_OCA BIT3 // Over-current Active
+#define XHC_PORTSC_RESET BIT4 // Port Reset
+#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
+#define XHC_PORTSC_PP BIT9 // Port Power
+#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
+#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
+#define XHC_PORTSC_CSC BIT17 // Connect Status Change
+#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
+#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
+#define XHC_PORTSC_OCC BIT20 // Over-Current Change
+#define XHC_PORTSC_PRC BIT21 // Port Reset Change
+#define XHC_PORTSC_PLC BIT22 // Port Link State Change
+#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
+#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
+
+#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
+#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
+#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
+#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
+#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
+#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
+#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
+#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
+#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
+#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
+#define XHC_IMAN_IP BIT0 // Interrupt Pending
+#define XHC_IMAN_IE BIT1 // Interrupt Enable
+
+#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
+#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
//
// Hub Class Feature Selector for Clear Port Feature Request
@@ -198,8 +198,8 @@ typedef union { // For more details, Please refer to USB 3.0 Spec Table 10-7.
//
typedef enum {
- Usb3PortBHPortReset = 28,
- Usb3PortBHPortResetChange = 29
+ Usb3PortBHPortReset = 28,
+ Usb3PortBHPortResetChange = 29
} XHC_PORT_FEATURE;
//
@@ -207,16 +207,16 @@ typedef enum { // UEFI's port states.
//
typedef struct {
- UINT32 HwState;
- UINT16 UefiState;
+ UINT32 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
// Structure to map the hardware port states to feature selector for clear port feature request.
//
typedef struct {
- UINT32 HwState;
- UINT16 Selector;
+ UINT32 HwState;
+ UINT16 Selector;
} USB_CLEAR_PORT_MAP;
/**
@@ -231,8 +231,8 @@ typedef struct { **/
UINT8
XhcReadCapReg8 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -247,8 +247,8 @@ XhcReadCapReg8 ( **/
UINT32
XhcReadCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -263,8 +263,8 @@ XhcReadCapReg ( **/
UINT32
XhcReadOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -277,12 +277,11 @@ XhcReadOpReg ( **/
VOID
XhcWriteOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
-
/**
Read XHCI runtime register.
@@ -294,8 +293,8 @@ XhcWriteOpReg ( **/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -308,12 +307,11 @@ XhcReadRuntimeReg ( **/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
-
/**
Write the data to the XHCI door bell register.
@@ -324,9 +322,9 @@ XhcWriteRuntimeReg ( **/
VOID
XhcWriteDoorBellReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -339,9 +337,9 @@ XhcWriteDoorBellReg ( **/
VOID
XhcSetOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -354,9 +352,9 @@ XhcSetOpRegBit ( **/
VOID
XhcClearOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -375,11 +373,11 @@ XhcClearOpRegBit ( **/
EFI_STATUS
XhcWaitOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
);
/**
@@ -393,8 +391,8 @@ XhcWaitOpRegBit ( **/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -407,9 +405,9 @@ XhcReadRuntimeReg ( **/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -422,9 +420,9 @@ XhcWriteRuntimeReg ( **/
VOID
XhcSetRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -437,9 +435,9 @@ XhcSetRuntimeRegBit ( **/
VOID
XhcClearRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -453,8 +451,8 @@ XhcClearRuntimeRegBit ( **/
UINT32
XhcReadExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -468,7 +466,7 @@ XhcReadExtCapReg ( **/
BOOLEAN
XhcIsHalt (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -482,7 +480,7 @@ XhcIsHalt ( **/
BOOLEAN
XhcIsSysError (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -497,8 +495,8 @@ XhcIsSysError ( **/
EFI_STATUS
XhcResetHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -513,8 +511,8 @@ XhcResetHC ( **/
EFI_STATUS
XhcHaltHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -529,8 +527,8 @@ XhcHaltHC ( **/
EFI_STATUS
XhcRunHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -544,8 +542,8 @@ XhcRunHC ( **/
UINT32
XhcGetCapabilityAddr (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 CapId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 92f63c29fc..c2906e06fd 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -19,25 +19,25 @@ SPDX-License-Identifier: BSD-2-Clause-Patent @return Created URB or NULL.
**/
-URB*
+URB *
XhcCreateCmdTrb (
IN USB_XHCI_INSTANCE *Xhc,
IN TRB_TEMPLATE *CmdTrb
)
{
- URB *Urb;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
return NULL;
}
- Urb->Signature = XHC_URB_SIG;
+ Urb->Signature = XHC_URB_SIG;
- Urb->Ring = &Xhc->CmdRing;
+ Urb->Ring = &Xhc->CmdRing;
XhcSyncTrsRing (Xhc, Urb->Ring);
- Urb->TrbNum = 1;
- Urb->TrbStart = Urb->Ring->RingEnqueue;
+ Urb->TrbNum = 1;
+ Urb->TrbStart = Urb->Ring->RingEnqueue;
CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
Urb->TrbEnd = Urb->TrbStart;
@@ -63,14 +63,14 @@ XhcCreateCmdTrb ( EFI_STATUS
EFIAPI
XhcCmdTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *CmdTrb,
- IN UINTN Timeout,
- OUT TRB_TEMPLATE **EvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *CmdTrb,
+ IN UINTN Timeout,
+ OUT TRB_TEMPLATE **EvtTrb
)
{
- EFI_STATUS Status;
- URB *Urb;
+ EFI_STATUS Status;
+ URB *Urb;
//
// Validate the parameters
@@ -128,24 +128,24 @@ ON_EXIT: @return Created URB or NULL
**/
-URB*
+URB *
XhcCreateUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- USB_ENDPOINT *Ep;
- EFI_STATUS Status;
- URB *Urb;
+ USB_ENDPOINT *Ep;
+ EFI_STATUS Status;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
@@ -189,8 +189,8 @@ XhcCreateUrb ( **/
VOID
XhcFreeUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
if ((Xhc == NULL) || (Urb == NULL)) {
@@ -215,23 +215,23 @@ XhcFreeUrb ( **/
EFI_STATUS
XhcCreateTransferTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- VOID *OutputContext;
- TRANSFER_RING *EPRing;
- UINT8 EPType;
- UINT8 SlotId;
- UINT8 Dci;
- TRB *TrbStart;
- UINTN TotalLen;
- UINTN Len;
- UINTN TrbNum;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *Map;
- EFI_STATUS Status;
+ VOID *OutputContext;
+ TRANSFER_RING *EPRing;
+ UINT8 EPType;
+ UINT8 SlotId;
+ UINT8 Dci;
+ TRB *TrbStart;
+ UINTN TotalLen;
+ UINTN Len;
+ UINTN TrbNum;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *Map;
+ EFI_STATUS Status;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
@@ -244,37 +244,37 @@ XhcCreateTransferTrb ( Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
- EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
- Urb->Ring = EPRing;
+ EPRing = (TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
+ Urb->Ring = EPRing;
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
if (Xhc->HcCParams.Data.Csz == 0) {
- EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
} else {
- EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
}
//
// No need to remap.
//
if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
- if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
+ if (((UINT8)(Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
} else {
MapOp = EfiPciIoOperationBusMasterRead;
}
- Len = Urb->DataLen;
- Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
+ Len = Urb->DataLen;
+ Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
return EFI_OUT_OF_RESOURCES;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
//
@@ -287,7 +287,7 @@ XhcCreateTransferTrb ( //
// For control transfer, create SETUP_STAGE_TRB first.
//
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
@@ -310,6 +310,7 @@ XhcCreateTransferTrb ( } else {
TrbStart->TrbCtrSetup.TRT = 0;
}
+
//
// Update the cycle bit
//
@@ -321,10 +322,10 @@ XhcCreateTransferTrb ( //
if (Urb->DataLen > 0) {
XhcSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
- TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
- TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);
+ TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);
+ TrbStart->TrbCtrData.Length = (UINT32)Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0;
TrbStart->TrbCtrData.ISP = 1;
@@ -339,18 +340,20 @@ XhcCreateTransferTrb ( } else {
TrbStart->TrbCtrData.DIR = 0;
}
+
//
// Update the cycle bit
//
TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
Urb->TrbNum++;
}
+
//
// For control transfer, create STATUS_STAGE_TRB.
// Get the pointer to next TRB for status stage use
//
XhcSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrStatus.IntTarget = 0;
TrbStart->TrbCtrStatus.IOC = 1;
TrbStart->TrbCtrStatus.CH = 0;
@@ -362,6 +365,7 @@ XhcCreateTransferTrb ( } else {
TrbStart->TrbCtrStatus.DIR = 0;
}
+
//
// Update the cycle bit
//
@@ -387,10 +391,11 @@ XhcCreateTransferTrb ( } else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -422,10 +427,11 @@ XhcCreateTransferTrb ( } else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -446,7 +452,7 @@ XhcCreateTransferTrb ( break;
default:
- DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));
+ DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n", EPType));
ASSERT (FALSE);
break;
}
@@ -454,7 +460,6 @@ XhcCreateTransferTrb ( return EFI_SUCCESS;
}
-
/**
Initialize the XHCI host controller for schedule.
@@ -463,7 +468,7 @@ XhcCreateTransferTrb ( **/
VOID
XhcInitSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
VOID *Dcbaa;
@@ -500,8 +505,8 @@ XhcInitSched ( // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
//
- Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
- Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
+ Entries = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
+ Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
ASSERT (Dcbaa != NULL);
ZeroMem (Dcbaa, Entries);
@@ -529,14 +534,14 @@ XhcInitSched ( Xhc->ScratchEntry = ScratchEntry;
ScratchPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- Xhc->PciIo,
- EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
- Xhc->PageSize,
- (VOID **) &ScratchBuf,
- &ScratchPhy,
- &Xhc->ScratchMap
- );
+ Status = UsbHcAllocateAlignedPages (
+ Xhc->PciIo,
+ EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
+ Xhc->PageSize,
+ (VOID **)&ScratchBuf,
+ &ScratchPhy,
+ &Xhc->ScratchMap
+ );
ASSERT_EFI_ERROR (Status);
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
@@ -547,14 +552,14 @@ XhcInitSched ( //
for (Index = 0; Index < MaxScratchpadBufs; Index++) {
ScratchEntryPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- Xhc->PciIo,
- EFI_SIZE_TO_PAGES (Xhc->PageSize),
- Xhc->PageSize,
- (VOID **) &ScratchEntry[Index],
- &ScratchEntryPhy,
- (VOID **) &ScratchEntryMap[Index]
- );
+ Status = UsbHcAllocateAlignedPages (
+ Xhc->PciIo,
+ EFI_SIZE_TO_PAGES (Xhc->PageSize),
+ Xhc->PageSize,
+ (VOID **)&ScratchEntry[Index],
+ &ScratchEntryPhy,
+ (VOID **)&ScratchEntryMap[Index]
+ );
ASSERT_EFI_ERROR (Status);
ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
//
@@ -562,11 +567,12 @@ XhcInitSched ( //
*ScratchBuf++ = ScratchEntryPhy;
}
+
//
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
// Device Context Base Address Array points to the Scratchpad Buffer Array.
//
- *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
+ *(UINT64 *)Dcbaa = (UINT64)(UINTN)ScratchPhy;
}
//
@@ -579,7 +585,7 @@ XhcInitSched ( // So divide it to two 32-bytes width register access.
//
DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
- XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
+ XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
DEBUG ((DEBUG_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
@@ -596,15 +602,15 @@ XhcInitSched ( // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
// So we set RCS as inverted PCS init value to let Command Ring empty
//
- CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
- CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
+ CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
+ CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
ASSERT ((CmdRingPhy & 0x3F) == 0);
CmdRingPhy |= XHC_CRCR_RCS;
//
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
+ XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT (CmdRingPhy));
XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
//
@@ -621,9 +627,13 @@ XhcInitSched ( // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
//
CreateEventRing (Xhc, &Xhc->EventRing);
- DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
- Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
- Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
+ DEBUG ((
+ DEBUG_INFO,
+ "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
+ Xhc->CmdRing.RingSeg0,
+ (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
+ Xhc->EventRing.EventRingSeg0,
+ (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
));
}
@@ -644,19 +654,20 @@ XhcInitSched ( EFI_STATUS
EFIAPI
XhcRecoverHaltedEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
+
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
@@ -665,8 +676,8 @@ XhcRecoverHaltedEndpoint ( //
// 1) Send Reset endpoint command to transit from halt to stop state
//
- Status = XhcResetEndpoint(Xhc, SlotId, Dci);
- if (EFI_ERROR(Status)) {
+ Status = XhcResetEndpoint (Xhc, SlotId, Dci);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -674,8 +685,8 @@ XhcRecoverHaltedEndpoint ( //
// 2)Set dequeue pointer
//
- Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -706,19 +717,20 @@ Done: EFI_STATUS
EFIAPI
XhcDequeueTrbFromEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
+
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
@@ -727,8 +739,8 @@ XhcDequeueTrbFromEndpoint ( //
// 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
//
- Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ Status = XhcStopEndpoint (Xhc, SlotId, Dci, Urb);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -736,7 +748,7 @@ XhcDequeueTrbFromEndpoint ( //
// 2)Set dequeue pointer
//
- if (Urb->Finished && Urb->Result == EFI_USB_NOERROR) {
+ if (Urb->Finished && (Urb->Result == EFI_USB_NOERROR)) {
//
// Return Already Started to indicate the pending URB is finished.
// This fixes BULK data loss when transfer is detected as timeout
@@ -745,7 +757,7 @@ XhcDequeueTrbFromEndpoint ( Status = EFI_ALREADY_STARTED;
DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));
} else {
- Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
@@ -770,8 +782,8 @@ Done: **/
VOID
CreateEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- OUT EVENT_RING *EventRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ OUT EVENT_RING *EventRing
)
{
VOID *Buf;
@@ -783,15 +795,15 @@ CreateEventRing ( ASSERT (EventRing != NULL);
Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
EventRing->EventRingSeg0 = Buf;
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
- EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
- EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
+ EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
+ EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
@@ -802,12 +814,12 @@ CreateEventRing ( EventRing->EventRingCCS = 1;
Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
- ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
+ ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;
EventRing->ERSTBase = ERSTBase;
ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
@@ -832,12 +844,12 @@ CreateEventRing ( XhcWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET,
- XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)
);
XhcWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET + 4,
- XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)
);
//
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
@@ -848,12 +860,12 @@ CreateEventRing ( XhcWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET,
- XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)ERSTPhy)
);
XhcWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET + 4,
- XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTPhy)
);
//
// Need set IMAN IE bit to enble the ring interrupt
@@ -871,9 +883,9 @@ CreateEventRing ( **/
VOID
CreateTransferRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
)
{
VOID *Buf;
@@ -882,28 +894,28 @@ CreateTransferRing ( Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
- TransferRing->RingSeg0 = Buf;
- TransferRing->TrbNumber = TrbNum;
- TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingPCS = 1;
+ TransferRing->RingSeg0 = Buf;
+ TransferRing->TrbNumber = TrbNum;
+ TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingPCS = 1;
//
// 4.9.2 Transfer Ring Management
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
// point to the first TRB in the ring.
//
- EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
+ EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK;
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
//
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
//
- EndTrb->TC = 1;
+ EndTrb->TC = 1;
//
// Set Cycle bit as other TRB PCS init value
//
@@ -920,11 +932,11 @@ CreateTransferRing ( EFI_STATUS
EFIAPI
XhcFreeEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EventRing
-)
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EventRing
+ )
{
- if(EventRing->EventRingSeg0 == NULL) {
+ if (EventRing->EventRingSeg0 == NULL) {
return EFI_SUCCESS;
}
@@ -948,11 +960,11 @@ XhcFreeEventRing ( **/
VOID
XhcFreeSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Index;
- UINT64 *ScratchEntry;
+ UINT32 Index;
+ UINT64 *ScratchEntry;
if (Xhc->ScratchBuf != NULL) {
ScratchEntry = Xhc->ScratchEntry;
@@ -960,8 +972,9 @@ XhcFreeSched ( //
// Free Scratchpad Buffers
//
- UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *)Xhc->ScratchEntryMap[Index]);
}
+
//
// Free Scratchpad Buffer Array
//
@@ -975,10 +988,10 @@ XhcFreeSched ( Xhc->CmdRing.RingSeg0 = NULL;
}
- XhcFreeEventRing (Xhc,&Xhc->EventRing);
+ XhcFreeEventRing (Xhc, &Xhc->EventRing);
if (Xhc->DCBAA != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));
Xhc->DCBAA = NULL;
}
@@ -1004,30 +1017,31 @@ XhcFreeSched ( **/
BOOLEAN
IsTransferRingTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *Trb,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *Trb,
+ IN URB *Urb
)
{
- LINK_TRB *LinkTrb;
- TRB_TEMPLATE *CheckedTrb;
- UINTN Index;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ LINK_TRB *LinkTrb;
+ TRB_TEMPLATE *CheckedTrb;
+ UINTN Index;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CheckedTrb = Urb->TrbStart;
for (Index = 0; Index < Urb->TrbNum; Index++) {
if (Trb == CheckedTrb) {
return TRUE;
}
+
CheckedTrb++;
//
// If the checked TRB is the link TRB at the end of the transfer ring,
// recircle it to the head of the ring.
//
if (CheckedTrb->Type == TRB_TYPE_LINK) {
- LinkTrb = (LINK_TRB *) CheckedTrb;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));
- CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ LinkTrb = (LINK_TRB *)CheckedTrb;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64)LinkTrb->PtrHi, 32));
+ CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
}
}
@@ -1048,14 +1062,14 @@ IsTransferRingTrb ( **/
BOOLEAN
IsAsyncIntTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *Trb,
- OUT URB **Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *Trb,
+ OUT URB **Urb
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- URB *CheckedUrb;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *CheckedUrb;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1068,7 +1082,6 @@ IsAsyncIntTrb ( return FALSE;
}
-
/**
Check the URB's execution result and update the URB's
result accordingly.
@@ -1081,21 +1094,21 @@ IsAsyncIntTrb ( **/
BOOLEAN
XhcCheckUrbResult (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EVT_TRB_TRANSFER *EvtTrb;
- TRB_TEMPLATE *TRBPtr;
- UINTN Index;
- UINT8 TRBType;
- EFI_STATUS Status;
- URB *AsyncUrb;
- URB *CheckedUrb;
- UINT64 XhcDequeue;
- UINT32 High;
- UINT32 Low;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EVT_TRB_TRANSFER *EvtTrb;
+ TRB_TEMPLATE *TRBPtr;
+ UINTN Index;
+ UINT8 TRBType;
+ EFI_STATUS Status;
+ URB *AsyncUrb;
+ URB *CheckedUrb;
+ UINT64 XhcDequeue;
+ UINT32 High;
+ UINT32 Low;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Xhc != NULL) && (Urb != NULL));
@@ -1136,8 +1149,8 @@ XhcCheckUrbResult ( //
// Need convert pci device address to host address
//
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
- TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
+ TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
//
// Update the status of URB including the pending URB, the URB that is currently checked,
@@ -1145,7 +1158,7 @@ XhcCheckUrbResult ( // This way is used to avoid that those completed async transfer events don't get
// handled in time and are flushed by newer coming events.
//
- if (Xhc->PendingUrb != NULL && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
+ if ((Xhc->PendingUrb != NULL) && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
CheckedUrb = Xhc->PendingUrb;
} else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
CheckedUrb = Urb;
@@ -1159,25 +1172,25 @@ XhcCheckUrbResult ( case TRB_COMPLETION_STALL_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_STALL;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_BABBLE_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_DATA_BUFFER_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_USB_TRANSACTION_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_STOPPED:
@@ -1196,17 +1209,18 @@ XhcCheckUrbResult ( DEBUG ((DEBUG_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
}
- TRBType = (UINT8) (TRBPtr->Type);
+ TRBType = (UINT8)(TRBPtr->Type);
if ((TRBType == TRB_TYPE_DATA_STAGE) ||
(TRBType == TRB_TYPE_NORMAL) ||
- (TRBType == TRB_TYPE_ISOCH)) {
- CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
+ (TRBType == TRB_TYPE_ISOCH))
+ {
+ CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);
}
break;
default:
- DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
goto EXIT;
@@ -1237,9 +1251,9 @@ EXIT: // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
- High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
- XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
+ Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
+ High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
+ XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
@@ -1255,7 +1269,6 @@ EXIT: return Urb->Finished;
}
-
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -1272,18 +1285,18 @@ EXIT: **/
EFI_STATUS
XhcExecTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
)
{
- EFI_STATUS Status;
- UINT8 SlotId;
- UINT8 Dci;
- BOOLEAN Finished;
- EFI_EVENT TimeoutEvent;
- BOOLEAN IndefiniteTimeout;
+ EFI_STATUS Status;
+ UINT8 SlotId;
+ UINT8 Dci;
+ BOOLEAN Finished;
+ EFI_EVENT TimeoutEvent;
+ BOOLEAN IndefiniteTimeout;
Status = EFI_SUCCESS;
Finished = FALSE;
@@ -1298,7 +1311,8 @@ XhcExecTransfer ( if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
}
@@ -1319,9 +1333,11 @@ XhcExecTransfer ( goto DONE;
}
- Status = gBS->SetTimer (TimeoutEvent,
- TimerRelative,
- EFI_TIMER_PERIOD_MILLISECONDS(Timeout));
+ Status = gBS->SetTimer (
+ TimeoutEvent,
+ TimerRelative,
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
+ );
if (EFI_ERROR (Status)) {
goto DONE;
@@ -1335,17 +1351,18 @@ RINGDOORBELL: if (Finished) {
break;
}
+
gBS->Stall (XHC_1_MICROSECOND);
- } while (IndefiniteTimeout || EFI_ERROR(gBS->CheckEvent (TimeoutEvent)));
+ } while (IndefiniteTimeout || EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
DONE:
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
Urb->Result = EFI_USB_ERR_NOTEXECUTE;
} else if (!Finished) {
Urb->Result = EFI_USB_ERR_TIMEOUT;
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
- Status = EFI_DEVICE_ERROR;
+ Status = EFI_DEVICE_ERROR;
}
if (TimeoutEvent != NULL) {
@@ -1369,9 +1386,9 @@ DONE: **/
EFI_STATUS
XhciDelAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpNum
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpNum
)
{
LIST_ENTRY *Entry;
@@ -1389,7 +1406,8 @@ XhciDelAsyncIntTransfer ( Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if ((Urb->Ep.BusAddr == BusAddr) &&
(Urb->Ep.EpAddr == EpNum) &&
- (Urb->Ep.Direction == Direction)) {
+ (Urb->Ep.Direction == Direction))
+ {
//
// Device doesn't finish the IntTransfer until real data comes
// So the TRB should be removed as well.
@@ -1417,13 +1435,13 @@ XhciDelAsyncIntTransfer ( **/
VOID
XhciDelAllAsyncIntTransfers (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- URB *Urb;
- EFI_STATUS Status;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *Urb;
+ EFI_STATUS Status;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1461,18 +1479,18 @@ XhciDelAllAsyncIntTransfers ( **/
URB *
XhciInsertAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- VOID *Data;
- URB *Urb;
+ VOID *Data;
+ URB *Urb;
Data = AllocateZeroPool (DataLen);
if (Data == NULL) {
@@ -1517,17 +1535,18 @@ XhciInsertAsyncIntTransfer ( **/
VOID
XhcUpdateAsyncRequest (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (Urb->Result == EFI_USB_NOERROR) {
Status = XhcCreateTransferTrb (Xhc, Urb);
if (EFI_ERROR (Status)) {
return;
}
+
Status = RingIntTransferDoorBell (Xhc, Urb);
if (EFI_ERROR (Status)) {
return;
@@ -1548,16 +1567,16 @@ XhcUpdateAsyncRequest ( **/
EFI_STATUS
XhcFlushAsyncIntMap (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINTN Len;
- VOID *Map;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN Len;
+ VOID *Map;
PciIo = Xhc->PciIo;
Len = Urb->DataLen;
@@ -1582,8 +1601,8 @@ XhcFlushAsyncIntMap ( goto ON_ERROR;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
return EFI_SUCCESS;
ON_ERROR:
@@ -1600,22 +1619,22 @@ ON_ERROR: VOID
EFIAPI
XhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- USB_XHCI_INSTANCE *Xhc;
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- UINT8 *ProcBuf;
- URB *Urb;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ UINT8 *ProcBuf;
+ URB *Urb;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = (USB_XHCI_INSTANCE*) Context;
+ Xhc = (USB_XHCI_INSTANCE *)Context;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1685,7 +1704,7 @@ XhcMonitorAsyncRequests ( // his callback. Some drivers may has a lower TPL restriction.
//
gBS->RestoreTPL (OldTpl);
- (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
+ (Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
OldTpl = gBS->RaiseTPL (XHC_TPL);
}
@@ -1713,19 +1732,19 @@ XhcMonitorAsyncRequests ( EFI_STATUS
EFIAPI
XhcPollPortStatusChange (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
)
{
- EFI_STATUS Status;
- UINT8 Speed;
- UINT8 SlotId;
- UINT8 Retries;
- USB_DEV_ROUTE RouteChart;
+ EFI_STATUS Status;
+ UINT8 Speed;
+ UINT8 SlotId;
+ UINT8 Retries;
+ USB_DEV_ROUTE RouteChart;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
Retries = XHC_INIT_DEVICE_SLOT_RETRIES;
if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
@@ -1737,13 +1756,14 @@ XhcPollPortStatusChange ( RouteChart.Route.RootPortNum = Port + 1;
RouteChart.Route.TierNum = 1;
} else {
- if(Port < 14) {
+ if (Port < 14) {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
} else {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
}
- RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
- RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
+
+ RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
+ RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
}
SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
@@ -1756,7 +1776,8 @@ XhcPollPortStatusChange ( }
if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
- ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
+ ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0))
+ {
//
// Has a device attached, Identify device speed after port is enabled.
//
@@ -1796,7 +1817,6 @@ XhcPollPortStatusChange ( return Status;
}
-
/**
Calculate the device context index by endpoint address and direction.
@@ -1808,19 +1828,20 @@ XhcPollPortStatusChange ( **/
UINT8
XhcEndpointToDci (
- IN UINT8 EpAddr,
- IN UINT8 Direction
+ IN UINT8 EpAddr,
+ IN UINT8 Direction
)
{
- UINT8 Index;
+ UINT8 Index;
if (EpAddr == 0) {
return 1;
} else {
- Index = (UINT8) (2 * EpAddr);
+ Index = (UINT8)(2 * EpAddr);
if (Direction == EfiUsbDataIn) {
Index += 1;
}
+
return Index;
}
}
@@ -1846,7 +1867,8 @@ XhcBusDevAddrToSlotId ( for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr))
+ {
break;
}
}
@@ -1879,7 +1901,8 @@ XhcRouteStringToSlotId ( for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword))
+ {
break;
}
}
@@ -1903,12 +1926,12 @@ XhcRouteStringToSlotId ( EFI_STATUS
EFIAPI
XhcSyncEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing
)
{
- UINTN Index;
- TRB_TEMPLATE *EvtTrb1;
+ UINTN Index;
+ TRB_TEMPLATE *EvtTrb1;
ASSERT (EvtRing != NULL);
@@ -1925,8 +1948,8 @@ XhcSyncEventRing ( EvtTrb1++;
- if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
- EvtTrb1 = EvtRing->EventRingSeg0;
+ if ((UINTN)EvtTrb1 >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ EvtTrb1 = EvtRing->EventRingSeg0;
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
}
}
@@ -1952,12 +1975,12 @@ XhcSyncEventRing ( EFI_STATUS
EFIAPI
XhcSyncTrsRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRANSFER_RING *TrsRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRANSFER_RING *TrsRing
)
{
- UINTN Index;
- TRB_TEMPLATE *TrsTrb;
+ UINTN Index;
+ TRB_TEMPLATE *TrsTrb;
ASSERT (TrsRing != NULL);
//
@@ -1970,18 +1993,19 @@ XhcSyncTrsRing ( if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
}
+
TrsTrb++;
- if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
- ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
+ if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {
+ ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);
//
// set cycle bit in Link TRB as normal
//
- ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
+ ((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
//
// Toggle PCS maintained by software
//
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
- TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
+ TrsTrb = (TRB_TEMPLATE *)TrsRing->RingSeg0; // Use host address
}
}
@@ -2018,9 +2042,9 @@ XhcSyncTrsRing ( EFI_STATUS
EFIAPI
XhcCheckNewEvent (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
)
{
ASSERT (EvtRing != NULL);
@@ -2035,7 +2059,7 @@ XhcCheckNewEvent ( //
// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
//
- if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
}
@@ -2055,9 +2079,9 @@ XhcCheckNewEvent ( EFI_STATUS
EFIAPI
XhcRingDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
if (SlotId == 0) {
@@ -2080,12 +2104,12 @@ XhcRingDoorBell ( **/
EFI_STATUS
RingIntTransferDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- UINT8 SlotId;
- UINT8 Dci;
+ UINT8 SlotId;
+ UINT8 Dci;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
@@ -2108,11 +2132,11 @@ RingIntTransferDoorBell ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
EFI_STATUS Status;
@@ -2133,15 +2157,16 @@ XhcInitializeDeviceSlot ( CmdTrb.Type = TRB_TYPE_EN_SLOT;
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
@@ -2159,10 +2184,10 @@ XhcInitializeDeviceSlot ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -2183,14 +2208,15 @@ XhcInitializeDeviceSlot ( //
// The device is behind of hub device.
//
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -2217,9 +2243,9 @@ XhcInitializeDeviceSlot ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -2232,6 +2258,7 @@ XhcInitializeDeviceSlot ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -2259,7 +2286,7 @@ XhcInitializeDeviceSlot ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -2271,7 +2298,7 @@ XhcInitializeDeviceSlot ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -2282,20 +2309,20 @@ XhcInitializeDeviceSlot ( //
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT *)OutputContext)->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
@@ -2321,11 +2348,11 @@ XhcInitializeDeviceSlot ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
EFI_STATUS Status;
@@ -2346,15 +2373,16 @@ XhcInitializeDeviceSlot64 ( CmdTrb.Type = TRB_TYPE_EN_SLOT;
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
@@ -2372,10 +2400,10 @@ XhcInitializeDeviceSlot64 ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -2396,14 +2424,15 @@ XhcInitializeDeviceSlot64 ( //
// The device is behind of hub device.
//
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -2430,9 +2459,9 @@ XhcInitializeDeviceSlot64 ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -2445,6 +2474,7 @@ XhcInitializeDeviceSlot64 ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -2472,7 +2502,7 @@ XhcInitializeDeviceSlot64 ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -2484,7 +2514,7 @@ XhcInitializeDeviceSlot64 ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -2495,20 +2525,20 @@ XhcInitializeDeviceSlot64 ( //
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
@@ -2519,7 +2549,6 @@ XhcInitializeDeviceSlot64 ( return Status;
}
-
/**
Disable the specified device slot.
@@ -2532,8 +2561,8 @@ XhcInitializeDeviceSlot64 ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -2549,7 +2578,8 @@ XhcDisableSlotCmd ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -2570,16 +2600,17 @@ XhcDisableSlotCmd ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -2594,6 +2625,7 @@ XhcDisableSlotCmd ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -2616,6 +2648,7 @@ XhcDisableSlotCmd ( if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -2639,8 +2672,8 @@ XhcDisableSlotCmd ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -2656,7 +2689,8 @@ XhcDisableSlotCmd64 ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -2677,16 +2711,17 @@ XhcDisableSlotCmd64 ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -2701,6 +2736,7 @@ XhcDisableSlotCmd64 ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -2721,8 +2757,9 @@ XhcDisableSlotCmd64 ( }
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -2749,23 +2786,23 @@ XhcDisableSlotCmd64 ( UINT8
EFIAPI
XhcInitializeEndpointContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN INPUT_CONTEXT *InputContext,
- IN USB_INTERFACE_DESCRIPTOR *IfDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN INPUT_CONTEXT *InputContext,
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc
)
{
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
- TRANSFER_RING *EndpointTransferRing;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+ TRANSFER_RING *EndpointTransferRing;
MaxDci = 0;
@@ -2815,14 +2852,16 @@ XhcInitializeEndpointContext ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -2834,6 +2873,7 @@ XhcInitializeEndpointContext ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -2862,6 +2902,7 @@ XhcInitializeEndpointContext ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -2873,7 +2914,7 @@ XhcInitializeEndpointContext ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -2888,15 +2929,18 @@ XhcInitializeEndpointContext ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -2915,8 +2959,8 @@ XhcInitializeEndpointContext ( ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -2941,23 +2985,23 @@ XhcInitializeEndpointContext ( UINT8
EFIAPI
XhcInitializeEndpointContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN INPUT_CONTEXT_64 *InputContext,
- IN USB_INTERFACE_DESCRIPTOR *IfDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN INPUT_CONTEXT_64 *InputContext,
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc
)
{
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
- TRANSFER_RING *EndpointTransferRing;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+ TRANSFER_RING *EndpointTransferRing;
MaxDci = 0;
@@ -3007,14 +3051,16 @@ XhcInitializeEndpointContext64 ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -3026,6 +3072,7 @@ XhcInitializeEndpointContext64 ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -3054,6 +3101,7 @@ XhcInitializeEndpointContext64 ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -3065,7 +3113,7 @@ XhcInitializeEndpointContext64 ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -3080,15 +3128,18 @@ XhcInitializeEndpointContext64 ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint64[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -3107,8 +3158,8 @@ XhcInitializeEndpointContext64 ( ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -3132,23 +3183,24 @@ XhcInitializeEndpointContext64 ( EFI_STATUS
EFIAPI
XhcSetConfigCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- UINT8 Index;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ UINT8 Index;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT *InputContext;
DEVICE_CONTEXT *OutputContext;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -3186,7 +3238,7 @@ XhcSetConfigCmd ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3195,9 +3247,9 @@ XhcSetConfigCmd ( DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
@@ -3222,23 +3274,24 @@ XhcSetConfigCmd ( EFI_STATUS
EFIAPI
XhcSetConfigCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- UINT8 Index;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ UINT8 Index;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT_64 *InputContext;
DEVICE_CONTEXT_64 *OutputContext;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -3276,7 +3329,7 @@ XhcSetConfigCmd64 ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3285,9 +3338,9 @@ XhcSetConfigCmd64 ( DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
@@ -3313,15 +3366,15 @@ XhcSetConfigCmd64 ( EFI_STATUS
EFIAPI
XhcStopEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *PendingUrb OPTIONAL
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *PendingUrb OPTIONAL
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
DEBUG ((DEBUG_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
@@ -3356,13 +3409,13 @@ XhcStopEndpoint ( CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
CmdTrbStopED.EDID = Dci;
CmdTrbStopED.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbStopED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
@@ -3385,9 +3438,9 @@ XhcStopEndpoint ( EFI_STATUS
EFIAPI
XhcResetEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
EFI_STATUS Status;
@@ -3404,13 +3457,13 @@ XhcResetEndpoint ( CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
CmdTrbResetED.EDID = Dci;
CmdTrbResetED.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbResetED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
@@ -3433,10 +3486,10 @@ XhcResetEndpoint ( EFI_STATUS
EFIAPI
XhcSetTrDequeuePointer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
)
{
EFI_STATUS Status;
@@ -3450,20 +3503,20 @@ XhcSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;
CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
CmdSetTRDeq.Endpoint = Dci;
CmdSetTRDeq.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdSetTRDeq,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
@@ -3485,26 +3538,26 @@ XhcSetTrDequeuePointer ( EFI_STATUS
EFIAPI
XhcSetInterface (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDescActive;
- USB_INTERFACE_DESCRIPTOR *IfDescSet;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *RingSeg;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *RingSeg;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT *InputContext;
@@ -3533,18 +3586,18 @@ XhcSetInterface ( MaxDci = 0;
IfDescActive = NULL;
- IfDescSet = NULL;
+ IfDescSet = NULL;
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
- while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {
if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
- if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {
if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
//
// Find out the active interface descriptor.
//
IfDescActive = IfDesc;
- } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {
//
// Find out the interface descriptor to set.
//
@@ -3552,6 +3605,7 @@ XhcSetInterface ( }
}
}
+
IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
@@ -3570,8 +3624,8 @@ XhcSetInterface ( //
if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
- NumEp = IfDescActive->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
+ NumEp = IfDescActive->NumEndpoints;
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
@@ -3582,14 +3636,15 @@ XhcSetInterface ( continue;
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
if (Dci > MaxDci) {
MaxDci = Dci;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
@@ -3598,6 +3653,7 @@ XhcSetInterface ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
@@ -3607,6 +3663,7 @@ XhcSetInterface ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
}
@@ -3646,7 +3703,7 @@ XhcSetInterface ( // 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3655,9 +3712,9 @@ XhcSetInterface ( DEBUG ((DEBUG_INFO, "SetInterface: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
@@ -3665,7 +3722,7 @@ XhcSetInterface ( //
// Update the active AlternateSetting.
//
- Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;
}
}
@@ -3687,26 +3744,26 @@ XhcSetInterface ( EFI_STATUS
EFIAPI
XhcSetInterface64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDescActive;
- USB_INTERFACE_DESCRIPTOR *IfDescSet;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *RingSeg;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *RingSeg;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT_64 *InputContext;
@@ -3735,18 +3792,18 @@ XhcSetInterface64 ( MaxDci = 0;
IfDescActive = NULL;
- IfDescSet = NULL;
+ IfDescSet = NULL;
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
- while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {
if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
- if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {
if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
//
// Find out the active interface descriptor.
//
IfDescActive = IfDesc;
- } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {
//
// Find out the interface descriptor to set.
//
@@ -3754,6 +3811,7 @@ XhcSetInterface64 ( }
}
}
+
IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
@@ -3772,8 +3830,8 @@ XhcSetInterface64 ( //
if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
- NumEp = IfDescActive->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
+ NumEp = IfDescActive->NumEndpoints;
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
@@ -3784,14 +3842,15 @@ XhcSetInterface64 ( continue;
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
if (Dci > MaxDci) {
MaxDci = Dci;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
@@ -3800,6 +3859,7 @@ XhcSetInterface64 ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
@@ -3809,6 +3869,7 @@ XhcSetInterface64 ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
}
@@ -3848,7 +3909,7 @@ XhcSetInterface64 ( // 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3857,9 +3918,9 @@ XhcSetInterface64 ( DEBUG ((DEBUG_INFO, "SetInterface64: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
@@ -3867,7 +3928,7 @@ XhcSetInterface64 ( //
// Update the active AlternateSetting.
//
- Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;
}
}
@@ -3887,9 +3948,9 @@ XhcSetInterface64 ( EFI_STATUS
EFIAPI
XhcEvaluateContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
EFI_STATUS Status;
@@ -3910,7 +3971,7 @@ XhcEvaluateContext ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -3919,13 +3980,14 @@ XhcEvaluateContext ( DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -3942,9 +4004,9 @@ XhcEvaluateContext ( EFI_STATUS
EFIAPI
XhcEvaluateContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
EFI_STATUS Status;
@@ -3965,7 +4027,7 @@ XhcEvaluateContext64 ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -3974,17 +4036,17 @@ XhcEvaluateContext64 ( DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
-
/**
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
@@ -3999,11 +4061,11 @@ XhcEvaluateContext64 ( **/
EFI_STATUS
XhcConfigHubContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
EFI_STATUS Status;
@@ -4027,14 +4089,14 @@ XhcConfigHubContext ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -4042,14 +4104,15 @@ XhcConfigHubContext ( CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -4067,11 +4130,11 @@ XhcConfigHubContext ( **/
EFI_STATUS
XhcConfigHubContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
EFI_STATUS Status;
@@ -4095,14 +4158,14 @@ XhcConfigHubContext64 ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -4110,13 +4173,14 @@ XhcConfigHubContext64 ( CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h index 3f9cdb1c36..7c85f7993b 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h @@ -10,73 +10,73 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_XHCI_SCHED_H_
#define _EFI_XHCI_SCHED_H_
-#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
-#define XHC_INIT_DEVICE_SLOT_RETRIES 1
+#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define XHC_INIT_DEVICE_SLOT_RETRIES 1
//
// Transfer types, used in URB to identify the transfer type
//
-#define XHC_CTRL_TRANSFER 0x01
-#define XHC_BULK_TRANSFER 0x02
-#define XHC_INT_TRANSFER_SYNC 0x04
-#define XHC_INT_TRANSFER_ASYNC 0x08
-#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
+#define XHC_CTRL_TRANSFER 0x01
+#define XHC_BULK_TRANSFER 0x02
+#define XHC_INT_TRANSFER_SYNC 0x04
+#define XHC_INT_TRANSFER_ASYNC 0x08
+#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
//
// 6.4.6 TRB Types
//
-#define TRB_TYPE_NORMAL 1
-#define TRB_TYPE_SETUP_STAGE 2
-#define TRB_TYPE_DATA_STAGE 3
-#define TRB_TYPE_STATUS_STAGE 4
-#define TRB_TYPE_ISOCH 5
-#define TRB_TYPE_LINK 6
-#define TRB_TYPE_EVENT_DATA 7
-#define TRB_TYPE_NO_OP 8
-#define TRB_TYPE_EN_SLOT 9
-#define TRB_TYPE_DIS_SLOT 10
-#define TRB_TYPE_ADDRESS_DEV 11
-#define TRB_TYPE_CON_ENDPOINT 12
-#define TRB_TYPE_EVALU_CONTXT 13
-#define TRB_TYPE_RESET_ENDPOINT 14
-#define TRB_TYPE_STOP_ENDPOINT 15
-#define TRB_TYPE_SET_TR_DEQUE 16
-#define TRB_TYPE_RESET_DEV 17
-#define TRB_TYPE_GET_PORT_BANW 21
-#define TRB_TYPE_FORCE_HEADER 22
-#define TRB_TYPE_NO_OP_COMMAND 23
-#define TRB_TYPE_TRANS_EVENT 32
-#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
-#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
-#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
-#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
-#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
+#define TRB_TYPE_NORMAL 1
+#define TRB_TYPE_SETUP_STAGE 2
+#define TRB_TYPE_DATA_STAGE 3
+#define TRB_TYPE_STATUS_STAGE 4
+#define TRB_TYPE_ISOCH 5
+#define TRB_TYPE_LINK 6
+#define TRB_TYPE_EVENT_DATA 7
+#define TRB_TYPE_NO_OP 8
+#define TRB_TYPE_EN_SLOT 9
+#define TRB_TYPE_DIS_SLOT 10
+#define TRB_TYPE_ADDRESS_DEV 11
+#define TRB_TYPE_CON_ENDPOINT 12
+#define TRB_TYPE_EVALU_CONTXT 13
+#define TRB_TYPE_RESET_ENDPOINT 14
+#define TRB_TYPE_STOP_ENDPOINT 15
+#define TRB_TYPE_SET_TR_DEQUE 16
+#define TRB_TYPE_RESET_DEV 17
+#define TRB_TYPE_GET_PORT_BANW 21
+#define TRB_TYPE_FORCE_HEADER 22
+#define TRB_TYPE_NO_OP_COMMAND 23
+#define TRB_TYPE_TRANS_EVENT 32
+#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
+#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
+#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
+#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
+#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
//
// Endpoint Type (EP Type).
//
-#define ED_NOT_VALID 0
-#define ED_ISOCH_OUT 1
-#define ED_BULK_OUT 2
-#define ED_INTERRUPT_OUT 3
-#define ED_CONTROL_BIDIR 4
-#define ED_ISOCH_IN 5
-#define ED_BULK_IN 6
-#define ED_INTERRUPT_IN 7
+#define ED_NOT_VALID 0
+#define ED_ISOCH_OUT 1
+#define ED_BULK_OUT 2
+#define ED_INTERRUPT_OUT 3
+#define ED_CONTROL_BIDIR 4
+#define ED_ISOCH_IN 5
+#define ED_BULK_IN 6
+#define ED_INTERRUPT_IN 7
//
// 6.4.5 TRB Completion Codes
//
-#define TRB_COMPLETION_INVALID 0
-#define TRB_COMPLETION_SUCCESS 1
-#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
-#define TRB_COMPLETION_BABBLE_ERROR 3
-#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
-#define TRB_COMPLETION_TRB_ERROR 5
-#define TRB_COMPLETION_STALL_ERROR 6
-#define TRB_COMPLETION_SHORT_PACKET 13
-#define TRB_COMPLETION_STOPPED 26
-#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
+#define TRB_COMPLETION_INVALID 0
+#define TRB_COMPLETION_SUCCESS 1
+#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
+#define TRB_COMPLETION_BABBLE_ERROR 3
+#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
+#define TRB_COMPLETION_TRB_ERROR 5
+#define TRB_COMPLETION_STALL_ERROR 6
+#define TRB_COMPLETION_SHORT_PACKET 13
+#define TRB_COMPLETION_STOPPED 26
+#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
//
// The topology string used to present usb device location
@@ -85,15 +85,15 @@ typedef struct _USB_DEV_TOPOLOGY { //
// The tier concatenation of down stream port.
//
- UINT32 RouteString:20;
+ UINT32 RouteString : 20;
//
// The root port number of the chain.
//
- UINT32 RootPortNum:8;
+ UINT32 RootPortNum : 8;
//
// The Tier the device reside.
//
- UINT32 TierNum:4;
+ UINT32 TierNum : 4;
} USB_DEV_TOPOLOGY;
//
@@ -126,33 +126,33 @@ typedef struct _USB_ENDPOINT { // TRB Template
//
typedef struct _TRB_TEMPLATE {
- UINT32 Parameter1;
+ UINT32 Parameter1;
- UINT32 Parameter2;
+ UINT32 Parameter2;
- UINT32 Status;
+ UINT32 Status;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:9;
- UINT32 Type:6;
- UINT32 Control:16;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 9;
+ UINT32 Type : 6;
+ UINT32 Control : 16;
} TRB_TEMPLATE;
typedef struct _TRANSFER_RING {
- VOID *RingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *RingEnqueue;
- TRB_TEMPLATE *RingDequeue;
- UINT32 RingPCS;
+ VOID *RingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *RingEnqueue;
+ TRB_TEMPLATE *RingDequeue;
+ UINT32 RingPCS;
} TRANSFER_RING;
typedef struct _EVENT_RING {
- VOID *ERSTBase;
- VOID *EventRingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *EventRingEnqueue;
- TRB_TEMPLATE *EventRingDequeue;
- UINT32 EventRingCCS;
+ VOID *ERSTBase;
+ VOID *EventRingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *EventRingEnqueue;
+ TRB_TEMPLATE *EventRingDequeue;
+ UINT32 EventRingCCS;
} EVENT_RING;
//
@@ -160,39 +160,39 @@ typedef struct _EVENT_RING { // usb requests.
//
typedef struct _URB {
- UINT32 Signature;
- LIST_ENTRY UrbList;
+ UINT32 Signature;
+ LIST_ENTRY UrbList;
//
// Usb Device URB related information
//
- USB_ENDPOINT Ep;
- EFI_USB_DEVICE_REQUEST *Request;
- VOID *Data;
- UINTN DataLen;
- VOID *DataPhy;
- VOID *DataMap;
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ USB_ENDPOINT Ep;
+ EFI_USB_DEVICE_REQUEST *Request;
+ VOID *Data;
+ UINTN DataLen;
+ VOID *DataPhy;
+ VOID *DataMap;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
//
// Execute result
//
- UINT32 Result;
+ UINT32 Result;
//
// completed data length
//
- UINTN Completed;
+ UINTN Completed;
//
// Command/Tranfer Ring info
//
- TRANSFER_RING *Ring;
- TRB_TEMPLATE *TrbStart;
- TRB_TEMPLATE *TrbEnd;
- UINTN TrbNum;
- BOOLEAN StartDone;
- BOOLEAN EndDone;
- BOOLEAN Finished;
-
- TRB_TEMPLATE *EvtTrb;
+ TRANSFER_RING *Ring;
+ TRB_TEMPLATE *TrbStart;
+ TRB_TEMPLATE *TrbEnd;
+ UINTN TrbNum;
+ BOOLEAN StartDone;
+ BOOLEAN EndDone;
+ BOOLEAN Finished;
+
+ TRB_TEMPLATE *EvtTrb;
} URB;
//
@@ -203,11 +203,11 @@ typedef struct _URB { // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
//
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
- UINT32 PtrLo;
- UINT32 PtrHi;
- UINT32 RingTrbSize:16;
- UINT32 RsvdZ1:16;
- UINT32 RsvdZ2;
+ UINT32 PtrLo;
+ UINT32 PtrHi;
+ UINT32 RingTrbSize : 16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 RsvdZ2;
} EVENT_RING_SEG_TABLE_ENTRY;
//
@@ -217,25 +217,25 @@ typedef struct _EVENT_RING_SEG_TABLE_ENTRY { // Rings, and to define the Data stage information for Control Transfer Rings.
//
typedef struct _TRANSFER_TRB_NORMAL {
- UINT32 TRBPtrLo;
-
- UINT32 TRBPtrHi;
-
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:2;
- UINT32 BEI:1;
- UINT32 Type:6;
- UINT32 RsvdZ2:16;
+ UINT32 TRBPtrLo;
+
+ UINT32 TRBPtrHi;
+
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 2;
+ UINT32 BEI : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ2 : 16;
} TRANSFER_TRB_NORMAL;
//
@@ -243,25 +243,25 @@ typedef struct _TRANSFER_TRB_NORMAL { // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
//
typedef struct _TRANSFER_TRB_CONTROL_SETUP {
- UINT32 bmRequestType:8;
- UINT32 bRequest:8;
- UINT32 wValue:16;
-
- UINT32 wIndex:16;
- UINT32 wLength:16;
-
- UINT32 Length:17;
- UINT32 RsvdZ1:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:4;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ3:3;
- UINT32 Type:6;
- UINT32 TRT:2;
- UINT32 RsvdZ4:14;
+ UINT32 bmRequestType : 8;
+ UINT32 bRequest : 8;
+ UINT32 wValue : 16;
+
+ UINT32 wIndex : 16;
+ UINT32 wLength : 16;
+
+ UINT32 Length : 17;
+ UINT32 RsvdZ1 : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 4;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ3 : 3;
+ UINT32 Type : 6;
+ UINT32 TRT : 2;
+ UINT32 RsvdZ4 : 14;
} TRANSFER_TRB_CONTROL_SETUP;
//
@@ -269,25 +269,25 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_DATA {
- UINT32 TRBPtrLo;
-
- UINT32 TRBPtrHi;
-
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:3;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ2:15;
+ UINT32 TRBPtrLo;
+
+ UINT32 TRBPtrHi;
+
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 3;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ2 : 15;
} TRANSFER_TRB_CONTROL_DATA;
//
@@ -295,21 +295,21 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_STATUS {
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 RsvdZ3:22;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 RsvdZ4:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ5:4;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ6:15;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 RsvdZ3 : 22;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 RsvdZ4 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ5 : 4;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ6 : 15;
} TRANSFER_TRB_CONTROL_STATUS;
//
@@ -318,21 +318,21 @@ typedef struct _TRANSFER_TRB_CONTROL_STATUS { // for more information on the use and operation of Transfer Events.
//
typedef struct _EVT_TRB_TRANSFER {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 Length:24;
- UINT32 Completecode:8;
+ UINT32 Length : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:1;
- UINT32 ED:1;
- UINT32 RsvdZ2:7;
- UINT32 Type:6;
- UINT32 EndpointId:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 1;
+ UINT32 ED : 1;
+ UINT32 RsvdZ2 : 7;
+ UINT32 Type : 6;
+ UINT32 EndpointId : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} EVT_TRB_TRANSFER;
//
@@ -341,26 +341,26 @@ typedef struct _EVT_TRB_TRANSFER { // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
//
typedef struct _EVT_TRB_COMMAND_COMPLETION {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 RsvdZ2:24;
- UINT32 Completecode:8;
+ UINT32 RsvdZ2 : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 VFID:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 VFID : 8;
+ UINT32 SlotId : 8;
} EVT_TRB_COMMAND_COMPLETION;
typedef union _TRB {
- TRB_TEMPLATE TrbTemplate;
- TRANSFER_TRB_NORMAL TrbNormal;
- TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
- TRANSFER_TRB_CONTROL_DATA TrbCtrData;
- TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
+ TRB_TEMPLATE TrbTemplate;
+ TRANSFER_TRB_NORMAL TrbNormal;
+ TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
+ TRANSFER_TRB_CONTROL_DATA TrbCtrData;
+ TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
} TRB;
//
@@ -369,14 +369,14 @@ typedef union _TRB { // mechanisms offered by the xHCI.
//
typedef struct _CMD_TRB_NO_OP {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_NO_OP;
//
@@ -385,14 +385,14 @@ typedef struct _CMD_TRB_NO_OP { // selected slot to the host in a Command Completion Event.
//
typedef struct _CMD_TRB_ENABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_ENABLE_SLOT;
//
@@ -401,15 +401,15 @@ typedef struct _CMD_TRB_ENABLE_SLOT { // internal xHC resources assigned to the slot.
//
typedef struct _CMD_TRB_DISABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:8;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_DISABLE_SLOT;
//
@@ -419,18 +419,18 @@ typedef struct _CMD_TRB_DISABLE_SLOT { // issue a SET_ADDRESS request to the USB device.
//
typedef struct _CMD_TRB_ADDRESS_DEVICE {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 BSR:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 BSR : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_ADDRESS_DEVICE;
//
@@ -439,18 +439,18 @@ typedef struct _CMD_TRB_ADDRESS_DEVICE { // endpoints selected by the command.
//
typedef struct _CMD_TRB_CONFIG_ENDPOINT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 DC:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 DC : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_CONFIG_ENDPOINT;
//
@@ -460,17 +460,17 @@ typedef struct _CMD_TRB_CONFIG_ENDPOINT { // shall evaluate any changes
//
typedef struct _CMD_TRB_EVALUATE_CONTEXT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_EVALUATE_CONTEXT;
//
@@ -478,17 +478,17 @@ typedef struct _CMD_TRB_EVALUATE_CONTEXT { // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
//
typedef struct _CMD_TRB_RESET_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:8;
- UINT32 TSP:1;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:3;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 8;
+ UINT32 TSP : 1;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 3;
+ UINT32 SlotId : 8;
} CMD_TRB_RESET_ENDPOINT;
//
@@ -497,17 +497,17 @@ typedef struct _CMD_TRB_RESET_ENDPOINT { // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
//
typedef struct _CMD_TRB_STOP_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:2;
- UINT32 SP:1;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 2;
+ UINT32 SP : 1;
+ UINT32 SlotId : 8;
} CMD_TRB_STOP_ENDPOINT;
//
@@ -516,19 +516,19 @@ typedef struct _CMD_TRB_STOP_ENDPOINT { // Pointer and DCS fields of an Endpoint or Stream Context.
//
typedef struct _CMD_SET_TR_DEQ_POINTER {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:16;
- UINT32 StreamID:16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 StreamID : 16;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 Endpoint:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 Endpoint : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} CMD_SET_TR_DEQ_POINTER;
//
@@ -536,211 +536,207 @@ typedef struct _CMD_SET_TR_DEQ_POINTER { // A Link TRB provides support for non-contiguous TRB Rings.
//
typedef struct _LINK_TRB {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:22;
- UINT32 InterTarget:10;
+ UINT32 RsvdZ1 : 22;
+ UINT32 InterTarget : 10;
- UINT32 CycleBit:1;
- UINT32 TC:1;
- UINT32 RsvdZ2:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ3:4;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 CycleBit : 1;
+ UINT32 TC : 1;
+ UINT32 RsvdZ2 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ3 : 4;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} LINK_TRB;
//
// 6.2.2 Slot Context
//
typedef struct _SLOT_CONTEXT {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
-
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
-
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
-
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
-
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
+
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
+
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
+
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
+
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} SLOT_CONTEXT;
typedef struct _SLOT_CONTEXT_64 {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
-
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
-
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
-
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
-
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
-
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
-
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
+
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
+
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
+
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
+
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} SLOT_CONTEXT_64;
-
//
// 6.2.3 Endpoint Context
//
typedef struct _ENDPOINT_CONTEXT {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
-
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
-
- UINT32 PtrLo;
-
- UINT32 PtrHi;
-
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
-
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
+
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
+
+ UINT32 PtrLo;
+
+ UINT32 PtrHi;
+
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
+
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} ENDPOINT_CONTEXT;
typedef struct _ENDPOINT_CONTEXT_64 {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
-
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
-
- UINT32 PtrLo;
-
- UINT32 PtrHi;
-
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
-
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
-
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
-
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
+
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
+
+ UINT32 PtrLo;
+
+ UINT32 PtrHi;
+
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
+
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} ENDPOINT_CONTEXT_64;
-
//
// 6.2.5.1 Input Control Context
//
typedef struct _INPUT_CONTRL_CONTEXT {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
} INPUT_CONTRL_CONTEXT;
typedef struct _INPUT_CONTRL_CONTEXT_64 {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
} INPUT_CONTRL_CONTEXT_64;
//
// 6.2.1 Device Context
//
typedef struct _DEVICE_CONTEXT {
- SLOT_CONTEXT Slot;
- ENDPOINT_CONTEXT EP[31];
+ SLOT_CONTEXT Slot;
+ ENDPOINT_CONTEXT EP[31];
} DEVICE_CONTEXT;
typedef struct _DEVICE_CONTEXT_64 {
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} DEVICE_CONTEXT_64;
//
@@ -753,12 +749,11 @@ typedef struct _INPUT_CONTEXT { } INPUT_CONTEXT;
typedef struct _INPUT_CONTEXT_64 {
- INPUT_CONTRL_CONTEXT_64 InputControlContext;
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ INPUT_CONTRL_CONTEXT_64 InputControlContext;
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} INPUT_CONTEXT_64;
-
/**
Initialize the XHCI host controller for schedule.
@@ -767,7 +762,7 @@ typedef struct _INPUT_CONTEXT_64 { **/
VOID
XhcInitSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -778,7 +773,7 @@ XhcInitSched ( **/
VOID
XhcFreeSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -792,8 +787,8 @@ XhcFreeSched ( **/
EFI_STATUS
RingIntTransferDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -811,10 +806,10 @@ RingIntTransferDoorBell ( **/
EFI_STATUS
XhcExecTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
);
/**
@@ -831,9 +826,9 @@ XhcExecTransfer ( **/
EFI_STATUS
XhciDelAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpNum
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpNum
);
/**
@@ -844,7 +839,7 @@ XhciDelAsyncIntTransfer ( **/
VOID
XhciDelAllAsyncIntTransfers (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -865,14 +860,14 @@ XhciDelAllAsyncIntTransfers ( **/
URB *
XhciInsertAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
);
/**
@@ -883,7 +878,7 @@ XhciInsertAsyncIntTransfer ( **/
VOID
XhcSetBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -894,7 +889,7 @@ XhcSetBiosOwnership ( **/
VOID
XhcClearBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -924,8 +919,8 @@ XhcRouteStringToSlotId ( **/
UINT8
XhcEndpointToDci (
- IN UINT8 EpAddr,
- IN UINT8 Direction
+ IN UINT8 EpAddr,
+ IN UINT8 Direction
);
/**
@@ -941,9 +936,9 @@ XhcEndpointToDci ( EFI_STATUS
EFIAPI
XhcRingDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -956,8 +951,8 @@ XhcRingDoorBell ( VOID
EFIAPI
XhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
);
/**
@@ -975,10 +970,10 @@ XhcMonitorAsyncRequests ( EFI_STATUS
EFIAPI
XhcPollPortStatusChange (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
);
/**
@@ -995,14 +990,13 @@ XhcPollPortStatusChange ( **/
EFI_STATUS
XhcConfigHubContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
-
/**
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
@@ -1017,14 +1011,13 @@ XhcConfigHubContext ( **/
EFI_STATUS
XhcConfigHubContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
-
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@@ -1039,13 +1032,12 @@ XhcConfigHubContext64 ( EFI_STATUS
EFIAPI
XhcSetConfigCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
-
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@@ -1060,10 +1052,10 @@ XhcSetConfigCmd ( EFI_STATUS
EFIAPI
XhcSetConfigCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
/**
@@ -1081,11 +1073,11 @@ XhcSetConfigCmd64 ( EFI_STATUS
EFIAPI
XhcSetInterface (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
);
/**
@@ -1103,11 +1095,11 @@ XhcSetInterface ( EFI_STATUS
EFIAPI
XhcSetInterface64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
);
/**
@@ -1141,11 +1133,11 @@ XhcBusDevAddrToSlotId ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1163,11 +1155,11 @@ XhcInitializeDeviceSlot ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1183,12 +1175,11 @@ XhcInitializeDeviceSlot64 ( EFI_STATUS
EFIAPI
XhcEvaluateContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
-
/**
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
@@ -1202,12 +1193,11 @@ XhcEvaluateContext ( EFI_STATUS
EFIAPI
XhcEvaluateContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
-
/**
Disable the specified device slot.
@@ -1220,11 +1210,10 @@ XhcEvaluateContext64 ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
);
-
/**
Disable the specified device slot.
@@ -1237,11 +1226,10 @@ XhcDisableSlotCmd ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
);
-
/**
Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
@@ -1254,8 +1242,8 @@ XhcDisableSlotCmd64 ( EFI_STATUS
EFIAPI
XhcSyncTrsRing (
- IN USB_XHCI_INSTANCE *Xhc,
- TRANSFER_RING *TrsRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ TRANSFER_RING *TrsRing
);
/**
@@ -1270,8 +1258,8 @@ XhcSyncTrsRing ( EFI_STATUS
EFIAPI
XhcSyncEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- EVENT_RING *EvtRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ EVENT_RING *EvtRing
);
/**
@@ -1288,9 +1276,9 @@ XhcSyncEventRing ( EFI_STATUS
EFIAPI
XhcCheckNewEvent (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
);
/**
@@ -1303,9 +1291,9 @@ XhcCheckNewEvent ( **/
VOID
CreateTransferRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
);
/**
@@ -1317,8 +1305,8 @@ CreateTransferRing ( **/
VOID
CreateEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- OUT EVENT_RING *EventRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ OUT EVENT_RING *EventRing
);
/**
@@ -1338,8 +1326,8 @@ CreateEventRing ( EFI_STATUS
EFIAPI
XhcRecoverHaltedEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1358,8 +1346,8 @@ XhcRecoverHaltedEndpoint ( EFI_STATUS
EFIAPI
XhcDequeueTrbFromEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1377,10 +1365,10 @@ XhcDequeueTrbFromEndpoint ( EFI_STATUS
EFIAPI
XhcStopEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *PendingUrb OPTIONAL
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *PendingUrb OPTIONAL
);
/**
@@ -1397,9 +1385,9 @@ XhcStopEndpoint ( EFI_STATUS
EFIAPI
XhcResetEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -1418,10 +1406,10 @@ XhcResetEndpoint ( EFI_STATUS
EFIAPI
XhcSetTrDequeuePointer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
);
/**
@@ -1442,19 +1430,19 @@ XhcSetTrDequeuePointer ( @return Created URB or NULL
**/
-URB*
+URB *
XhcCreateUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
);
/**
@@ -1466,8 +1454,8 @@ XhcCreateUrb ( **/
VOID
XhcFreeUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1481,8 +1469,8 @@ XhcFreeUrb ( **/
EFI_STATUS
XhcCreateTransferTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c b/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c index c4d93aea25..c8e49e1864 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c @@ -32,11 +32,11 @@ EDKII_IOMMU_PPI *mIoMmu; **/
EFI_STATUS
IoMmuMap (
- IN EDKII_IOMMU_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ IN EDKII_IOMMU_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
)
{
EFI_STATUS Status;
@@ -54,23 +54,25 @@ IoMmuMap ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
switch (Operation) {
- case EdkiiIoMmuOperationBusMasterRead:
- case EdkiiIoMmuOperationBusMasterRead64:
- Attribute = EDKII_IOMMU_ACCESS_READ;
- break;
- case EdkiiIoMmuOperationBusMasterWrite:
- case EdkiiIoMmuOperationBusMasterWrite64:
- Attribute = EDKII_IOMMU_ACCESS_WRITE;
- break;
- case EdkiiIoMmuOperationBusMasterCommonBuffer:
- case EdkiiIoMmuOperationBusMasterCommonBuffer64:
- Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
- break;
- default:
- ASSERT(FALSE);
- return EFI_INVALID_PARAMETER;
+ case EdkiiIoMmuOperationBusMasterRead:
+ case EdkiiIoMmuOperationBusMasterRead64:
+ Attribute = EDKII_IOMMU_ACCESS_READ;
+ break;
+ case EdkiiIoMmuOperationBusMasterWrite:
+ case EdkiiIoMmuOperationBusMasterWrite64:
+ Attribute = EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ case EdkiiIoMmuOperationBusMasterCommonBuffer:
+ case EdkiiIoMmuOperationBusMasterCommonBuffer64:
+ Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
}
+
Status = mIoMmu->SetAttribute (
mIoMmu,
*Mapping,
@@ -81,9 +83,10 @@ IoMmuMap ( }
} else {
*DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
- *Mapping = NULL;
- Status = EFI_SUCCESS;
+ *Mapping = NULL;
+ Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -98,7 +101,7 @@ IoMmuMap ( **/
EFI_STATUS
IoMmuUnmap (
- IN VOID *Mapping
+ IN VOID *Mapping
)
{
EFI_STATUS Status;
@@ -109,6 +112,7 @@ IoMmuUnmap ( } else {
Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -142,7 +146,7 @@ IoMmuAllocateBuffer ( UINTN NumberOfBytes;
EFI_PHYSICAL_ADDRESS HostPhyAddress;
- *HostAddress = NULL;
+ *HostAddress = NULL;
*DeviceAddress = 0;
if (mIoMmu != NULL) {
@@ -157,18 +161,19 @@ IoMmuAllocateBuffer ( return EFI_OUT_OF_RESOURCES;
}
- NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);
- Status = mIoMmu->Map (
- mIoMmu,
- EdkiiIoMmuOperationBusMasterCommonBuffer,
- *HostAddress,
- &NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+ NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
+ Status = mIoMmu->Map (
+ mIoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ *HostAddress,
+ &NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
Status = mIoMmu->SetAttribute (
mIoMmu,
*Mapping,
@@ -186,10 +191,12 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *)(UINTN)HostPhyAddress;
+
+ *HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
- *Mapping = NULL;
+ *Mapping = NULL;
}
+
return Status;
}
@@ -207,9 +214,9 @@ IoMmuAllocateBuffer ( **/
EFI_STATUS
IoMmuFreeBuffer (
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
)
{
EFI_STATUS Status;
@@ -221,6 +228,7 @@ IoMmuFreeBuffer ( } else {
Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -286,9 +294,10 @@ IoMmuAllocateAlignedBuffer ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
Memory = *HostAddress;
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
@@ -296,11 +305,13 @@ IoMmuAllocateAlignedBuffer ( Status = mIoMmu->FreeBuffer (
mIoMmu,
UnalignedPages,
- Memory);
+ Memory
+ );
if (EFI_ERROR (Status)) {
return Status;
}
}
+
Memory = (VOID *)(UINTN)(AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@@ -310,24 +321,27 @@ IoMmuAllocateAlignedBuffer ( Status = mIoMmu->FreeBuffer (
mIoMmu,
UnalignedPages,
- Memory);
+ Memory
+ );
if (EFI_ERROR (Status)) {
return Status;
}
}
- *HostAddress = (VOID *) AlignedMemory;
- NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);
- Status = mIoMmu->Map (
- mIoMmu,
- EdkiiIoMmuOperationBusMasterCommonBuffer,
- *HostAddress,
- &NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+
+ *HostAddress = (VOID *)AlignedMemory;
+ NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
+ Status = mIoMmu->Map (
+ mIoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ *HostAddress,
+ &NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
Status = mIoMmu->SetAttribute (
mIoMmu,
*Mapping,
@@ -345,10 +359,12 @@ IoMmuAllocateAlignedBuffer ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *)(((UINTN) HostPhyAddress + AlignmentMask) & ~AlignmentMask);
- *DeviceAddress = ((UINTN) HostPhyAddress + AlignmentMask) & ~AlignmentMask;
- *Mapping = NULL;
+
+ *HostAddress = (VOID *)(((UINTN)HostPhyAddress + AlignmentMask) & ~AlignmentMask);
+ *DeviceAddress = ((UINTN)HostPhyAddress + AlignmentMask) & ~AlignmentMask;
+ *Mapping = NULL;
}
+
return Status;
}
@@ -367,4 +383,3 @@ IoMmuInit ( (VOID **)&mIoMmu
);
}
-
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c index 01f4228537..c64b38fcfc 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c @@ -20,7 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN UINTN Pages
+ IN UINTN Pages
)
{
USBHC_MEM_BLOCK *Block;
@@ -32,16 +32,17 @@ UsbHcAllocMemBlock ( EFI_PHYSICAL_ADDRESS TempPtr;
PageNumber = EFI_SIZE_TO_PAGES (sizeof (USBHC_MEM_BLOCK));
- Status = PeiServicesAllocatePages (
- EfiBootServicesData,
- PageNumber,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesData,
+ PageNumber,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
return NULL;
}
- ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
+
+ ZeroMem ((VOID *)(UINTN)TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
//
// each bit in the bit array represents USBHC_MEM_UNIT
@@ -49,23 +50,24 @@ UsbHcAllocMemBlock ( //
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block = (USBHC_MEM_BLOCK *) (UINTN) TempPtr;
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block = (USBHC_MEM_BLOCK *)(UINTN)TempPtr;
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
PageNumber = EFI_SIZE_TO_PAGES (Block->BitsLen);
- Status = PeiServicesAllocatePages (
- EfiBootServicesData,
- PageNumber,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesData,
+ PageNumber,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
return NULL;
}
- ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
- Block->Bits = (UINT8 *) (UINTN) TempPtr;
+ ZeroMem ((VOID *)(UINTN)TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
+
+ Block->Bits = (UINT8 *)(UINTN)TempPtr;
Status = IoMmuAllocateBuffer (
Pages,
@@ -76,12 +78,13 @@ UsbHcAllocMemBlock ( if (EFI_ERROR (Status)) {
return NULL;
}
- ZeroMem ((VOID *) (UINTN) BufHost, EFI_PAGES_TO_SIZE (Pages));
- Block->BufHost = (UINT8 *) (UINTN) BufHost;
- Block->Buf = (UINT8 *) (UINTN) MappedAddr;
- Block->Mapping = Mapping;
- Block->Next = NULL;
+ ZeroMem ((VOID *)(UINTN)BufHost, EFI_PAGES_TO_SIZE (Pages));
+
+ Block->BufHost = (UINT8 *)(UINTN)BufHost;
+ Block->Buf = (UINT8 *)(UINTN)MappedAddr;
+ Block->Mapping = Mapping;
+ Block->Next = NULL;
return Block;
}
@@ -95,8 +98,8 @@ UsbHcAllocMemBlock ( **/
VOID
UsbHcFreeMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -120,22 +123,22 @@ UsbHcFreeMemBlock ( **/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -154,9 +157,9 @@ UsbHcAllocMemFromBlock ( } else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -167,13 +170,13 @@ UsbHcAllocMemFromBlock ( //
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | (UINT8)USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -192,9 +195,9 @@ UsbHcAllocMemFromBlock ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
@@ -215,7 +218,7 @@ UsbHcGetPciAddrForHostAddr ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -224,8 +227,8 @@ UsbHcGetPciAddrForHostAddr ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *) Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS) (UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -241,9 +244,9 @@ UsbHcGetPciAddrForHostAddr ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
USBHC_MEM_BLOCK *Head;
@@ -264,7 +267,7 @@ UsbHcGetHostAddrForPciAddr ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->Buf <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
+ if ((Block->Buf <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
break;
}
}
@@ -273,8 +276,8 @@ UsbHcGetHostAddrForPciAddr ( //
// calculate the host memory address for pci memory address.
//
- Offset = (UINT8 *) Mem - Block->Buf;
- HostAddr = (EFI_PHYSICAL_ADDRESS) (UINTN) (Block->BufHost + Offset);
+ Offset = (UINT8 *)Mem - Block->Buf;
+ HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->BufHost + Offset);
return HostAddr;
}
@@ -287,8 +290,8 @@ UsbHcGetHostAddrForPciAddr ( **/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -307,10 +310,10 @@ UsbHcInsertMemBlockToPool ( **/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -321,8 +324,6 @@ UsbHcIsMemBlockEmpty ( return TRUE;
}
-
-
/**
Initialize the memory management pool for the host controller.
@@ -340,17 +341,18 @@ UsbHcInitMemPool ( EFI_PHYSICAL_ADDRESS TempPtr;
PageNumber = EFI_SIZE_TO_PAGES (sizeof (USBHC_MEM_POOL));
- Status = PeiServicesAllocatePages (
- EfiBootServicesData,
- PageNumber,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesData,
+ PageNumber,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
return NULL;
}
- ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
- Pool = (USBHC_MEM_POOL *) ((UINTN) TempPtr);
+ ZeroMem ((VOID *)(UINTN)TempPtr, EFI_PAGES_TO_SIZE (PageNumber));
+
+ Pool = (USBHC_MEM_POOL *)((UINTN)TempPtr);
Pool->Head = UsbHcAllocMemBlock (USBHC_MEM_DEFAULT_PAGES);
if (Pool->Head == NULL) {
@@ -371,10 +373,10 @@ UsbHcInitMemPool ( **/
VOID
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -384,7 +386,7 @@ UsbHcFreeMemPool ( // first block.
//
for (Block = Pool->Head->Next; Block != NULL; Block = Pool->Head->Next) {
- //UsbHcUnlinkMemBlock (Pool->Head, Block);
+ // UsbHcUnlinkMemBlock (Pool->Head, Block);
UsbHcFreeMemBlock (Pool, Block);
}
@@ -403,16 +405,16 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -446,6 +448,7 @@ UsbHcAllocateMem ( } else {
Pages = USBHC_MEM_DEFAULT_PAGES;
}
+
NewBlock = UsbHcAllocMemBlock (Pages);
if (NewBlock == NULL) {
@@ -475,22 +478,22 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -501,8 +504,8 @@ UsbHcFreeMem ( //
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -510,7 +513,7 @@ UsbHcFreeMem ( for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -529,7 +532,7 @@ UsbHcFreeMem ( // Release the current memory block if it is empty and not the head
//
if ((Block != Head) && UsbHcIsMemBlockEmpty (Block)) {
- //UsbHcUnlinkMemBlock (Head, Block);
+ // UsbHcUnlinkMemBlock (Head, Block);
UsbHcFreeMemBlock (Pool, Block);
}
}
@@ -553,11 +556,11 @@ UsbHcFreeMem ( **/
EFI_STATUS
UsbHcAllocateAlignedPages (
- IN UINTN Pages,
- IN UINTN Alignment,
- OUT VOID **HostAddress,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ IN UINTN Pages,
+ IN UINTN Alignment,
+ OUT VOID **HostAddress,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
)
{
EFI_STATUS Status;
@@ -603,7 +606,7 @@ UsbHcAllocateAlignedPages ( }
}
- *HostAddress = Memory;
+ *HostAddress = Memory;
*DeviceAddress = DeviceMemory;
return EFI_SUCCESS;
@@ -619,13 +622,12 @@ UsbHcAllocateAlignedPages ( **/
VOID
UsbHcFreeAlignedPages (
- IN VOID *HostAddress,
- IN UINTN Pages,
- IN VOID *Mapping
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ IN VOID *Mapping
)
{
ASSERT (Pages != 0);
IoMmuFreeBuffer (Pages, HostAddress, Mapping);
}
-
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h index 5aa41397f3..2b4c8b19fc 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h @@ -12,29 +12,29 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Uefi.h>
-#define USBHC_MEM_DEFAULT_PAGES 16
+#define USBHC_MEM_DEFAULT_PAGES 16
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
-#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
-#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))
+#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
+#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -57,9 +57,9 @@ struct _USBHC_MEM_BLOCK { // data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
/**
@@ -74,9 +74,9 @@ typedef struct _USBHC_MEM_POOL { **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -91,9 +91,9 @@ UsbHcGetPciAddrForHostAddr ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -115,11 +115,11 @@ UsbHcGetHostAddrForPciAddr ( **/
EFI_STATUS
UsbHcAllocateAlignedPages (
- IN UINTN Pages,
- IN UINTN Alignment,
- OUT VOID **HostAddress,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ IN UINTN Pages,
+ IN UINTN Alignment,
+ OUT VOID **HostAddress,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
);
/**
@@ -132,9 +132,9 @@ UsbHcAllocateAlignedPages ( **/
VOID
UsbHcFreeAlignedPages (
- IN VOID *HostAddress,
- IN UINTN Pages,
- IN VOID *Mapping
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ IN VOID *Mapping
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c index 6bdf488413..301f376b04 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c @@ -15,48 +15,48 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
- {XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_PORTSC_PP, USB_PORT_STAT_POWER},
- {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_PORTSC_PP, USB_PORT_STAT_POWER },
+ { XHC_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
- {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
- {XHC_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_PORTSC_PRC, EfiUsbPortResetChange}
+USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
+ { XHC_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_PORTSC_PRC, EfiUsbPortResetChange }
};
USB_PORT_STATE_MAP mUsbHubPortStateMap[] = {
- {XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_HUB_PORTSC_PP, USB_PORT_STAT_POWER},
- {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_HUB_PORTSC_PP, USB_PORT_STAT_POWER },
+ { XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbHubPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},
- {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}
+USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
+ { XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange },
+ { XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange }
};
/**
@@ -70,11 +70,11 @@ USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = { **/
UINT32
XhcPeiReadOpReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (Xhc->CapLength != 0);
@@ -92,9 +92,9 @@ XhcPeiReadOpReg ( **/
VOID
XhcPeiWriteOpReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
ASSERT (Xhc->CapLength != 0);
@@ -112,12 +112,12 @@ XhcPeiWriteOpReg ( **/
VOID
XhcPeiSetOpRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcPeiReadOpReg (Xhc, Offset);
Data |= Bit;
@@ -134,12 +134,12 @@ XhcPeiSetOpRegBit ( **/
VOID
XhcPeiClearOpRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcPeiReadOpReg (Xhc, Offset);
Data &= ~Bit;
@@ -162,14 +162,14 @@ XhcPeiClearOpRegBit ( **/
EFI_STATUS
XhcPeiWaitOpRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- UINT64 Index;
+ UINT64 Index;
for (Index = 0; Index < Timeout * XHC_1_MILLISECOND; Index++) {
if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {
@@ -193,19 +193,17 @@ XhcPeiWaitOpRegBit ( **/
UINT32
XhcPeiReadCapRegister (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset);
return Data;
}
-
-
/**
Write the data to the XHCI door bell register.
@@ -216,9 +214,9 @@ XhcPeiReadCapRegister ( **/
VOID
XhcPeiWriteDoorBellReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
ASSERT (Xhc->DBOff != 0);
@@ -237,11 +235,11 @@ XhcPeiWriteDoorBellReg ( **/
UINT32
XhcPeiReadRuntimeReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (Xhc->RTSOff != 0);
@@ -260,9 +258,9 @@ XhcPeiReadRuntimeReg ( **/
VOID
XhcPeiWriteRuntimeReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
ASSERT (Xhc->RTSOff != 0);
@@ -280,12 +278,12 @@ XhcPeiWriteRuntimeReg ( **/
VOID
XhcPeiSetRuntimeRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcPeiReadRuntimeReg (Xhc, Offset);
Data |= Bit;
@@ -302,12 +300,12 @@ XhcPeiSetRuntimeRegBit ( **/
VOID
XhcPeiClearRuntimeRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcPeiReadRuntimeReg (Xhc, Offset);
Data &= ~Bit;
@@ -325,7 +323,7 @@ XhcPeiClearRuntimeRegBit ( **/
BOOLEAN
XhcPeiIsHalt (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
@@ -342,7 +340,7 @@ XhcPeiIsHalt ( **/
BOOLEAN
XhcPeiIsSysError (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
@@ -360,11 +358,11 @@ XhcPeiIsSysError ( **/
EFI_STATUS
XhcPeiResetHC (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Host can only be reset when it is halt. If not so, halt it
@@ -402,11 +400,11 @@ ON_EXIT: **/
EFI_STATUS
XhcPeiHaltHC (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcPeiClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
@@ -426,11 +424,11 @@ XhcPeiHaltHC ( **/
EFI_STATUS
XhcPeiRunHC (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
@@ -467,37 +465,37 @@ XhcPeiRunHC ( EFI_STATUS
EFIAPI
XhcPeiControlTransfer (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 DeviceAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN EFI_USB_DATA_DIRECTION TransferDirection,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN UINTN TimeOut,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
- OUT UINT32 *TransferResult
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN EFI_USB_DATA_DIRECTION TransferDirection,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN UINTN TimeOut,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ OUT UINT32 *TransferResult
)
{
- PEI_XHC_DEV *Xhc;
- URB *Urb;
- UINT8 Endpoint;
- UINT8 Index;
- UINT8 DescriptorType;
- UINT8 SlotId;
- UINT8 TTT;
- UINT8 MTT;
- UINT32 MaxPacket0;
- EFI_USB_HUB_DESCRIPTOR *HubDesc;
- EFI_STATUS Status;
- EFI_STATUS RecoveryStatus;
- UINTN MapSize;
- EFI_USB_PORT_STATUS PortStatus;
- UINT32 State;
- EFI_USB_DEVICE_REQUEST ClearPortRequest;
- UINTN Len;
+ PEI_XHC_DEV *Xhc;
+ URB *Urb;
+ UINT8 Endpoint;
+ UINT8 Index;
+ UINT8 DescriptorType;
+ UINT8 SlotId;
+ UINT8 TTT;
+ UINT8 MTT;
+ UINT32 MaxPacket0;
+ EFI_USB_HUB_DESCRIPTOR *HubDesc;
+ EFI_STATUS Status;
+ EFI_STATUS RecoveryStatus;
+ UINTN MapSize;
+ EFI_USB_PORT_STATUS PortStatus;
+ UINT32 State;
+ EFI_USB_DEVICE_REQUEST ClearPortRequest;
+ UINTN Len;
//
// Validate parameters
@@ -508,24 +506,28 @@ XhcPeiControlTransfer ( if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
- (TransferDirection != EfiUsbNoData)) {
+ (TransferDirection != EfiUsbNoData))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
- ((Data != NULL) || (*DataLength != 0))) {
+ ((Data != NULL) || (*DataLength != 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
- ((Data == NULL) || (*DataLength == 0))) {
+ ((Data == NULL) || (*DataLength == 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
(MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&
(MaximumPacketLength != 512)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
@@ -537,7 +539,7 @@ XhcPeiControlTransfer ( return EFI_INVALID_PARAMETER;
}
- Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
+ Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
@@ -561,7 +563,8 @@ XhcPeiControlTransfer ( // According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.
//
if ((Request->Request == USB_REQ_SET_ADDRESS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.
// This way is used to clean the history to avoid using wrong device address afterwards.
@@ -569,7 +572,8 @@ XhcPeiControlTransfer ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId == 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8) Request->Value)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value))
+ {
Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;
}
}
@@ -577,14 +581,15 @@ XhcPeiControlTransfer ( if (Xhc->UsbDevContext[SlotId].XhciDevAddr == 0) {
goto ON_EXIT;
}
+
//
// The actual device address has been assigned by XHCI during initializing the device slot.
// So we just need establish the mapping relationship between the device address requested from UsbBus
// and the actual device address assigned by XHCI. The following invocations through EFI_USB2_HC_PROTOCOL interface
// can find out the actual device address by it.
//
- Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8) Request->Value;
- Status = EFI_SUCCESS;
+ Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8)Request->Value;
+ Status = EFI_SUCCESS;
goto ON_EXIT;
}
@@ -595,20 +600,20 @@ XhcPeiControlTransfer ( // endpoint is bidirectional. XhcPeiCreateUrb expects this
// combination of Ep addr and its direction.
//
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
- Urb = XhcPeiCreateUrb (
- Xhc,
- DeviceAddress,
- Endpoint,
- DeviceSpeed,
- MaximumPacketLength,
- XHC_CTRL_TRANSFER,
- Request,
- Data,
- *DataLength,
- NULL,
- NULL
- );
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
+ Urb = XhcPeiCreateUrb (
+ Xhc,
+ DeviceAddress,
+ Endpoint,
+ DeviceSpeed,
+ MaximumPacketLength,
+ XHC_CTRL_TRANSFER,
+ Request,
+ Data,
+ *DataLength,
+ NULL,
+ NULL
+ );
if (Urb == NULL) {
DEBUG ((DEBUG_ERROR, "XhcPeiControlTransfer: failed to create URB"));
@@ -629,20 +634,22 @@ XhcPeiControlTransfer ( //
// The transfer timed out. Abort the transfer by dequeueing of the TD.
//
- RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);
- if (EFI_ERROR(RecoveryStatus)) {
- DEBUG((DEBUG_ERROR, "XhcPeiControlTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
+ RecoveryStatus = XhcPeiDequeueTrbFromEndpoint (Xhc, Urb);
+ if (EFI_ERROR (RecoveryStatus)) {
+ DEBUG ((DEBUG_ERROR, "XhcPeiControlTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
}
+
XhcPeiFreeUrb (Xhc, Urb);
goto ON_EXIT;
} else {
if (*TransferResult == EFI_USB_NOERROR) {
Status = EFI_SUCCESS;
} else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {
- RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);
+ RecoveryStatus = XhcPeiRecoverHaltedEndpoint (Xhc, Urb);
if (EFI_ERROR (RecoveryStatus)) {
DEBUG ((DEBUG_ERROR, "XhcPeiControlTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
}
+
Status = EFI_DEVICE_ERROR;
XhcPeiFreeUrb (Xhc, Urb);
goto ON_EXIT;
@@ -651,6 +658,7 @@ XhcPeiControlTransfer ( goto ON_EXIT;
}
}
+
//
// Unmap data before consume.
//
@@ -663,8 +671,9 @@ XhcPeiControlTransfer ( //
if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||
- ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {
- DescriptorType = (UINT8) (Request->Value >> 8);
+ ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE)))))
+ {
+ DescriptorType = (UINT8)(Request->Value >> 8);
if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {
ASSERT (Data != NULL);
//
@@ -679,11 +688,13 @@ XhcPeiControlTransfer ( } else {
MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
}
+
Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
if (Xhc->UsbDevContext[SlotId].ConfDesc == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
+
if (Xhc->HcCParams.Data.Csz == 0) {
Status = XhcPeiEvaluateContext (Xhc, SlotId, MaxPacket0);
} else {
@@ -691,28 +702,30 @@ XhcPeiControlTransfer ( }
} else if (DescriptorType == USB_DESC_TYPE_CONFIG) {
ASSERT (Data != NULL);
- if (*DataLength == ((UINT16 *) Data)[1]) {
+ if (*DataLength == ((UINT16 *)Data)[1]) {
//
// Get configuration value from request, store the configuration descriptor for Configure_Endpoint cmd.
//
- Index = (UINT8) Request->Value;
+ Index = (UINT8)Request->Value;
ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);
Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);
if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
+
CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);
}
} else if (((DescriptorType == USB_DESC_TYPE_HUB) ||
- (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {
+ (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2))
+ {
ASSERT (Data != NULL);
- HubDesc = (EFI_USB_HUB_DESCRIPTOR *) Data;
+ HubDesc = (EFI_USB_HUB_DESCRIPTOR *)Data;
ASSERT (HubDesc->NumPorts <= 15);
//
// The bit 5,6 of HubCharacter field of Hub Descriptor is TTT.
//
- TTT = (UINT8) ((HubDesc->HubCharacter & (BIT5 | BIT6)) >> 5);
+ TTT = (UINT8)((HubDesc->HubCharacter & (BIT5 | BIT6)) >> 5);
if (Xhc->UsbDevContext[SlotId].DevDesc.DeviceProtocol == 2) {
//
// Don't support multi-TT feature for super speed hub now.
@@ -730,7 +743,8 @@ XhcPeiControlTransfer ( }
}
} else if ((Request->Request == USB_REQ_SET_CONFIG) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Hook Set_Config request from UsbBus as we need configure device endpoint.
//
@@ -741,16 +755,18 @@ XhcPeiControlTransfer ( } else {
Status = XhcPeiSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
}
+
break;
}
}
} else if ((Request->Request == USB_REQ_GET_STATUS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER)))
+ {
ASSERT (Data != NULL);
//
// Hook Get_Status request from UsbBus to keep track of the port status change.
//
- State = *(UINT32 *) Data;
+ State = *(UINT32 *)Data;
PortStatus.PortStatus = 0;
PortStatus.PortChangeStatus = 0;
@@ -778,14 +794,14 @@ XhcPeiControlTransfer ( MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {
- PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
+ PortStatus.PortStatus = (UINT16)(PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
}
}
MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {
- PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
+ PortStatus.PortChangeStatus = (UINT16)(PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
}
}
@@ -794,11 +810,11 @@ XhcPeiControlTransfer ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {
ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));
- ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
- ClearPortRequest.Request = (UINT8) USB_REQ_CLEAR_FEATURE;
- ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
- ClearPortRequest.Index = Request->Index;
- ClearPortRequest.Length = 0;
+ ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
+ ClearPortRequest.Request = (UINT8)USB_REQ_CLEAR_FEATURE;
+ ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
+ ClearPortRequest.Index = Request->Index;
+ ClearPortRequest.Length = 0;
XhcPeiControlTransfer (
PeiServices,
@@ -819,7 +835,7 @@ XhcPeiControlTransfer ( XhcPeiPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);
- *(UINT32 *) Data = *(UINT32 *) &PortStatus;
+ *(UINT32 *)Data = *(UINT32 *)&PortStatus;
}
ON_EXIT:
@@ -866,31 +882,32 @@ ON_EXIT: EFI_STATUS
EFIAPI
XhcPeiBulkTransfer (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
- IN OUT UINTN *DataLength,
- IN OUT UINT8 *DataToggle,
- IN UINTN TimeOut,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
- OUT UINT32 *TransferResult
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
+ IN OUT UINTN *DataLength,
+ IN OUT UINT8 *DataToggle,
+ IN UINTN TimeOut,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
+ OUT UINT32 *TransferResult
)
{
- PEI_XHC_DEV *Xhc;
- URB *Urb;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_STATUS RecoveryStatus;
+ PEI_XHC_DEV *Xhc;
+ URB *Urb;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_STATUS RecoveryStatus;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -901,11 +918,12 @@ XhcPeiBulkTransfer ( if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 512)) ||
- ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength > 1024))) {
+ ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength > 1024)))
+ {
return EFI_INVALID_PARAMETER;
}
- Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
+ Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -956,18 +974,19 @@ XhcPeiBulkTransfer ( //
// The transfer timed out. Abort the transfer by dequeueing of the TD.
//
- RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);
- if (EFI_ERROR(RecoveryStatus)) {
- DEBUG((DEBUG_ERROR, "XhcPeiBulkTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
+ RecoveryStatus = XhcPeiDequeueTrbFromEndpoint (Xhc, Urb);
+ if (EFI_ERROR (RecoveryStatus)) {
+ DEBUG ((DEBUG_ERROR, "XhcPeiBulkTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));
}
} else {
if (*TransferResult == EFI_USB_NOERROR) {
Status = EFI_SUCCESS;
} else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {
- RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);
+ RecoveryStatus = XhcPeiRecoverHaltedEndpoint (Xhc, Urb);
if (EFI_ERROR (RecoveryStatus)) {
DEBUG ((DEBUG_ERROR, "XhcPeiBulkTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
}
+
Status = EFI_DEVICE_ERROR;
}
}
@@ -998,12 +1017,13 @@ ON_EXIT: EFI_STATUS
EFIAPI
XhcPeiGetRootHubPortNumber (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- OUT UINT8 *PortNumber
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ OUT UINT8 *PortNumber
)
{
- PEI_XHC_DEV *XhcDev;
+ PEI_XHC_DEV *XhcDev;
+
XhcDev = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
if (PortNumber == NULL) {
@@ -1033,18 +1053,18 @@ XhcPeiGetRootHubPortNumber ( EFI_STATUS
EFIAPI
XhcPeiClearRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- PEI_XHC_DEV *Xhc;
- UINT32 Offset;
- UINT32 State;
- EFI_STATUS Status;
+ PEI_XHC_DEV *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ EFI_STATUS Status;
- Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
+ Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
Status = EFI_SUCCESS;
if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {
@@ -1052,15 +1072,15 @@ XhcPeiClearRootHubPortFeature ( goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
- State = XhcPeiReadOpReg (Xhc, Offset);
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ State = XhcPeiReadOpReg (Xhc, Offset);
DEBUG ((DEBUG_INFO, "XhcPeiClearRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
//
// Mask off the port status change bits, these bits are
// write clean bits
//
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
case EfiUsbPortEnable:
@@ -1096,6 +1116,7 @@ XhcPeiClearRootHubPortFeature ( State &= ~XHC_PORTSC_PP;
XhcPeiWriteOpReg (Xhc, Offset, State);
}
+
break;
case EfiUsbPortOwner:
@@ -1168,18 +1189,18 @@ ON_EXIT: EFI_STATUS
EFIAPI
XhcPeiSetRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- PEI_XHC_DEV *Xhc;
- UINT32 Offset;
- UINT32 State;
- EFI_STATUS Status;
+ PEI_XHC_DEV *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ EFI_STATUS Status;
- Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
+ Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
Status = EFI_SUCCESS;
if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {
@@ -1187,15 +1208,15 @@ XhcPeiSetRootHubPortFeature ( goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
- State = XhcPeiReadOpReg (Xhc, Offset);
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ State = XhcPeiReadOpReg (Xhc, Offset);
DEBUG ((DEBUG_INFO, "XhcPeiSetRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
//
// Mask off the port status change bits, these bits are
// write clean bits
//
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
case EfiUsbPortEnable:
@@ -1209,7 +1230,7 @@ XhcPeiSetRootHubPortFeature ( State |= XHC_PORTSC_LWS;
XhcPeiWriteOpReg (Xhc, Offset, State);
State &= ~XHC_PORTSC_PLS;
- State |= (3 << 5) ;
+ State |= (3 << 5);
XhcPeiWriteOpReg (Xhc, Offset, State);
break;
@@ -1232,7 +1253,7 @@ XhcPeiSetRootHubPortFeature ( //
State |= XHC_PORTSC_RESET;
XhcPeiWriteOpReg (Xhc, Offset, State);
- XhcPeiWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
+ XhcPeiWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
break;
case EfiUsbPortPower:
@@ -1243,6 +1264,7 @@ XhcPeiSetRootHubPortFeature ( State |= XHC_PORTSC_PP;
XhcPeiWriteOpReg (Xhc, Offset, State);
}
+
break;
case EfiUsbPortOwner:
@@ -1276,18 +1298,18 @@ ON_EXIT: EFI_STATUS
EFIAPI
XhcPeiGetRootHubPortStatus (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- OUT EFI_USB_PORT_STATUS *PortStatus
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- PEI_XHC_DEV *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINTN Index;
- UINTN MapSize;
- USB_DEV_ROUTE ParentRouteChart;
+ PEI_XHC_DEV *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINTN Index;
+ UINTN MapSize;
+ USB_DEV_ROUTE ParentRouteChart;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
@@ -1302,11 +1324,11 @@ XhcPeiGetRootHubPortStatus ( //
// Clear port status.
//
- PortStatus->PortStatus = 0;
- PortStatus->PortChangeStatus = 0;
+ PortStatus->PortStatus = 0;
+ PortStatus->PortChangeStatus = 0;
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
- State = XhcPeiReadOpReg (Xhc, Offset);
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ State = XhcPeiReadOpReg (Xhc, Offset);
DEBUG ((DEBUG_INFO, "XhcPeiGetRootHubPortStatus: Port: %x State: %x\n", PortNumber, State));
//
@@ -1338,9 +1360,10 @@ XhcPeiGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
+
//
// Bit5~8 reflects its current link state.
//
@@ -1352,7 +1375,7 @@ XhcPeiGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -1394,9 +1417,9 @@ XhcEndOfPei ( IN VOID *Ppi
)
{
- PEI_XHC_DEV *Xhc;
+ PEI_XHC_DEV *Xhc;
- Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(NotifyDescriptor);
+ Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY (NotifyDescriptor);
XhcPeiHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
@@ -1415,19 +1438,19 @@ XhcEndOfPei ( EFI_STATUS
EFIAPI
XhcPeimEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- PEI_USB_CONTROLLER_PPI *UsbControllerPpi;
- EFI_STATUS Status;
- UINT8 Index;
- UINTN ControllerType;
- UINTN BaseAddress;
- UINTN MemPages;
- PEI_XHC_DEV *XhcDev;
- EFI_PHYSICAL_ADDRESS TempPtr;
- UINT32 PageSize;
+ PEI_USB_CONTROLLER_PPI *UsbControllerPpi;
+ EFI_STATUS Status;
+ UINT8 Index;
+ UINTN ControllerType;
+ UINTN BaseAddress;
+ UINTN MemPages;
+ PEI_XHC_DEV *XhcDev;
+ EFI_PHYSICAL_ADDRESS TempPtr;
+ UINT32 PageSize;
//
// Shadow this PEIM to run from memory.
@@ -1440,7 +1463,7 @@ XhcPeimEntry ( &gPeiUsbControllerPpiGuid,
0,
NULL,
- (VOID **) &UsbControllerPpi
+ (VOID **)&UsbControllerPpi
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
@@ -1451,7 +1474,7 @@ XhcPeimEntry ( Index = 0;
while (TRUE) {
Status = UsbControllerPpi->GetUsbController (
- (EFI_PEI_SERVICES **) PeiServices,
+ (EFI_PEI_SERVICES **)PeiServices,
UsbControllerPpi,
Index,
&ControllerType,
@@ -1473,25 +1496,26 @@ XhcPeimEntry ( }
MemPages = EFI_SIZE_TO_PAGES (sizeof (PEI_XHC_DEV));
- Status = PeiServicesAllocatePages (
- EfiBootServicesData,
- MemPages,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesData,
+ MemPages,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (MemPages));
- XhcDev = (PEI_XHC_DEV *) ((UINTN) TempPtr);
-
- XhcDev->Signature = USB_XHC_DEV_SIGNATURE;
- XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;
- XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0FF);
- XhcDev->HcSParams1.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS1_OFFSET);
- XhcDev->HcSParams2.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS2_OFFSET);
- XhcDev->HcCParams.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCCPARAMS_OFFSET);
- XhcDev->DBOff = XhcPeiReadCapRegister (XhcDev, XHC_DBOFF_OFFSET);
- XhcDev->RTSOff = XhcPeiReadCapRegister (XhcDev, XHC_RTSOFF_OFFSET);
+
+ ZeroMem ((VOID *)(UINTN)TempPtr, EFI_PAGES_TO_SIZE (MemPages));
+ XhcDev = (PEI_XHC_DEV *)((UINTN)TempPtr);
+
+ XhcDev->Signature = USB_XHC_DEV_SIGNATURE;
+ XhcDev->UsbHostControllerBaseAddress = (UINT32)BaseAddress;
+ XhcDev->CapLength = (UINT8)(XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0FF);
+ XhcDev->HcSParams1.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS1_OFFSET);
+ XhcDev->HcSParams2.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS2_OFFSET);
+ XhcDev->HcCParams.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCCPARAMS_OFFSET);
+ XhcDev->DBOff = XhcPeiReadCapRegister (XhcDev, XHC_DBOFF_OFFSET);
+ XhcDev->RTSOff = XhcPeiReadCapRegister (XhcDev, XHC_RTSOFF_OFFSET);
//
// This PageSize field defines the page size supported by the xHC implementation.
@@ -1528,19 +1552,19 @@ XhcPeimEntry ( //
MicroSecondDelay (XHC_ROOT_PORT_STATE_STABLE);
- XhcDev->Usb2HostControllerPpi.ControlTransfer = XhcPeiControlTransfer;
- XhcDev->Usb2HostControllerPpi.BulkTransfer = XhcPeiBulkTransfer;
- XhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = XhcPeiGetRootHubPortNumber;
- XhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = XhcPeiGetRootHubPortStatus;
- XhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = XhcPeiSetRootHubPortFeature;
- XhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = XhcPeiClearRootHubPortFeature;
+ XhcDev->Usb2HostControllerPpi.ControlTransfer = XhcPeiControlTransfer;
+ XhcDev->Usb2HostControllerPpi.BulkTransfer = XhcPeiBulkTransfer;
+ XhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = XhcPeiGetRootHubPortNumber;
+ XhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = XhcPeiGetRootHubPortStatus;
+ XhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = XhcPeiSetRootHubPortFeature;
+ XhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = XhcPeiClearRootHubPortFeature;
XhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- XhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
- XhcDev->PpiDescriptor.Ppi = &XhcDev->Usb2HostControllerPpi;
+ XhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
+ XhcDev->PpiDescriptor.Ppi = &XhcDev->Usb2HostControllerPpi;
- XhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- XhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
+ XhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+ XhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
XhcDev->EndOfPeiNotifyList.Notify = XhcEndOfPei;
PeiServicesInstallPpi (&XhcDev->PpiDescriptor);
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h index 03a55f3eb6..0800b15c72 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h @@ -25,33 +25,33 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
-typedef struct _PEI_XHC_DEV PEI_XHC_DEV;
-typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
+typedef struct _PEI_XHC_DEV PEI_XHC_DEV;
+typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "UsbHcMem.h"
#include "XhciReg.h"
#include "XhciSched.h"
-#define CMD_RING_TRB_NUMBER 0x100
-#define TR_RING_TRB_NUMBER 0x100
-#define ERST_NUMBER 0x01
-#define EVENT_RING_TRB_NUMBER 0x200
+#define CMD_RING_TRB_NUMBER 0x100
+#define TR_RING_TRB_NUMBER 0x100
+#define ERST_NUMBER 0x01
+#define EVENT_RING_TRB_NUMBER 0x200
-#define XHC_1_MICROSECOND 1
-#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)
-#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
+#define XHC_1_MICROSECOND 1
+#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)
+#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
//
// XHC reset timeout experience values.
// The unit is millisecond, setting it as 1s.
//
-#define XHC_RESET_TIMEOUT (1000)
+#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
-#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
+#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// Wait for root port state stable.
@@ -62,11 +62,11 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT; // XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
-#define XHC_GENERIC_TIMEOUT (10 * 1000)
+#define XHC_GENERIC_TIMEOUT (10 * 1000)
-#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
-#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
+#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
+#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \
(XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))
@@ -86,23 +86,23 @@ struct _USB_DEV_CONTEXT { //
// Whether this entry in UsbDevContext array is used or not.
//
- BOOLEAN Enabled;
+ BOOLEAN Enabled;
//
// The slot id assigned to the new device through XHCI's Enable_Slot cmd.
//
- UINT8 SlotId;
+ UINT8 SlotId;
//
// The route string presented an attached usb device.
//
- USB_DEV_ROUTE RouteString;
+ USB_DEV_ROUTE RouteString;
//
// The route string of parent device if it exists. Otherwise it's zero.
//
- USB_DEV_ROUTE ParentRouteString;
+ USB_DEV_ROUTE ParentRouteString;
//
// The actual device address assigned by XHCI through Address_Device command.
//
- UINT8 XhciDevAddr;
+ UINT8 XhciDevAddr;
//
// The requested device address from UsbBus driver through Set_Address standard usb request.
// As XHCI spec replaces this request with Address_Device command, we have to record the
@@ -111,23 +111,23 @@ struct _USB_DEV_CONTEXT { // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
// device address and access the actual device.
//
- UINT8 BusDevAddr;
+ UINT8 BusDevAddr;
//
// The pointer to the input device context.
//
- VOID *InputContext;
+ VOID *InputContext;
//
// The pointer to the output device context.
//
- VOID *OutputContext;
+ VOID *OutputContext;
//
// The transfer queue for every endpoint.
//
- VOID *EndpointTransferRing[31];
+ VOID *EndpointTransferRing[31];
//
// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
//
- EFI_USB_DEVICE_DESCRIPTOR DevDesc;
+ EFI_USB_DEVICE_DESCRIPTOR DevDesc;
//
// As a usb device may include multiple configuration descriptors, we dynamically allocate an array
// to store them.
@@ -135,59 +135,59 @@ struct _USB_DEV_CONTEXT { // such as Interface descriptor, Endpoint descriptor, and so on.
// These information is used to support XHCI's Config_Endpoint cmd.
//
- EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
+ EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
};
-#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')
+#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')
struct _PEI_XHC_DEV {
- UINTN Signature;
- PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
- UINT32 UsbHostControllerBaseAddress;
- USBHC_MEM_POOL *MemPool;
+ UINTN Signature;
+ PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ UINT32 UsbHostControllerBaseAddress;
+ USBHC_MEM_POOL *MemPool;
//
// EndOfPei callback is used to stop the XHC DMA operation
// after exit PEI phase.
//
- EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
//
// XHCI configuration data
//
- UINT8 CapLength; ///< Capability Register Length
- XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
- XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
- XHC_HCCPARAMS HcCParams; ///< Capability Parameters
- UINT32 DBOff; ///< Doorbell Offset
- UINT32 RTSOff; ///< Runtime Register Space Offset
- UINT32 PageSize;
- UINT32 MaxScratchpadBufs;
- UINT64 *ScratchBuf;
- VOID *ScratchMap;
- UINT64 *ScratchEntry;
- UINTN *ScratchEntryMap;
- UINT64 *DCBAA;
- UINT32 MaxSlotsEn;
+ UINT8 CapLength; ///< Capability Register Length
+ XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
+ XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
+ XHC_HCCPARAMS HcCParams; ///< Capability Parameters
+ UINT32 DBOff; ///< Doorbell Offset
+ UINT32 RTSOff; ///< Runtime Register Space Offset
+ UINT32 PageSize;
+ UINT32 MaxScratchpadBufs;
+ UINT64 *ScratchBuf;
+ VOID *ScratchMap;
+ UINT64 *ScratchEntry;
+ UINTN *ScratchEntryMap;
+ UINT64 *DCBAA;
+ UINT32 MaxSlotsEn;
//
// Cmd Transfer Ring
//
- TRANSFER_RING CmdRing;
+ TRANSFER_RING CmdRing;
//
// EventRing
//
- EVENT_RING EventRing;
+ EVENT_RING EventRing;
//
// Store device contexts managed by XHCI device
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
- USB_DEV_CONTEXT UsbDevContext[256];
+ USB_DEV_CONTEXT UsbDevContext[256];
};
-#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
-#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)
/**
Initialize the memory management pool for the host controller.
@@ -209,7 +209,7 @@ UsbHcInitMemPool ( **/
VOID
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
;
@@ -225,8 +225,8 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
;
@@ -240,13 +240,12 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
;
-
/**
Initialize IOMMU.
**/
@@ -276,11 +275,11 @@ IoMmuInit ( **/
EFI_STATUS
IoMmuMap (
- IN EDKII_IOMMU_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ IN EDKII_IOMMU_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
);
/**
@@ -294,7 +293,7 @@ IoMmuMap ( **/
EFI_STATUS
IoMmuUnmap (
- IN VOID *Mapping
+ IN VOID *Mapping
);
/**
@@ -337,9 +336,9 @@ IoMmuAllocateBuffer ( **/
EFI_STATUS
IoMmuFreeBuffer (
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
);
/**
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h index e98b451a96..bfbb608526 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h @@ -13,153 +13,152 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Capability registers offset
//
-#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
-#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
-#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
-#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
-#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
-#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
-#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
-#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
+#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
+#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
+#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
+#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
+#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
+#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
+#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
+#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
//
// Operational registers offset
//
-#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
-#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
-#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
-#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
-#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
-#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
-#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
-#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
+#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
+#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
+#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
+#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
+#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
+#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
+#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
+#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
//
// Runtime registers offset
//
-#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
-#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
-#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
-#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
-#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
-#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
+#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
+#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
+#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
+#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
+#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
+#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
//
// Register Bit Definition
//
-#define XHC_USBCMD_RUN BIT0 // Run/Stop
-#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
-#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
-#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
-
-#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
-#define XHC_USBSTS_HSE BIT2 // Host System Error
-#define XHC_USBSTS_EINT BIT3 // Event Interrupt
-#define XHC_USBSTS_PCD BIT4 // Port Change Detect
-#define XHC_USBSTS_SSS BIT8 // Save State Status
-#define XHC_USBSTS_RSS BIT9 // Restore State Status
-#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
-#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
-#define XHC_USBSTS_HCE BIT12 // Host Controller Error
-
-#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
-
-#define XHC_CRCR_RCS BIT0 // Ring Cycle State
-#define XHC_CRCR_CS BIT1 // Command Stop
-#define XHC_CRCR_CA BIT2 // Command Abort
-#define XHC_CRCR_CRR BIT3 // Command Ring Running
-
-#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled
-
-#define XHC_PORTSC_CCS BIT0 // Current Connect Status
-#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
-#define XHC_PORTSC_OCA BIT3 // Over-current Active
-#define XHC_PORTSC_RESET BIT4 // Port Reset
-#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
-#define XHC_PORTSC_PP BIT9 // Port Power
-#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
-#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
-#define XHC_PORTSC_CSC BIT17 // Connect Status Change
-#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
-#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
-#define XHC_PORTSC_OCC BIT20 // Over-Current Change
-#define XHC_PORTSC_PRC BIT21 // Port Reset Change
-#define XHC_PORTSC_PLC BIT22 // Port Link State Change
-#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
-#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
-
-#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
-#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
-#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
-#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
-#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
-#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
-#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
-#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
-#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
-#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
-
-#define XHC_IMAN_IP BIT0 // Interrupt Pending
-#define XHC_IMAN_IE BIT1 // Interrupt Enable
-
-#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
-#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
-
+#define XHC_USBCMD_RUN BIT0 // Run/Stop
+#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
+#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
+#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
+
+#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
+#define XHC_USBSTS_HSE BIT2 // Host System Error
+#define XHC_USBSTS_EINT BIT3 // Event Interrupt
+#define XHC_USBSTS_PCD BIT4 // Port Change Detect
+#define XHC_USBSTS_SSS BIT8 // Save State Status
+#define XHC_USBSTS_RSS BIT9 // Restore State Status
+#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
+#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
+#define XHC_USBSTS_HCE BIT12 // Host Controller Error
+
+#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
+
+#define XHC_CRCR_RCS BIT0 // Ring Cycle State
+#define XHC_CRCR_CS BIT1 // Command Stop
+#define XHC_CRCR_CA BIT2 // Command Abort
+#define XHC_CRCR_CRR BIT3 // Command Ring Running
+
+#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled
+
+#define XHC_PORTSC_CCS BIT0 // Current Connect Status
+#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
+#define XHC_PORTSC_OCA BIT3 // Over-current Active
+#define XHC_PORTSC_RESET BIT4 // Port Reset
+#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
+#define XHC_PORTSC_PP BIT9 // Port Power
+#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
+#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
+#define XHC_PORTSC_CSC BIT17 // Connect Status Change
+#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
+#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
+#define XHC_PORTSC_OCC BIT20 // Over-Current Change
+#define XHC_PORTSC_PRC BIT21 // Port Reset Change
+#define XHC_PORTSC_PLC BIT22 // Port Link State Change
+#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
+#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
+
+#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
+#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
+#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
+#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
+#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
+#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
+#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
+#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
+#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
+#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
+
+#define XHC_IMAN_IP BIT0 // Interrupt Pending
+#define XHC_IMAN_IE BIT1 // Interrupt Enable
+
+#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
+#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
#pragma pack (1)
typedef struct {
- UINT8 MaxSlots; // Number of Device Slots
- UINT16 MaxIntrs:11; // Number of Interrupters
- UINT16 Rsvd:5;
- UINT8 MaxPorts; // Number of Ports
+ UINT8 MaxSlots; // Number of Device Slots
+ UINT16 MaxIntrs : 11; // Number of Interrupters
+ UINT16 Rsvd : 5;
+ UINT8 MaxPorts; // Number of Ports
} HCSPARAMS1;
//
// Structural Parameters 1 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS1 Data;
+ UINT32 Dword;
+ HCSPARAMS1 Data;
} XHC_HCSPARAMS1;
typedef struct {
- UINT32 Ist:4; // Isochronous Scheduling Threshold
- UINT32 Erst:4; // Event Ring Segment Table Max
- UINT32 Rsvd:13;
- UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
- UINT32 Spr:1; // Scratchpad Restore
- UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
+ UINT32 Ist : 4; // Isochronous Scheduling Threshold
+ UINT32 Erst : 4; // Event Ring Segment Table Max
+ UINT32 Rsvd : 13;
+ UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi
+ UINT32 Spr : 1; // Scratchpad Restore
+ UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo
} HCSPARAMS2;
//
// Structural Parameters 2 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS2 Data;
+ UINT32 Dword;
+ HCSPARAMS2 Data;
} XHC_HCSPARAMS2;
typedef struct {
- UINT16 Ac64:1; // 64-bit Addressing Capability
- UINT16 Bnc:1; // BW Negotiation Capability
- UINT16 Csz:1; // Context Size
- UINT16 Ppc:1; // Port Power Control
- UINT16 Pind:1; // Port Indicators
- UINT16 Lhrc:1; // Light HC Reset Capability
- UINT16 Ltc:1; // Latency Tolerance Messaging Capability
- UINT16 Nss:1; // No Secondary SID Support
- UINT16 Pae:1; // Parse All Event Data
- UINT16 Rsvd:3;
- UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
- UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
+ UINT16 Ac64 : 1; // 64-bit Addressing Capability
+ UINT16 Bnc : 1; // BW Negotiation Capability
+ UINT16 Csz : 1; // Context Size
+ UINT16 Ppc : 1; // Port Power Control
+ UINT16 Pind : 1; // Port Indicators
+ UINT16 Lhrc : 1; // Light HC Reset Capability
+ UINT16 Ltc : 1; // Latency Tolerance Messaging Capability
+ UINT16 Nss : 1; // No Secondary SID Support
+ UINT16 Pae : 1; // Parse All Event Data
+ UINT16 Rsvd : 3;
+ UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size
+ UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
} HCCPARAMS;
//
// Capability Parameters Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCCPARAMS Data;
+ UINT32 Dword;
+ HCCPARAMS Data;
} XHC_HCCPARAMS;
#pragma pack ()
@@ -169,19 +168,19 @@ typedef union { //
#pragma pack(1)
typedef struct {
- UINT8 Pi;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 Pi;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
typedef struct {
- UINT8 Length;
- UINT8 DescType;
- UINT8 NumPorts;
- UINT16 HubCharacter;
- UINT8 PwrOn2PwrGood;
- UINT8 HubContrCurrent;
- UINT8 Filler[16];
+ UINT8 Length;
+ UINT8 DescType;
+ UINT8 NumPorts;
+ UINT16 HubCharacter;
+ UINT8 PwrOn2PwrGood;
+ UINT8 HubContrCurrent;
+ UINT8 Filler[16];
} EFI_USB_HUB_DESCRIPTOR;
#pragma pack()
@@ -191,8 +190,8 @@ typedef struct { // For more details, Please refer to USB 3.0 Spec Table 10-7.
//
typedef enum {
- Usb3PortBHPortReset = 28,
- Usb3PortBHPortResetChange = 29
+ Usb3PortBHPortReset = 28,
+ Usb3PortBHPortResetChange = 29
} XHC_PORT_FEATURE;
//
@@ -200,16 +199,16 @@ typedef enum { // UEFI's port states.
//
typedef struct {
- UINT32 HwState;
- UINT16 UefiState;
+ UINT32 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
// Structure to map the hardware port states to feature selector for clear port feature request.
//
typedef struct {
- UINT32 HwState;
- UINT16 Selector;
+ UINT32 HwState;
+ UINT16 Selector;
} USB_CLEAR_PORT_MAP;
/**
@@ -223,8 +222,8 @@ typedef struct { **/
UINT32
XhcPeiReadOpReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset
);
/**
@@ -237,9 +236,9 @@ XhcPeiReadOpReg ( **/
VOID
XhcPeiWriteOpReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -252,9 +251,9 @@ XhcPeiWriteOpReg ( **/
VOID
XhcPeiSetOpRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -267,9 +266,9 @@ XhcPeiSetOpRegBit ( **/
VOID
XhcPeiClearOpRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -288,14 +287,13 @@ XhcPeiClearOpRegBit ( **/
EFI_STATUS
XhcPeiWaitOpRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
);
-
/**
Write the data to the XHCI door bell register.
@@ -306,9 +304,9 @@ XhcPeiWaitOpRegBit ( **/
VOID
XhcPeiWriteDoorBellReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -322,8 +320,8 @@ XhcPeiWriteDoorBellReg ( **/
UINT32
XhcPeiReadRuntimeReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset
);
/**
@@ -336,9 +334,9 @@ XhcPeiReadRuntimeReg ( **/
VOID
XhcPeiWriteRuntimeReg (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -351,9 +349,9 @@ XhcPeiWriteRuntimeReg ( **/
VOID
XhcPeiSetRuntimeRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -366,9 +364,9 @@ XhcPeiSetRuntimeRegBit ( **/
VOID
XhcPeiClearRuntimeRegBit (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -382,7 +380,7 @@ XhcPeiClearRuntimeRegBit ( **/
BOOLEAN
XhcPeiIsHalt (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
);
/**
@@ -396,7 +394,7 @@ XhcPeiIsHalt ( **/
BOOLEAN
XhcPeiIsSysError (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
);
/**
@@ -411,8 +409,8 @@ XhcPeiIsSysError ( **/
EFI_STATUS
XhcPeiResetHC (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -427,8 +425,8 @@ XhcPeiResetHC ( **/
EFI_STATUS
XhcPeiHaltHC (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -443,8 +441,8 @@ XhcPeiHaltHC ( **/
EFI_STATUS
XhcPeiRunHC (
- IN PEI_XHC_DEV *Xhc,
- IN UINT32 Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT32 Timeout
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c index 1fc06aaa61..cc597a4371 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -19,25 +19,25 @@ SPDX-License-Identifier: BSD-2-Clause-Patent @return Created URB or NULL.
**/
-URB*
+URB *
XhcPeiCreateCmdTrb (
- IN PEI_XHC_DEV *Xhc,
- IN TRB_TEMPLATE *CmdTrb
+ IN PEI_XHC_DEV *Xhc,
+ IN TRB_TEMPLATE *CmdTrb
)
{
- URB *Urb;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
return NULL;
}
- Urb->Signature = XHC_URB_SIG;
+ Urb->Signature = XHC_URB_SIG;
- Urb->Ring = &Xhc->CmdRing;
+ Urb->Ring = &Xhc->CmdRing;
XhcPeiSyncTrsRing (Xhc, Urb->Ring);
- Urb->TrbNum = 1;
- Urb->TrbStart = Urb->Ring->RingEnqueue;
+ Urb->TrbNum = 1;
+ Urb->TrbStart = Urb->Ring->RingEnqueue;
CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
Urb->TrbEnd = Urb->TrbStart;
@@ -62,14 +62,14 @@ XhcPeiCreateCmdTrb ( **/
EFI_STATUS
XhcPeiCmdTransfer (
- IN PEI_XHC_DEV *Xhc,
- IN TRB_TEMPLATE *CmdTrb,
- IN UINTN Timeout,
- OUT TRB_TEMPLATE **EvtTrb
+ IN PEI_XHC_DEV *Xhc,
+ IN TRB_TEMPLATE *CmdTrb,
+ IN UINTN Timeout,
+ OUT TRB_TEMPLATE **EvtTrb
)
{
- EFI_STATUS Status;
- URB *Urb;
+ EFI_STATUS Status;
+ URB *Urb;
//
// Validate the parameters
@@ -126,24 +126,24 @@ ON_EXIT: @return Created URB or NULL
**/
-URB*
+URB *
XhcPeiCreateUrb (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- USB_ENDPOINT *Ep;
- EFI_STATUS Status;
- URB *Urb;
+ USB_ENDPOINT *Ep;
+ EFI_STATUS Status;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
@@ -154,7 +154,7 @@ XhcPeiCreateUrb ( Ep = &Urb->Ep;
Ep->BusAddr = BusAddr;
- Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
+ Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
@@ -185,8 +185,8 @@ XhcPeiCreateUrb ( **/
VOID
XhcPeiFreeUrb (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
if ((Xhc == NULL) || (Urb == NULL)) {
@@ -209,23 +209,23 @@ XhcPeiFreeUrb ( **/
EFI_STATUS
XhcPeiCreateTransferTrb (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- VOID *OutputContext;
- TRANSFER_RING *EPRing;
- UINT8 EPType;
- UINT8 SlotId;
- UINT8 Dci;
- TRB *TrbStart;
- UINTN TotalLen;
- UINTN Len;
- UINTN TrbNum;
- EDKII_IOMMU_OPERATION MapOp;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *Map;
- EFI_STATUS Status;
+ VOID *OutputContext;
+ TRANSFER_RING *EPRing;
+ UINT8 EPType;
+ UINT8 SlotId;
+ UINT8 Dci;
+ TRB *TrbStart;
+ UINTN TotalLen;
+ UINTN Len;
+ UINTN TrbNum;
+ EDKII_IOMMU_OPERATION MapOp;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *Map;
+ EFI_STATUS Status;
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
@@ -238,27 +238,27 @@ XhcPeiCreateTransferTrb ( Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
- EPRing = (TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
- Urb->Ring = EPRing;
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+ EPRing = (TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
+ Urb->Ring = EPRing;
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
if (Xhc->HcCParams.Data.Csz == 0) {
- EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
} else {
- EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
}
//
// No need to remap.
//
if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
- if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
+ if (((UINT8)(Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EdkiiIoMmuOperationBusMasterWrite;
} else {
MapOp = EdkiiIoMmuOperationBusMasterRead;
}
- Len = Urb->DataLen;
+ Len = Urb->DataLen;
Status = IoMmuMap (MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
@@ -266,8 +266,8 @@ XhcPeiCreateTransferTrb ( return EFI_OUT_OF_RESOURCES;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
//
@@ -280,7 +280,7 @@ XhcPeiCreateTransferTrb ( //
// For control transfer, create SETUP_STAGE_TRB first.
//
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
@@ -303,6 +303,7 @@ XhcPeiCreateTransferTrb ( } else {
TrbStart->TrbCtrSetup.TRT = 0;
}
+
//
// Update the cycle bit
//
@@ -314,10 +315,10 @@ XhcPeiCreateTransferTrb ( //
if (Urb->DataLen > 0) {
XhcPeiSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);
TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);
- TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
+ TrbStart->TrbCtrData.Length = (UINT32)Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0;
TrbStart->TrbCtrData.ISP = 1;
@@ -332,18 +333,20 @@ XhcPeiCreateTransferTrb ( } else {
TrbStart->TrbCtrData.DIR = 0;
}
+
//
// Update the cycle bit
//
TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
Urb->TrbNum++;
}
+
//
// For control transfer, create STATUS_STAGE_TRB.
// Get the pointer to next TRB for status stage use
//
XhcPeiSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrStatus.IntTarget = 0;
TrbStart->TrbCtrStatus.IOC = 1;
TrbStart->TrbCtrStatus.CH = 0;
@@ -355,6 +358,7 @@ XhcPeiCreateTransferTrb ( } else {
TrbStart->TrbCtrStatus.DIR = 0;
}
+
//
// Update the cycle bit
//
@@ -364,7 +368,7 @@ XhcPeiCreateTransferTrb ( //
XhcPeiSyncTrsRing (Xhc, EPRing);
Urb->TrbNum++;
- Urb->TrbEnd = (TRB_TEMPLATE *) (UINTN) TrbStart;
+ Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
break;
@@ -373,17 +377,18 @@ XhcPeiCreateTransferTrb ( TotalLen = 0;
Len = 0;
TrbNum = 0;
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
while (TotalLen < Urb->DataLen) {
if ((TotalLen + 0x10000) >= Urb->DataLen) {
Len = Urb->DataLen - TotalLen;
} else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -408,17 +413,18 @@ XhcPeiCreateTransferTrb ( TotalLen = 0;
Len = 0;
TrbNum = 0;
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
while (TotalLen < Urb->DataLen) {
if ((TotalLen + 0x10000) >= Urb->DataLen) {
Len = Urb->DataLen - TotalLen;
} else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -439,7 +445,7 @@ XhcPeiCreateTransferTrb ( break;
default:
- DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));
+ DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n", EPType));
ASSERT (FALSE);
break;
}
@@ -463,20 +469,21 @@ XhcPeiCreateTransferTrb ( **/
EFI_STATUS
XhcPeiRecoverHaltedEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
+
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
DEBUG ((DEBUG_INFO, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId, Dci));
@@ -484,7 +491,7 @@ XhcPeiRecoverHaltedEndpoint ( // 1) Send Reset endpoint command to transit from halt to stop state
//
Status = XhcPeiResetEndpoint (Xhc, SlotId, Dci);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -493,7 +500,7 @@ XhcPeiRecoverHaltedEndpoint ( // 2) Set dequeue pointer
//
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -522,20 +529,21 @@ Done: **/
EFI_STATUS
XhcPeiDequeueTrbFromEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
+
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
DEBUG ((DEBUG_INFO, "XhcPeiDequeueTrbFromEndpoint: Stop Slot = %x, Dci = %x\n", SlotId, Dci));
@@ -543,7 +551,7 @@ XhcPeiDequeueTrbFromEndpoint ( // 1) Send Stop endpoint command to stop endpoint.
//
Status = XhcPeiStopEndpoint (Xhc, SlotId, Dci);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -552,7 +560,7 @@ XhcPeiDequeueTrbFromEndpoint ( // 2) Set dequeue pointer
//
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -578,8 +586,8 @@ Done: **/
BOOLEAN
XhcPeiIsTransferRingTrb (
- IN TRB_TEMPLATE *Trb,
- IN URB *Urb
+ IN TRB_TEMPLATE *Trb,
+ IN URB *Urb
)
{
TRB_TEMPLATE *CheckedTrb;
@@ -593,6 +601,7 @@ XhcPeiIsTransferRingTrb ( if (Trb == CheckedTrb) {
return TRUE;
}
+
CheckedTrb++;
}
@@ -611,20 +620,20 @@ XhcPeiIsTransferRingTrb ( **/
BOOLEAN
XhcPeiCheckUrbResult (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- EVT_TRB_TRANSFER *EvtTrb;
- TRB_TEMPLATE *TRBPtr;
- UINTN Index;
- UINT8 TRBType;
- EFI_STATUS Status;
- URB *CheckedUrb;
- UINT64 XhcDequeue;
- UINT32 High;
- UINT32 Low;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EVT_TRB_TRANSFER *EvtTrb;
+ TRB_TEMPLATE *TRBPtr;
+ UINTN Index;
+ UINT8 TRBType;
+ EFI_STATUS Status;
+ URB *CheckedUrb;
+ UINT64 XhcDequeue;
+ UINT32 High;
+ UINT32 Low;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Xhc != NULL) && (Urb != NULL));
@@ -646,7 +655,7 @@ XhcPeiCheckUrbResult ( //
XhcPeiSyncEventRing (Xhc, &Xhc->EventRing);
for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {
- Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **) &EvtTrb));
+ Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
if (Status == EFI_NOT_READY) {
//
// All new events are handled, return directly.
@@ -664,8 +673,8 @@ XhcPeiCheckUrbResult ( //
// Need convert pci device address to host address
//
- PhyAddr = (EFI_PHYSICAL_ADDRESS) (EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
- TRBPtr = (TRB_TEMPLATE *) (UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *) (UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
+ TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
//
// Update the status of Urb according to the finished event regardless of whether
@@ -710,11 +719,12 @@ XhcPeiCheckUrbResult ( DEBUG ((DEBUG_VERBOSE, "XhcPeiCheckUrbResult: short packet happens!\n"));
}
- TRBType = (UINT8) (TRBPtr->Type);
+ TRBType = (UINT8)(TRBPtr->Type);
if ((TRBType == TRB_TYPE_DATA_STAGE) ||
(TRBType == TRB_TYPE_NORMAL) ||
- (TRBType == TRB_TYPE_ISOCH)) {
- CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
+ (TRBType == TRB_TYPE_ISOCH))
+ {
+ CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);
}
break;
@@ -739,7 +749,7 @@ XhcPeiCheckUrbResult ( if (CheckedUrb->StartDone && CheckedUrb->EndDone) {
CheckedUrb->Finished = TRUE;
- CheckedUrb->EvtTrb = (TRB_TEMPLATE *) EvtTrb;
+ CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;
}
}
@@ -751,9 +761,9 @@ EXIT: // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- Low = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
- High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
- XhcDequeue = (UINT64) (LShiftU64((UINT64) High, 32) | Low);
+ Low = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
+ High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
+ XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
@@ -784,18 +794,18 @@ EXIT: **/
EFI_STATUS
XhcPeiExecTransfer (
- IN PEI_XHC_DEV *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINT64 Loop;
- UINT8 SlotId;
- UINT8 Dci;
- BOOLEAN Finished;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT64 Loop;
+ UINT8 SlotId;
+ UINT8 Dci;
+ BOOLEAN Finished;
if (CmdTransfer) {
SlotId = 0;
@@ -805,7 +815,8 @@ XhcPeiExecTransfer ( if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
}
Status = EFI_SUCCESS;
@@ -821,6 +832,7 @@ XhcPeiExecTransfer ( if (Finished) {
break;
}
+
MicroSecondDelay (XHC_1_MICROSECOND);
}
@@ -828,7 +840,7 @@ XhcPeiExecTransfer ( Urb->Result = EFI_USB_ERR_TIMEOUT;
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
- Status = EFI_DEVICE_ERROR;
+ Status = EFI_DEVICE_ERROR;
}
return Status;
@@ -848,16 +860,16 @@ XhcPeiExecTransfer ( **/
EFI_STATUS
XhcPeiPollPortStatusChange (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
)
{
- EFI_STATUS Status;
- UINT8 Speed;
- UINT8 SlotId;
- USB_DEV_ROUTE RouteChart;
+ EFI_STATUS Status;
+ UINT8 Speed;
+ UINT8 SlotId;
+ USB_DEV_ROUTE RouteChart;
DEBUG ((DEBUG_INFO, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState->PortChangeStatus, PortState->PortStatus));
@@ -872,13 +884,14 @@ XhcPeiPollPortStatusChange ( RouteChart.Route.RootPortNum = Port + 1;
RouteChart.Route.TierNum = 1;
} else {
- if(Port < 14) {
+ if (Port < 14) {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
} else {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
}
- RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
- RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
+
+ RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
+ RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
}
SlotId = XhcPeiRouteStringToSlotId (Xhc, RouteChart);
@@ -891,7 +904,8 @@ XhcPeiPollPortStatusChange ( }
if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
- ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
+ ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0))
+ {
//
// Has a device attached, Identify device speed after port is enabled.
//
@@ -903,6 +917,7 @@ XhcPeiPollPortStatusChange ( } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
Speed = EFI_USB_SPEED_SUPER;
}
+
//
// Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
//
@@ -930,21 +945,22 @@ XhcPeiPollPortStatusChange ( **/
UINT8
XhcPeiEndpointToDci (
- IN UINT8 EpAddr,
- IN EFI_USB_DATA_DIRECTION Direction
+ IN UINT8 EpAddr,
+ IN EFI_USB_DATA_DIRECTION Direction
)
{
- UINT8 Index;
+ UINT8 Index;
ASSERT (EpAddr <= 15);
if (EpAddr == 0) {
return 1;
} else {
- Index = (UINT8) (2 * EpAddr);
+ Index = (UINT8)(2 * EpAddr);
if (Direction == EfiUsbDataIn) {
Index += 1;
}
+
return Index;
}
}
@@ -960,16 +976,17 @@ XhcPeiEndpointToDci ( **/
UINT8
XhcPeiBusDevAddrToSlotId (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 BusDevAddr
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 BusDevAddr
)
{
- UINT8 Index;
+ UINT8 Index;
for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr))
+ {
break;
}
}
@@ -992,16 +1009,17 @@ XhcPeiBusDevAddrToSlotId ( **/
UINT8
XhcPeiRouteStringToSlotId (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE RouteString
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE RouteString
)
{
- UINT8 Index;
+ UINT8 Index;
for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword))
+ {
break;
}
}
@@ -1023,9 +1041,9 @@ XhcPeiRouteStringToSlotId ( **/
VOID
XhcPeiRingDoorBell (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
if (SlotId == 0) {
@@ -1050,25 +1068,25 @@ XhcPeiRingDoorBell ( **/
EFI_STATUS
XhcPeiInitializeDeviceSlot (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT *InputContext;
- DEVICE_CONTEXT *OutputContext;
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
- UINT8 DeviceAddress;
- CMD_TRB_ENABLE_SLOT CmdTrb;
- UINT8 SlotId;
- UINT8 ParentSlotId;
- DEVICE_CONTEXT *ParentDeviceContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT *InputContext;
+ DEVICE_CONTEXT *OutputContext;
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
+ UINT8 DeviceAddress;
+ CMD_TRB_ENABLE_SLOT CmdTrb;
+ UINT8 SlotId;
+ UINT8 ParentSlotId;
+ DEVICE_CONTEXT *ParentDeviceContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
CmdTrb.CycleBit = 1;
@@ -1076,17 +1094,18 @@ XhcPeiInitializeDeviceSlot ( Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
- SlotId = (UINT8) EvtTrb->SlotId;
+ SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
@@ -1101,10 +1120,10 @@ XhcPeiInitializeDeviceSlot ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -1130,9 +1149,10 @@ XhcPeiInitializeDeviceSlot ( //
// If the Full/Low device attached to a High Speed Hub, init the TTPortNum and TTHubSlotId field of slot context
//
- ParentDeviceContext = (DEVICE_CONTEXT *) Xhc->UsbDevContext[ParentSlotId].OutputContext;
+ ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -1159,9 +1179,9 @@ XhcPeiInitializeDeviceSlot ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -1174,6 +1194,7 @@ XhcPeiInitializeDeviceSlot ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -1190,7 +1211,7 @@ XhcPeiInitializeDeviceSlot ( //
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
@@ -1201,7 +1222,7 @@ XhcPeiInitializeDeviceSlot ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -1213,7 +1234,7 @@ XhcPeiInitializeDeviceSlot ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -1224,20 +1245,20 @@ XhcPeiInitializeDeviceSlot ( //
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)OutputContext->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
}
@@ -1261,25 +1282,25 @@ XhcPeiInitializeDeviceSlot ( **/
EFI_STATUS
XhcPeiInitializeDeviceSlot64 (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT_64 *InputContext;
- DEVICE_CONTEXT_64 *OutputContext;
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
- UINT8 DeviceAddress;
- CMD_TRB_ENABLE_SLOT CmdTrb;
- UINT8 SlotId;
- UINT8 ParentSlotId;
- DEVICE_CONTEXT_64 *ParentDeviceContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT_64 *InputContext;
+ DEVICE_CONTEXT_64 *OutputContext;
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
+ UINT8 DeviceAddress;
+ CMD_TRB_ENABLE_SLOT CmdTrb;
+ UINT8 SlotId;
+ UINT8 ParentSlotId;
+ DEVICE_CONTEXT_64 *ParentDeviceContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
CmdTrb.CycleBit = 1;
@@ -1287,14 +1308,15 @@ XhcPeiInitializeDeviceSlot64 ( Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
@@ -1312,10 +1334,10 @@ XhcPeiInitializeDeviceSlot64 ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -1339,11 +1361,12 @@ XhcPeiInitializeDeviceSlot64 ( ParentSlotId = XhcPeiRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
- ParentDeviceContext = (DEVICE_CONTEXT_64 *) Xhc->UsbDevContext[ParentSlotId].OutputContext;
+ ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -1370,9 +1393,9 @@ XhcPeiInitializeDeviceSlot64 ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- XhcPeiCreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -1385,6 +1408,7 @@ XhcPeiInitializeDeviceSlot64 ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -1401,7 +1425,7 @@ XhcPeiInitializeDeviceSlot64 ( //
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
@@ -1412,7 +1436,7 @@ XhcPeiInitializeDeviceSlot64 ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -1424,7 +1448,7 @@ XhcPeiInitializeDeviceSlot64 ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -1435,20 +1459,20 @@ XhcPeiInitializeDeviceSlot64 ( //
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)OutputContext->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
}
@@ -1457,7 +1481,6 @@ XhcPeiInitializeDeviceSlot64 ( return Status;
}
-
/**
Disable the specified device slot.
@@ -1469,8 +1492,8 @@ XhcPeiInitializeDeviceSlot64 ( **/
EFI_STATUS
XhcPeiDisableSlotCmd (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -1486,7 +1509,8 @@ XhcPeiDisableSlotCmd ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -1507,16 +1531,17 @@ XhcPeiDisableSlotCmd ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -1527,10 +1552,11 @@ XhcPeiDisableSlotCmd ( //
for (Index = 0; Index < 31; Index++) {
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
- RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -1549,6 +1575,7 @@ XhcPeiDisableSlotCmd ( if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -1572,8 +1599,8 @@ XhcPeiDisableSlotCmd ( **/
EFI_STATUS
XhcPeiDisableSlotCmd64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -1589,7 +1616,8 @@ XhcPeiDisableSlotCmd64 ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -1610,16 +1638,17 @@ XhcPeiDisableSlotCmd64 ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -1630,10 +1659,11 @@ XhcPeiDisableSlotCmd64 ( //
for (Index = 0; Index < 31; Index++) {
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
- RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -1650,8 +1680,9 @@ XhcPeiDisableSlotCmd64 ( }
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -1677,30 +1708,31 @@ XhcPeiDisableSlotCmd64 ( **/
EFI_STATUS
XhcPeiSetConfigCmd (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINT8 Index;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- EFI_USB_DATA_DIRECTION Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
-
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- INPUT_CONTEXT *InputContext;
- DEVICE_CONTEXT *OutputContext;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINT8 Index;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ EFI_USB_DATA_DIRECTION Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ INPUT_CONTEXT *InputContext;
+ DEVICE_CONTEXT *OutputContext;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -1713,22 +1745,22 @@ XhcPeiSetConfigCmd ( MaxDci = 0;
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
NumEp = IfDesc->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcPeiEndpointToDci (EpAddr, Direction);
if (Dci > MaxDci) {
@@ -1759,9 +1791,9 @@ XhcPeiSetConfigCmd ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
break;
@@ -1773,6 +1805,7 @@ XhcPeiSetConfigCmd ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -1801,6 +1834,7 @@ XhcPeiSetConfigCmd ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -1812,7 +1846,7 @@ XhcPeiSetConfigCmd ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32 ((UINT32) Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -1823,10 +1857,11 @@ XhcPeiSetConfigCmd ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -1842,17 +1877,18 @@ XhcPeiSetConfigCmd ( PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
+
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
InputContext->InputControlContext.Dword2 |= BIT0;
@@ -1861,7 +1897,7 @@ XhcPeiSetConfigCmd ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -1870,13 +1906,14 @@ XhcPeiSetConfigCmd ( DEBUG ((DEBUG_INFO, "XhcSetConfigCmd: Configure Endpoint\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -1893,30 +1930,31 @@ XhcPeiSetConfigCmd ( **/
EFI_STATUS
XhcPeiSetConfigCmd64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINT8 Index;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- EFI_USB_DATA_DIRECTION Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
-
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- INPUT_CONTEXT_64 *InputContext;
- DEVICE_CONTEXT_64 *OutputContext;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINT8 Index;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ EFI_USB_DATA_DIRECTION Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ INPUT_CONTEXT_64 *InputContext;
+ DEVICE_CONTEXT_64 *OutputContext;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -1929,22 +1967,22 @@ XhcPeiSetConfigCmd64 ( MaxDci = 0;
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
NumEp = IfDesc->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcPeiEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
@@ -1976,9 +2014,9 @@ XhcPeiSetConfigCmd64 ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
break;
@@ -1990,6 +2028,7 @@ XhcPeiSetConfigCmd64 ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -2018,6 +2057,7 @@ XhcPeiSetConfigCmd64 ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -2029,7 +2069,7 @@ XhcPeiSetConfigCmd64 ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32( (UINT32) Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -2040,10 +2080,11 @@ XhcPeiSetConfigCmd64 ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -2059,19 +2100,20 @@ XhcPeiSetConfigCmd64 ( PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN)EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN)IfDesc + IfDesc->Length);
+
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
InputContext->InputControlContext.Dword2 |= BIT0;
@@ -2080,7 +2122,7 @@ XhcPeiSetConfigCmd64 ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -2089,9 +2131,9 @@ XhcPeiSetConfigCmd64 ( DEBUG ((DEBUG_INFO, "XhcSetConfigCmd64: Configure Endpoint\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
@@ -2100,7 +2142,6 @@ XhcPeiSetConfigCmd64 ( return Status;
}
-
/**
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
@@ -2113,16 +2154,16 @@ XhcPeiSetConfigCmd64 ( **/
EFI_STATUS
XhcPeiEvaluateContext (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
- EFI_STATUS Status;
- CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT *InputContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT *InputContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@@ -2136,7 +2177,7 @@ XhcPeiEvaluateContext ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -2145,13 +2186,14 @@ XhcPeiEvaluateContext ( DEBUG ((DEBUG_INFO, "XhcEvaluateContext: Evaluate context\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2167,16 +2209,16 @@ XhcPeiEvaluateContext ( **/
EFI_STATUS
XhcPeiEvaluateContext64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
- EFI_STATUS Status;
- CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT_64 *InputContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT_64 *InputContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@@ -2190,7 +2232,7 @@ XhcPeiEvaluateContext64 ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -2199,13 +2241,14 @@ XhcPeiEvaluateContext64 ( DEBUG ((DEBUG_INFO, "XhcEvaluateContext64: Evaluate context 64\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2223,19 +2266,19 @@ XhcPeiEvaluateContext64 ( **/
EFI_STATUS
XhcPeiConfigHubContext (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT *InputContext;
- DEVICE_CONTEXT *OutputContext;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT *InputContext;
+ DEVICE_CONTEXT *OutputContext;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
InputContext = Xhc->UsbDevContext[SlotId].InputContext;
@@ -2251,14 +2294,14 @@ XhcPeiConfigHubContext ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -2267,13 +2310,14 @@ XhcPeiConfigHubContext ( DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2291,19 +2335,19 @@ XhcPeiConfigHubContext ( **/
EFI_STATUS
XhcPeiConfigHubContext64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT_64 *InputContext;
- DEVICE_CONTEXT_64 *OutputContext;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT_64 *InputContext;
+ DEVICE_CONTEXT_64 *OutputContext;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
InputContext = Xhc->UsbDevContext[SlotId].InputContext;
@@ -2319,14 +2363,14 @@ XhcPeiConfigHubContext64 ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -2335,13 +2379,14 @@ XhcPeiConfigHubContext64 ( DEBUG ((DEBUG_INFO, "Configure Hub Slot Context 64\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2359,14 +2404,14 @@ XhcPeiConfigHubContext64 ( EFI_STATUS
EFIAPI
XhcPeiStopEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
DEBUG ((DEBUG_INFO, "XhcPeiStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
@@ -2378,13 +2423,13 @@ XhcPeiStopEndpoint ( CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
CmdTrbStopED.EDID = Dci;
CmdTrbStopED.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbStopED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
@@ -2405,9 +2450,9 @@ XhcPeiStopEndpoint ( EFI_STATUS
EFIAPI
XhcPeiResetEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
EFI_STATUS Status;
@@ -2424,13 +2469,13 @@ XhcPeiResetEndpoint ( CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
CmdTrbResetED.EDID = Dci;
CmdTrbResetED.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbResetED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
@@ -2453,10 +2498,10 @@ XhcPeiResetEndpoint ( EFI_STATUS
EFIAPI
XhcPeiSetTrDequeuePointer (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
)
{
EFI_STATUS Status;
@@ -2470,20 +2515,20 @@ XhcPeiSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;
CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
CmdSetTRDeq.Endpoint = Dci;
CmdSetTRDeq.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdSetTRDeq,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
@@ -2503,9 +2548,9 @@ XhcPeiSetTrDequeuePointer ( **/
EFI_STATUS
XhcPeiCheckNewEvent (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
)
{
ASSERT (EvtRing != NULL);
@@ -2520,7 +2565,7 @@ XhcPeiCheckNewEvent ( //
// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
//
- if ((UINTN) EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
}
@@ -2538,12 +2583,12 @@ XhcPeiCheckNewEvent ( **/
EFI_STATUS
XhcPeiSyncEventRing (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EvtRing
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EvtRing
)
{
- UINTN Index;
- TRB_TEMPLATE *EvtTrb;
+ UINTN Index;
+ TRB_TEMPLATE *EvtTrb;
ASSERT (EvtRing != NULL);
@@ -2560,8 +2605,8 @@ XhcPeiSyncEventRing ( EvtTrb++;
- if ((UINTN) EvtTrb >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
- EvtTrb = EvtRing->EventRingSeg0;
+ if ((UINTN)EvtTrb >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ EvtTrb = EvtRing->EventRingSeg0;
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
}
}
@@ -2584,11 +2629,11 @@ XhcPeiSyncEventRing ( **/
VOID
XhcPeiFreeEventRing (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EventRing
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EventRing
)
{
- if(EventRing->EventRingSeg0 == NULL) {
+ if (EventRing->EventRingSeg0 == NULL) {
return;
}
@@ -2612,30 +2657,30 @@ XhcPeiFreeEventRing ( **/
VOID
XhcPeiCreateEventRing (
- IN PEI_XHC_DEV *Xhc,
- OUT EVENT_RING *EventRing
+ IN PEI_XHC_DEV *Xhc,
+ OUT EVENT_RING *EventRing
)
{
- VOID *Buf;
- EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
- UINTN Size;
- EFI_PHYSICAL_ADDRESS ERSTPhy;
- EFI_PHYSICAL_ADDRESS DequeuePhy;
+ VOID *Buf;
+ EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
+ UINTN Size;
+ EFI_PHYSICAL_ADDRESS ERSTPhy;
+ EFI_PHYSICAL_ADDRESS DequeuePhy;
ASSERT (EventRing != NULL);
Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
- EventRing->EventRingSeg0 = Buf;
- EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
- EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
- EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
+ EventRing->EventRingSeg0 = Buf;
+ EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
+ EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
+ EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
//
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
@@ -2644,12 +2689,12 @@ XhcPeiCreateEventRing ( EventRing->EventRingCCS = 1;
Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
- ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
+ ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;
EventRing->ERSTBase = ERSTBase;
ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
@@ -2674,12 +2719,12 @@ XhcPeiCreateEventRing ( XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET,
- XHC_LOW_32BIT ((UINT64) (UINTN) DequeuePhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)
);
XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET + 4,
- XHC_HIGH_32BIT ((UINT64) (UINTN) DequeuePhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)
);
//
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register (5.5.2.3.2)
@@ -2690,12 +2735,12 @@ XhcPeiCreateEventRing ( XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET,
- XHC_LOW_32BIT ((UINT64) (UINTN) ERSTPhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)ERSTPhy)
);
XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET + 4,
- XHC_HIGH_32BIT ((UINT64) (UINTN) ERSTPhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTPhy)
);
//
// Need set IMAN IE bit to enable the ring interrupt
@@ -2718,8 +2763,8 @@ XhcPeiSyncTrsRing ( IN TRANSFER_RING *TrsRing
)
{
- UINTN Index;
- TRB_TEMPLATE *TrsTrb;
+ UINTN Index;
+ TRB_TEMPLATE *TrsTrb;
ASSERT (TrsRing != NULL);
//
@@ -2732,18 +2777,19 @@ XhcPeiSyncTrsRing ( if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
}
+
TrsTrb++;
- if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
- ASSERT (((LINK_TRB *) TrsTrb)->TC != 0);
+ if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {
+ ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);
//
// set cycle bit in Link TRB as normal
//
- ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
+ ((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
//
// Toggle PCS maintained by software
//
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
- TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
+ TrsTrb = (TRB_TEMPLATE *)TrsRing->RingSeg0; // Use host address
}
}
@@ -2776,9 +2822,9 @@ XhcPeiSyncTrsRing ( **/
VOID
XhcPeiCreateTransferRing (
- IN PEI_XHC_DEV *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN PEI_XHC_DEV *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
)
{
VOID *Buf;
@@ -2787,28 +2833,28 @@ XhcPeiCreateTransferRing ( Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
- TransferRing->RingSeg0 = Buf;
- TransferRing->TrbNumber = TrbNum;
- TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingPCS = 1;
+ TransferRing->RingSeg0 = Buf;
+ TransferRing->TrbNumber = TrbNum;
+ TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingPCS = 1;
//
// 4.9.2 Transfer Ring Management
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
// point to the first TRB in the ring.
//
- EndTrb = (LINK_TRB *) ((UINTN) Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
+ EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK;
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
//
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
//
- EndTrb->TC = 1;
+ EndTrb->TC = 1;
//
// Set Cycle bit as other TRB PCS init value
//
@@ -2823,7 +2869,7 @@ XhcPeiCreateTransferRing ( **/
VOID
XhcPeiInitSched (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
)
{
VOID *Dcbaa;
@@ -2859,7 +2905,7 @@ XhcPeiInitSched ( // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
//
- Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
+ Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Dcbaa != NULL);
@@ -2887,13 +2933,13 @@ XhcPeiInitSched ( Xhc->ScratchEntry = ScratchEntry;
ScratchPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
- Xhc->PageSize,
- (VOID **) &ScratchBuf,
- &ScratchPhy,
- &Xhc->ScratchMap
- );
+ Status = UsbHcAllocateAlignedPages (
+ EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
+ Xhc->PageSize,
+ (VOID **)&ScratchBuf,
+ &ScratchPhy,
+ &Xhc->ScratchMap
+ );
ASSERT_EFI_ERROR (Status);
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
@@ -2904,32 +2950,33 @@ XhcPeiInitSched ( //
for (Index = 0; Index < MaxScratchpadBufs; Index++) {
ScratchEntryPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- EFI_SIZE_TO_PAGES (Xhc->PageSize),
- Xhc->PageSize,
- (VOID **) &ScratchEntry[Index],
- &ScratchEntryPhy,
- (VOID **) &ScratchEntryMap[Index]
- );
+ Status = UsbHcAllocateAlignedPages (
+ EFI_SIZE_TO_PAGES (Xhc->PageSize),
+ Xhc->PageSize,
+ (VOID **)&ScratchEntry[Index],
+ &ScratchEntryPhy,
+ (VOID **)&ScratchEntryMap[Index]
+ );
ASSERT_EFI_ERROR (Status);
- ZeroMem ((VOID *) (UINTN) ScratchEntry[Index], Xhc->PageSize);
+ ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
//
// Fill with the PCI device address
//
*ScratchBuf++ = ScratchEntryPhy;
}
+
//
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
// Device Context Base Address Array points to the Scratchpad Buffer Array.
//
- *(UINT64 *) Dcbaa = (UINT64) (UINTN) ScratchPhy;
+ *(UINT64 *)Dcbaa = (UINT64)(UINTN)ScratchPhy;
}
//
// Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
// a 64-bit address pointing to where the Device Context Base Address Array is located.
//
- Xhc->DCBAA = (UINT64 *) (UINTN) Dcbaa;
+ Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;
//
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
@@ -2989,11 +3036,11 @@ XhcPeiInitSched ( **/
VOID
XhcPeiFreeSched (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
)
{
- UINT32 Index;
- UINT64 *ScratchEntry;
+ UINT32 Index;
+ UINT64 *ScratchEntry;
if (Xhc->ScratchBuf != NULL) {
ScratchEntry = Xhc->ScratchEntry;
@@ -3001,8 +3048,9 @@ XhcPeiFreeSched ( //
// Free Scratchpad Buffers
//
- UsbHcFreeAlignedPages ((VOID*) (UINTN) ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
+ UsbHcFreeAlignedPages ((VOID *)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *)Xhc->ScratchEntryMap[Index]);
}
+
//
// Free Scratchpad Buffer Array
//
@@ -3016,7 +3064,7 @@ XhcPeiFreeSched ( Xhc->CmdRing.RingSeg0 = NULL;
}
- XhcPeiFreeEventRing (Xhc,&Xhc->EventRing);
+ XhcPeiFreeEventRing (Xhc, &Xhc->EventRing);
if (Xhc->DCBAA != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h index badc57a51b..bbe6232797 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h @@ -13,62 +13,62 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Transfer types, used in URB to identify the transfer type
//
-#define XHC_CTRL_TRANSFER 0x01
-#define XHC_BULK_TRANSFER 0x02
+#define XHC_CTRL_TRANSFER 0x01
+#define XHC_BULK_TRANSFER 0x02
//
// 6.4.6 TRB Types
//
-#define TRB_TYPE_NORMAL 1
-#define TRB_TYPE_SETUP_STAGE 2
-#define TRB_TYPE_DATA_STAGE 3
-#define TRB_TYPE_STATUS_STAGE 4
-#define TRB_TYPE_ISOCH 5
-#define TRB_TYPE_LINK 6
-#define TRB_TYPE_EVENT_DATA 7
-#define TRB_TYPE_NO_OP 8
-#define TRB_TYPE_EN_SLOT 9
-#define TRB_TYPE_DIS_SLOT 10
-#define TRB_TYPE_ADDRESS_DEV 11
-#define TRB_TYPE_CON_ENDPOINT 12
-#define TRB_TYPE_EVALU_CONTXT 13
-#define TRB_TYPE_RESET_ENDPOINT 14
-#define TRB_TYPE_STOP_ENDPOINT 15
-#define TRB_TYPE_SET_TR_DEQUE 16
-#define TRB_TYPE_RESET_DEV 17
-#define TRB_TYPE_GET_PORT_BANW 21
-#define TRB_TYPE_FORCE_HEADER 22
-#define TRB_TYPE_NO_OP_COMMAND 23
-#define TRB_TYPE_TRANS_EVENT 32
-#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
-#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
-#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
-#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
-#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
+#define TRB_TYPE_NORMAL 1
+#define TRB_TYPE_SETUP_STAGE 2
+#define TRB_TYPE_DATA_STAGE 3
+#define TRB_TYPE_STATUS_STAGE 4
+#define TRB_TYPE_ISOCH 5
+#define TRB_TYPE_LINK 6
+#define TRB_TYPE_EVENT_DATA 7
+#define TRB_TYPE_NO_OP 8
+#define TRB_TYPE_EN_SLOT 9
+#define TRB_TYPE_DIS_SLOT 10
+#define TRB_TYPE_ADDRESS_DEV 11
+#define TRB_TYPE_CON_ENDPOINT 12
+#define TRB_TYPE_EVALU_CONTXT 13
+#define TRB_TYPE_RESET_ENDPOINT 14
+#define TRB_TYPE_STOP_ENDPOINT 15
+#define TRB_TYPE_SET_TR_DEQUE 16
+#define TRB_TYPE_RESET_DEV 17
+#define TRB_TYPE_GET_PORT_BANW 21
+#define TRB_TYPE_FORCE_HEADER 22
+#define TRB_TYPE_NO_OP_COMMAND 23
+#define TRB_TYPE_TRANS_EVENT 32
+#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
+#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
+#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
+#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
+#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
//
// Endpoint Type (EP Type).
//
-#define ED_NOT_VALID 0
-#define ED_ISOCH_OUT 1
-#define ED_BULK_OUT 2
-#define ED_INTERRUPT_OUT 3
-#define ED_CONTROL_BIDIR 4
-#define ED_ISOCH_IN 5
-#define ED_BULK_IN 6
-#define ED_INTERRUPT_IN 7
+#define ED_NOT_VALID 0
+#define ED_ISOCH_OUT 1
+#define ED_BULK_OUT 2
+#define ED_INTERRUPT_OUT 3
+#define ED_CONTROL_BIDIR 4
+#define ED_ISOCH_IN 5
+#define ED_BULK_IN 6
+#define ED_INTERRUPT_IN 7
//
// 6.4.5 TRB Completion Codes
//
-#define TRB_COMPLETION_INVALID 0
-#define TRB_COMPLETION_SUCCESS 1
-#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
-#define TRB_COMPLETION_BABBLE_ERROR 3
-#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
-#define TRB_COMPLETION_TRB_ERROR 5
-#define TRB_COMPLETION_STALL_ERROR 6
-#define TRB_COMPLETION_SHORT_PACKET 13
+#define TRB_COMPLETION_INVALID 0
+#define TRB_COMPLETION_SUCCESS 1
+#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
+#define TRB_COMPLETION_BABBLE_ERROR 3
+#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
+#define TRB_COMPLETION_TRB_ERROR 5
+#define TRB_COMPLETION_STALL_ERROR 6
+#define TRB_COMPLETION_SHORT_PACKET 13
//
// The topology string used to present usb device location
@@ -77,23 +77,23 @@ typedef struct _USB_DEV_TOPOLOGY { //
// The tier concatenation of down stream port.
//
- UINT32 RouteString:20;
+ UINT32 RouteString : 20;
//
// The root port number of the chain.
//
- UINT32 RootPortNum:8;
+ UINT32 RootPortNum : 8;
//
// The Tier the device reside.
//
- UINT32 TierNum:4;
+ UINT32 TierNum : 4;
} USB_DEV_TOPOLOGY;
//
// USB Device's RouteChart
//
typedef union _USB_DEV_ROUTE {
- UINT32 Dword;
- USB_DEV_TOPOLOGY Route;
+ UINT32 Dword;
+ USB_DEV_TOPOLOGY Route;
} USB_DEV_ROUTE;
//
@@ -118,74 +118,74 @@ typedef struct _USB_ENDPOINT { // TRB Template
//
typedef struct _TRB_TEMPLATE {
- UINT32 Parameter1;
+ UINT32 Parameter1;
- UINT32 Parameter2;
+ UINT32 Parameter2;
- UINT32 Status;
+ UINT32 Status;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:9;
- UINT32 Type:6;
- UINT32 Control:16;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 9;
+ UINT32 Type : 6;
+ UINT32 Control : 16;
} TRB_TEMPLATE;
typedef struct _TRANSFER_RING {
- VOID *RingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *RingEnqueue;
- TRB_TEMPLATE *RingDequeue;
- UINT32 RingPCS;
+ VOID *RingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *RingEnqueue;
+ TRB_TEMPLATE *RingDequeue;
+ UINT32 RingPCS;
} TRANSFER_RING;
typedef struct _EVENT_RING {
- VOID *ERSTBase;
- VOID *EventRingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *EventRingEnqueue;
- TRB_TEMPLATE *EventRingDequeue;
- UINT32 EventRingCCS;
+ VOID *ERSTBase;
+ VOID *EventRingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *EventRingEnqueue;
+ TRB_TEMPLATE *EventRingDequeue;
+ UINT32 EventRingCCS;
} EVENT_RING;
-#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// URB (Usb Request Block) contains information for all kinds of
// usb requests.
//
typedef struct _URB {
- UINT32 Signature;
+ UINT32 Signature;
//
// Usb Device URB related information
//
- USB_ENDPOINT Ep;
- EFI_USB_DEVICE_REQUEST *Request;
- VOID *Data;
- UINTN DataLen;
- VOID *DataPhy;
- VOID *DataMap;
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ USB_ENDPOINT Ep;
+ EFI_USB_DEVICE_REQUEST *Request;
+ VOID *Data;
+ UINTN DataLen;
+ VOID *DataPhy;
+ VOID *DataMap;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
//
// Execute result
//
- UINT32 Result;
+ UINT32 Result;
//
// completed data length
//
- UINTN Completed;
+ UINTN Completed;
//
// Command/Tranfer Ring info
//
- TRANSFER_RING *Ring;
- TRB_TEMPLATE *TrbStart;
- TRB_TEMPLATE *TrbEnd;
- UINTN TrbNum;
- BOOLEAN StartDone;
- BOOLEAN EndDone;
- BOOLEAN Finished;
-
- TRB_TEMPLATE *EvtTrb;
+ TRANSFER_RING *Ring;
+ TRB_TEMPLATE *TrbStart;
+ TRB_TEMPLATE *TrbEnd;
+ UINTN TrbNum;
+ BOOLEAN StartDone;
+ BOOLEAN EndDone;
+ BOOLEAN Finished;
+
+ TRB_TEMPLATE *EvtTrb;
} URB;
//
@@ -196,11 +196,11 @@ typedef struct _URB { // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
//
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
- UINT32 PtrLo;
- UINT32 PtrHi;
- UINT32 RingTrbSize:16;
- UINT32 RsvdZ1:16;
- UINT32 RsvdZ2;
+ UINT32 PtrLo;
+ UINT32 PtrHi;
+ UINT32 RingTrbSize : 16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 RsvdZ2;
} EVENT_RING_SEG_TABLE_ENTRY;
//
@@ -210,25 +210,25 @@ typedef struct _EVENT_RING_SEG_TABLE_ENTRY { // Rings, and to define the Data stage information for Control Transfer Rings.
//
typedef struct _TRANSFER_TRB_NORMAL {
- UINT32 TRBPtrLo;
-
- UINT32 TRBPtrHi;
-
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:2;
- UINT32 BEI:1;
- UINT32 Type:6;
- UINT32 RsvdZ2:16;
+ UINT32 TRBPtrLo;
+
+ UINT32 TRBPtrHi;
+
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 2;
+ UINT32 BEI : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ2 : 16;
} TRANSFER_TRB_NORMAL;
//
@@ -236,25 +236,25 @@ typedef struct _TRANSFER_TRB_NORMAL { // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
//
typedef struct _TRANSFER_TRB_CONTROL_SETUP {
- UINT32 bmRequestType:8;
- UINT32 bRequest:8;
- UINT32 wValue:16;
-
- UINT32 wIndex:16;
- UINT32 wLength:16;
-
- UINT32 Length:17;
- UINT32 RsvdZ1:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:4;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ3:3;
- UINT32 Type:6;
- UINT32 TRT:2;
- UINT32 RsvdZ4:14;
+ UINT32 bmRequestType : 8;
+ UINT32 bRequest : 8;
+ UINT32 wValue : 16;
+
+ UINT32 wIndex : 16;
+ UINT32 wLength : 16;
+
+ UINT32 Length : 17;
+ UINT32 RsvdZ1 : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 4;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ3 : 3;
+ UINT32 Type : 6;
+ UINT32 TRT : 2;
+ UINT32 RsvdZ4 : 14;
} TRANSFER_TRB_CONTROL_SETUP;
//
@@ -262,25 +262,25 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_DATA {
- UINT32 TRBPtrLo;
-
- UINT32 TRBPtrHi;
-
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:3;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ2:15;
+ UINT32 TRBPtrLo;
+
+ UINT32 TRBPtrHi;
+
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 3;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ2 : 15;
} TRANSFER_TRB_CONTROL_DATA;
//
@@ -288,21 +288,21 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_STATUS {
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 RsvdZ3:22;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 RsvdZ4:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ5:4;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ6:15;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 RsvdZ3 : 22;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 RsvdZ4 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ5 : 4;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ6 : 15;
} TRANSFER_TRB_CONTROL_STATUS;
//
@@ -311,21 +311,21 @@ typedef struct _TRANSFER_TRB_CONTROL_STATUS { // for more information on the use and operation of Transfer Events.
//
typedef struct _EVT_TRB_TRANSFER {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 Length:24;
- UINT32 Completecode:8;
+ UINT32 Length : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:1;
- UINT32 ED:1;
- UINT32 RsvdZ2:7;
- UINT32 Type:6;
- UINT32 EndpointId:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 1;
+ UINT32 ED : 1;
+ UINT32 RsvdZ2 : 7;
+ UINT32 Type : 6;
+ UINT32 EndpointId : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} EVT_TRB_TRANSFER;
//
@@ -334,26 +334,26 @@ typedef struct _EVT_TRB_TRANSFER { // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
//
typedef struct _EVT_TRB_COMMAND_COMPLETION {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 RsvdZ2:24;
- UINT32 Completecode:8;
+ UINT32 RsvdZ2 : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 VFID:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 VFID : 8;
+ UINT32 SlotId : 8;
} EVT_TRB_COMMAND_COMPLETION;
typedef union _TRB {
- TRB_TEMPLATE TrbTemplate;
- TRANSFER_TRB_NORMAL TrbNormal;
- TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
- TRANSFER_TRB_CONTROL_DATA TrbCtrData;
- TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
+ TRB_TEMPLATE TrbTemplate;
+ TRANSFER_TRB_NORMAL TrbNormal;
+ TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
+ TRANSFER_TRB_CONTROL_DATA TrbCtrData;
+ TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
} TRB;
//
@@ -362,14 +362,14 @@ typedef union _TRB { // mechanisms offered by the xHCI.
//
typedef struct _CMD_TRB_NO_OP {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_NO_OP;
//
@@ -378,14 +378,14 @@ typedef struct _CMD_TRB_NO_OP { // selected slot to the host in a Command Completion Event.
//
typedef struct _CMD_TRB_ENABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_ENABLE_SLOT;
//
@@ -394,15 +394,15 @@ typedef struct _CMD_TRB_ENABLE_SLOT { // internal xHC resources assigned to the slot.
//
typedef struct _CMD_TRB_DISABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:8;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_DISABLE_SLOT;
//
@@ -412,18 +412,18 @@ typedef struct _CMD_TRB_DISABLE_SLOT { // issue a SET_ADDRESS request to the USB device.
//
typedef struct _CMD_TRB_ADDRESS_DEVICE {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 BSR:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 BSR : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_ADDRESS_DEVICE;
//
@@ -432,18 +432,18 @@ typedef struct _CMD_TRB_ADDRESS_DEVICE { // endpoints selected by the command.
//
typedef struct _CMD_TRB_CONFIG_ENDPOINT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 DC:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 DC : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_CONFIG_ENDPOINT;
//
@@ -453,17 +453,17 @@ typedef struct _CMD_TRB_CONFIG_ENDPOINT { // shall evaluate any changes
//
typedef struct _CMD_TRB_EVALUATE_CONTEXT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_EVALUATE_CONTEXT;
//
@@ -471,17 +471,17 @@ typedef struct _CMD_TRB_EVALUATE_CONTEXT { // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
//
typedef struct _CMD_TRB_RESET_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:8;
- UINT32 TSP:1;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:3;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 8;
+ UINT32 TSP : 1;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 3;
+ UINT32 SlotId : 8;
} CMD_TRB_RESET_ENDPOINT;
//
@@ -490,17 +490,17 @@ typedef struct _CMD_TRB_RESET_ENDPOINT { // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
//
typedef struct _CMD_TRB_STOP_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:2;
- UINT32 SP:1;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 2;
+ UINT32 SP : 1;
+ UINT32 SlotId : 8;
} CMD_TRB_STOP_ENDPOINT;
//
@@ -509,19 +509,19 @@ typedef struct _CMD_TRB_STOP_ENDPOINT { // Pointer and DCS fields of an Endpoint or Stream Context.
//
typedef struct _CMD_SET_TR_DEQ_POINTER {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:16;
- UINT32 StreamID:16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 StreamID : 16;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 Endpoint:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 Endpoint : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} CMD_SET_TR_DEQ_POINTER;
//
@@ -529,226 +529,222 @@ typedef struct _CMD_SET_TR_DEQ_POINTER { // A Link TRB provides support for non-contiguous TRB Rings.
//
typedef struct _LINK_TRB {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:22;
- UINT32 InterTarget:10;
+ UINT32 RsvdZ1 : 22;
+ UINT32 InterTarget : 10;
- UINT32 CycleBit:1;
- UINT32 TC:1;
- UINT32 RsvdZ2:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ3:4;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 CycleBit : 1;
+ UINT32 TC : 1;
+ UINT32 RsvdZ2 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ3 : 4;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} LINK_TRB;
//
// 6.2.2 Slot Context
//
typedef struct _SLOT_CONTEXT {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
-
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
-
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
-
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
-
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
+
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
+
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
+
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
+
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} SLOT_CONTEXT;
typedef struct _SLOT_CONTEXT_64 {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
-
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
-
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
-
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
-
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
-
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
-
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
+
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
+
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
+
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
+
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} SLOT_CONTEXT_64;
-
//
// 6.2.3 Endpoint Context
//
typedef struct _ENDPOINT_CONTEXT {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
-
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
-
- UINT32 PtrLo;
-
- UINT32 PtrHi;
-
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
-
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
+
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
+
+ UINT32 PtrLo;
+
+ UINT32 PtrHi;
+
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
+
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} ENDPOINT_CONTEXT;
typedef struct _ENDPOINT_CONTEXT_64 {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
-
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
-
- UINT32 PtrLo;
-
- UINT32 PtrHi;
-
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
-
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
-
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
-
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
+
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
+
+ UINT32 PtrLo;
+
+ UINT32 PtrHi;
+
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
+
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} ENDPOINT_CONTEXT_64;
-
//
// 6.2.5.1 Input Control Context
//
typedef struct _INPUT_CONTRL_CONTEXT {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
} INPUT_CONTRL_CONTEXT;
typedef struct _INPUT_CONTRL_CONTEXT_64 {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
} INPUT_CONTRL_CONTEXT_64;
//
// 6.2.1 Device Context
//
typedef struct _DEVICE_CONTEXT {
- SLOT_CONTEXT Slot;
- ENDPOINT_CONTEXT EP[31];
+ SLOT_CONTEXT Slot;
+ ENDPOINT_CONTEXT EP[31];
} DEVICE_CONTEXT;
typedef struct _DEVICE_CONTEXT_64 {
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} DEVICE_CONTEXT_64;
//
// 6.2.5 Input Context
//
typedef struct _INPUT_CONTEXT {
- INPUT_CONTRL_CONTEXT InputControlContext;
- SLOT_CONTEXT Slot;
- ENDPOINT_CONTEXT EP[31];
+ INPUT_CONTRL_CONTEXT InputControlContext;
+ SLOT_CONTEXT Slot;
+ ENDPOINT_CONTEXT EP[31];
} INPUT_CONTEXT;
typedef struct _INPUT_CONTEXT_64 {
- INPUT_CONTRL_CONTEXT_64 InputControlContext;
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ INPUT_CONTRL_CONTEXT_64 InputControlContext;
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} INPUT_CONTEXT_64;
/**
@@ -766,10 +762,10 @@ typedef struct _INPUT_CONTEXT_64 { **/
EFI_STATUS
XhcPeiExecTransfer (
- IN PEI_XHC_DEV *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
);
/**
@@ -783,8 +779,8 @@ XhcPeiExecTransfer ( **/
UINT8
XhcPeiBusDevAddrToSlotId (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 BusDevAddr
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 BusDevAddr
);
/**
@@ -798,8 +794,8 @@ XhcPeiBusDevAddrToSlotId ( **/
UINT8
XhcPeiRouteStringToSlotId (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE RouteString
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE RouteString
);
/**
@@ -813,8 +809,8 @@ XhcPeiRouteStringToSlotId ( **/
UINT8
XhcPeiEndpointToDci (
- IN UINT8 EpAddr,
- IN EFI_USB_DATA_DIRECTION Direction
+ IN UINT8 EpAddr,
+ IN EFI_USB_DATA_DIRECTION Direction
);
/**
@@ -827,9 +823,9 @@ XhcPeiEndpointToDci ( **/
VOID
XhcPeiRingDoorBell (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -846,10 +842,10 @@ XhcPeiRingDoorBell ( **/
EFI_STATUS
XhcPeiPollPortStatusChange (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
);
/**
@@ -866,11 +862,11 @@ XhcPeiPollPortStatusChange ( **/
EFI_STATUS
XhcPeiConfigHubContext (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
/**
@@ -887,11 +883,11 @@ XhcPeiConfigHubContext ( **/
EFI_STATUS
XhcPeiConfigHubContext64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
/**
@@ -907,10 +903,10 @@ XhcPeiConfigHubContext64 ( **/
EFI_STATUS
XhcPeiSetConfigCmd (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
/**
@@ -926,10 +922,10 @@ XhcPeiSetConfigCmd ( **/
EFI_STATUS
XhcPeiSetConfigCmd64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
/**
@@ -946,9 +942,9 @@ XhcPeiSetConfigCmd64 ( EFI_STATUS
EFIAPI
XhcPeiStopEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -965,9 +961,9 @@ XhcPeiStopEndpoint ( EFI_STATUS
EFIAPI
XhcPeiResetEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -986,10 +982,10 @@ XhcPeiResetEndpoint ( EFI_STATUS
EFIAPI
XhcPeiSetTrDequeuePointer (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
);
/**
@@ -1007,11 +1003,11 @@ XhcPeiSetTrDequeuePointer ( **/
EFI_STATUS
XhcPeiInitializeDeviceSlot (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1029,11 +1025,11 @@ XhcPeiInitializeDeviceSlot ( **/
EFI_STATUS
XhcPeiInitializeDeviceSlot64 (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1048,9 +1044,9 @@ XhcPeiInitializeDeviceSlot64 ( **/
EFI_STATUS
XhcPeiEvaluateContext (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
/**
@@ -1065,9 +1061,9 @@ XhcPeiEvaluateContext ( **/
EFI_STATUS
XhcPeiEvaluateContext64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
/**
@@ -1081,8 +1077,8 @@ XhcPeiEvaluateContext64 ( **/
EFI_STATUS
XhcPeiDisableSlotCmd (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId
);
/**
@@ -1096,8 +1092,8 @@ XhcPeiDisableSlotCmd ( **/
EFI_STATUS
XhcPeiDisableSlotCmd64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId
);
/**
@@ -1116,8 +1112,8 @@ XhcPeiDisableSlotCmd64 ( **/
EFI_STATUS
XhcPeiRecoverHaltedEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
);
/**
@@ -1135,8 +1131,8 @@ XhcPeiRecoverHaltedEndpoint ( **/
EFI_STATUS
XhcPeiDequeueTrbFromEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
);
/**
@@ -1157,19 +1153,19 @@ XhcPeiDequeueTrbFromEndpoint ( @return Created URB or NULL
**/
-URB*
+URB *
XhcPeiCreateUrb (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
);
/**
@@ -1181,8 +1177,8 @@ XhcPeiCreateUrb ( **/
VOID
XhcPeiFreeUrb (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
);
/**
@@ -1196,8 +1192,8 @@ XhcPeiFreeUrb ( **/
EFI_STATUS
XhcPeiCreateTransferTrb (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
);
/**
@@ -1225,9 +1221,9 @@ XhcPeiSyncTrsRing ( **/
VOID
XhcPeiCreateTransferRing (
- IN PEI_XHC_DEV *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN PEI_XHC_DEV *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
);
/**
@@ -1243,9 +1239,9 @@ XhcPeiCreateTransferRing ( **/
EFI_STATUS
XhcPeiCheckNewEvent (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
);
/**
@@ -1259,8 +1255,8 @@ XhcPeiCheckNewEvent ( **/
EFI_STATUS
XhcPeiSyncEventRing (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EvtRing
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EvtRing
);
/**
@@ -1272,8 +1268,8 @@ XhcPeiSyncEventRing ( **/
VOID
XhcPeiCreateEventRing (
- IN PEI_XHC_DEV *Xhc,
- OUT EVENT_RING *EventRing
+ IN PEI_XHC_DEV *Xhc,
+ OUT EVENT_RING *EventRing
);
/**
@@ -1284,7 +1280,7 @@ XhcPeiCreateEventRing ( **/
VOID
XhcPeiInitSched (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
);
/**
@@ -1295,7 +1291,7 @@ XhcPeiInitSched ( **/
VOID
XhcPeiFreeSched (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
);
#endif
|