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| author | Feng Tian <feng.tian@intel.com> | 2016-09-14 09:36:11 +0800 |
|---|---|---|
| committer | Feng Tian <feng.tian@intel.com> | 2016-09-21 12:42:05 +0800 |
| commit | dbe10619bc443215477c5c0c4c949410bf68b1ec (patch) | |
| tree | 16daf03be2f75e5e30622fb81862ed9d9af75b70 /MdeModulePkg/Bus | |
| parent | 7419aedd93132f2dfc91e7bf3634fba7e0842c7b (diff) | |
| download | edk2-dbe10619bc443215477c5c0c4c949410bf68b1ec.tar.gz edk2-dbe10619bc443215477c5c0c4c949410bf68b1ec.tar.bz2 edk2-dbe10619bc443215477c5c0c4c949410bf68b1ec.zip | |
MdeModulePkg/XhciDxe:1ms delay before access MMIO reg during reset
Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.
As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index d0f22050ad..0e1c86cc16 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -2,7 +2,7 @@ The XHCI register operation routines.
-Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -687,6 +687,12 @@ XhcResetHC ( if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
+ //
+ // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
+ // Otherwise there may have the timeout case happened.
+ // The below is a workaround to solve such problem.
+ //
+ gBS->Stall (XHC_1_MILLISECOND);
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
}
|