summaryrefslogtreecommitdiffstats
path: root/MdeModulePkg/Core/PiSmmCore
diff options
context:
space:
mode:
authorJian J Wang <jian.j.wang@intel.com>2018-01-15 10:21:08 +0800
committerRuiyu Ni <ruiyu.ni@intel.com>2018-01-18 17:03:25 +0800
commit94c0129d244f91fa0a7b122414872da49a35f853 (patch)
treeee2415ecebc2c71685e57de42a1c2d3151b0e38b /MdeModulePkg/Core/PiSmmCore
parentd4d87596c11d6e3f8220b6d9677797c802af3a33 (diff)
downloadedk2-94c0129d244f91fa0a7b122414872da49a35f853.tar.gz
edk2-94c0129d244f91fa0a7b122414872da49a35f853.tar.bz2
edk2-94c0129d244f91fa0a7b122414872da49a35f853.zip
MdeModulePkg/PiSmmCore: remove NX attr for SMM RAM
If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiReservedMemoryType, the BIOS will hang at a page fault exception during starting SMM driver. The root cause is that SMM RAM is type of EfiReservedMemoryType and marked as non-executable. The fix is simply removing NX attribute for those memory. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'MdeModulePkg/Core/PiSmmCore')
-rw-r--r--MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c18
1 files changed, 16 insertions, 2 deletions
diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
index a7663ca291..94d671bd74 100644
--- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
+++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
@@ -1550,6 +1550,7 @@ SmmIplEntry (
EFI_CPU_ARCH_PROTOCOL *CpuArch;
EFI_STATUS SetAttrStatus;
EFI_SMRAM_DESCRIPTOR *SmramRangeSmmDriver;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc;
//
// Fill in the image handle of the SMM IPL so the SMM Core can use this as the
@@ -1616,7 +1617,8 @@ SmmIplEntry (
GetSmramCacheRange (mCurrentSmramRange, &mSmramCacheBase, &mSmramCacheSize);
//
- // If CPU AP is present, attempt to set SMRAM cacheability to WB
+ // If CPU AP is present, attempt to set SMRAM cacheability to WB and clear
+ // XP if it's set.
// Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP
// is not available here.
//
@@ -1630,7 +1632,19 @@ SmmIplEntry (
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "SMM IPL failed to set SMRAM window to EFI_MEMORY_WB\n"));
- }
+ }
+
+ Status = gDS->GetMemorySpaceDescriptor(
+ mCurrentSmramRange->PhysicalStart,
+ &MemDesc
+ );
+ if (!EFI_ERROR (Status) && (MemDesc.Attributes & EFI_MEMORY_XP) != 0) {
+ gDS->SetMemorySpaceAttributes (
+ mCurrentSmramRange->PhysicalStart,
+ mCurrentSmramRange->PhysicalSize,
+ MemDesc.Attributes & (~EFI_MEMORY_XP)
+ );
+ }
}
//
// if Loading module at Fixed Address feature is enabled, save the SMRAM base to Load