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| author | Star Zeng <star.zeng@intel.com> | 2018-06-27 14:10:45 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-07-02 16:38:13 +0800 |
| commit | aa4240edff41034d709938a15b42cf4fd3214386 (patch) | |
| tree | cbb4e9f78c100f523311d14201193430bcfe5198 /MdeModulePkg | |
| parent | e9f4a2a934b1d6a0b9a0747f6858c005126d5ae9 (diff) | |
| download | edk2-aa4240edff41034d709938a15b42cf4fd3214386.tar.gz edk2-aa4240edff41034d709938a15b42cf4fd3214386.tar.bz2 edk2-aa4240edff41034d709938a15b42cf4fd3214386.zip | |
MdeModulePkg SataControllerDxe: Calculate ChannelCount based on PI value
Current code calculates ChannelCount based on CAP(NP) value.
It only works when the ports implemented number are <= CAP(NP),
for example, platform has CAP(NP) = 5 (means 6 ports) and ports
implemented are 0, 1, 2, 3, 4 and 5.
But we have some platform that has CAP(NP) = 1 (means 2 ports) and
ports implemented are 1 and 2, and has no port 0 implemented, then
current code does not work.
This patch updates the code to calculate ChannelCount based on PI value.
Cc: Amy Chan <amy.chan@intel.com>
Cc: Hong-chihX Hsueh <hong-chihx.hsueh@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Tested-by: Hong-chihX Hsueh <hong-chihx.hsueh@intel.com>
Diffstat (limited to 'MdeModulePkg')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c | 28 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h | 1 |
2 files changed, 25 insertions, 4 deletions
diff --git a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c index 7dc40f82e8..d47e918f57 100644 --- a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c +++ b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.c @@ -366,6 +366,7 @@ SataControllerStart ( UINT32 Data32;
UINTN TotalCount;
UINT64 Supports;
+ UINT8 MaxPortNumber;
DEBUG ((EFI_D_INFO, "SataControllerStart start\n"));
@@ -472,12 +473,31 @@ SataControllerStart ( Private->DeviceCount = IDE_MAX_DEVICES;
} else if (IS_PCI_SATADPA (&PciData)) {
//
- // Read Host Capability Register(CAP) to get Number of Ports(NPS) and Supports Port Multiplier(SPM)
- // NPS is 0's based value indicating the maximum number of ports supported by the HBA silicon.
- // A maximum of 32 ports can be supported. A value of '0h', indicating one port, is the minimum requirement.
+ // Read Ports Implemented(PI) to calculate max port number (0 based).
+ //
+ Data32 = AhciReadReg (PciIo, R_AHCI_PI);
+ DEBUG ((DEBUG_INFO, "Ports Implemented(PI) = 0x%x\n", Data32));
+ if (Data32 == 0) {
+ Status = EFI_UNSUPPORTED;
+ goto Done;
+ }
+ MaxPortNumber = 31;
+ while (MaxPortNumber > 0) {
+ if (Data32 & (1 << MaxPortNumber)) {
+ break;
+ }
+ MaxPortNumber--;
+ }
+ //
+ // Make the ChannelCount equal to the max port number (0 based) plus 1.
+ //
+ Private->IdeInit.ChannelCount = MaxPortNumber + 1;
+
+ //
+ // Read HBA Capabilities(CAP) to get Supports Port Multiplier(SPM).
//
Data32 = AhciReadReg (PciIo, R_AHCI_CAP);
- Private->IdeInit.ChannelCount = (UINT8) ((Data32 & B_AHCI_CAP_NPS) + 1);
+ DEBUG ((DEBUG_INFO, "HBA Capabilities(CAP) = 0x%x\n", Data32));
Private->DeviceCount = AHCI_MAX_DEVICES;
if ((Data32 & B_AHCI_CAP_SPM) == B_AHCI_CAP_SPM) {
Private->DeviceCount = AHCI_MULTI_MAX_DEVICES;
diff --git a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h index 436eff2dc6..7ffd3e218a 100644 --- a/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h +++ b/MdeModulePkg/Bus/Pci/SataControllerDxe/SataController.h @@ -44,6 +44,7 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2; #define R_AHCI_CAP 0x0
#define B_AHCI_CAP_NPS (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) // Number of Ports
#define B_AHCI_CAP_SPM BIT17 // Supports Port Multiplier
+#define R_AHCI_PI 0xC
///
/// AHCI each channel can have up to 1 device
|