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| author | Feng Tian <feng.tian@intel.com> | 2016-07-11 11:17:05 +0800 |
|---|---|---|
| committer | Feng Tian <feng.tian@intel.com> | 2016-07-25 09:37:05 +0800 |
| commit | db98a8bdb89afa29b4cedc9ffa29d3fca17e3ac9 (patch) | |
| tree | 05ce8a05c0ebc1ede49f2d59384d72e70a364a8e /MdeModulePkg | |
| parent | bf4808d6443775c9c5170b0ca9c521e6d9c977c1 (diff) | |
| download | edk2-db98a8bdb89afa29b4cedc9ffa29d3fca17e3ac9.tar.gz edk2-db98a8bdb89afa29b4cedc9ffa29d3fca17e3ac9.tar.bz2 edk2-db98a8bdb89afa29b4cedc9ffa29d3fca17e3ac9.zip | |
MdeModulePkg/XhciDxe: fix a bug on TRB check in async int transfer
The last TRB in transfer ring is a LINK type TRB, which shouldn't
be accounted as a valid item in IsAsyncIntTrb().
Without this fix, the original algo will bring issue on those URBs
whose TRBs crosses the transfer ring.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'MdeModulePkg')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 1130b6aac1..b6078b1f09 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -1009,7 +1009,11 @@ IsAsyncIntTrb ( return TRUE;
}
CheckedTrb++;
- if ((UINTN)CheckedTrb >= ((UINTN) CheckedUrb->Ring->RingSeg0 + sizeof (TRB_TEMPLATE) * CheckedUrb->Ring->TrbNumber)) {
+ //
+ // If the checked TRB is the link TRB at the end of the transfer ring,
+ // recircle it to the head of the ring.
+ //
+ if (CheckedTrb->Type == TRB_TYPE_LINK) {
CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0;
}
}
|