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| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:05 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 2f88bd3a1296c522317f1c21377876de63de5be7 (patch) | |
| tree | ba47875489cc5698061275a495983e9dea3be098 /MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h | |
| parent | 1436aea4d5707e672672a11bda72be2c63c936c3 (diff) | |
| download | edk2-2f88bd3a1296c522317f1c21377876de63de5be7.tar.gz edk2-2f88bd3a1296c522317f1c21377876de63de5be7.tar.bz2 edk2-2f88bd3a1296c522317f1c21377876de63de5be7.zip | |
MdePkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the MdePkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h | 37 |
1 files changed, 17 insertions, 20 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h b/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h index 01293ff293..383e3eaf57 100644 --- a/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h +++ b/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h @@ -56,7 +56,7 @@ @endcode
@note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
-#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
+#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
@@ -75,21 +75,20 @@ typedef union { /// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
- UINT32 AESConfiguration:2;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 AESConfiguration : 2;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
-
/**
Thread. Offcore Response Event Select Register (R/W).
@@ -106,8 +105,7 @@ typedef union { @endcode
@note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
-#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
-
+#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
@@ -127,7 +125,7 @@ typedef union { @endcode
@note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
-#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
+#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
@@ -141,41 +139,40 @@ typedef union { /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
- UINT32 Maximum1C:8;
+ UINT32 Maximum1C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
- UINT32 Maximum2C:8;
+ UINT32 Maximum2C : 8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
- UINT32 Maximum3C:8;
+ UINT32 Maximum3C : 8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
- UINT32 Maximum4C:8;
+ UINT32 Maximum4C : 8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5 core active.
///
- UINT32 Maximum5C:8;
+ UINT32 Maximum5C : 8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6 core active.
///
- UINT32 Maximum6C:8;
- UINT32 Reserved:16;
+ UINT32 Maximum6C : 8;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
-
/**
Package. See Table 2-2.
@@ -192,6 +189,6 @@ typedef union { @endcode
@note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
**/
-#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0
+#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0
#endif
|