UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean up

RegisterCpuInterruptHandler did not allow setting
exception handlers for anything beyond the timer IRQ.
Beyond that, it didn't meet the spec around handling
of inputs.

RiscVSupervisorModeTrapHandler now will invoke
set handlers for both exceptions and interrupts.
Two arrays of handlers are maintained - one for exceptions
and one for interrupts.

For unhandled traps, RiscVSupervisorModeTrapHandler dumps
state using the now implemented DumpCpuContext.

For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped
PC address (SEPC), just like on AArch64 (ELR). This is
necessary for X86EmulatorPkg to work as it allows a trap
handler to return execution to a different place. Add
SSTATUS/STVAL as well, at least for debugging purposes. There
is no value in hiding this.

Fix nested exception handling. Handler code should not
be saving SIE (the value is saved in SSTATUS.SPIE) or
directly restored (that's done by SRET). Save and
restore the entire SSTATUS and STVAL, too.

Cc: Daniel Schaefer <git@danielschaefer.me>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>

1 files changed, 30 insertions, 4 deletions

diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 2b0ae2d157..9742663619 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -613,11 +613,34 @@ typedef struct {
 #define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT        7

 #define EXCEPT_RISCV_ENV_CALL_FROM_UMODE           8

 #define EXCEPT_RISCV_ENV_CALL_FROM_SMODE           9

-#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE           10

+#define EXCEPT_RISCV_ENV_CALL_FROM_VS_MODE         10

 #define EXCEPT_RISCV_ENV_CALL_FROM_MMODE           11

-

-#define EXCEPT_RISCV_SOFTWARE_INT  0x0

-#define EXCEPT_RISCV_TIMER_INT     0x1

+#define EXCEPT_RISCV_INST_ACCESS_PAGE_FAULT        12

+#define EXCEPT_RISCV_LOAD_ACCESS_PAGE_FAULT        13

+#define EXCEPT_RISCV_14                            14

+#define EXCEPT_RISCV_STORE_ACCESS_PAGE_FAULT       15

+#define EXCEPT_RISCV_16                            16

+#define EXCEPT_RISCV_17                            17

+#define EXCEPT_RISCV_18                            18

+#define EXCEPT_RISCV_19                            19

+#define EXCEPT_RISCV_INST_GUEST_PAGE_FAULT         20

+#define EXCEPT_RISCV_LOAD_GUEST_PAGE_FAULT         21

+#define EXCEPT_RISCV_VIRTUAL_INSTRUCTION           22

+#define EXCEPT_RISCV_STORE_GUEST_PAGE_FAULT        23

+#define EXCEPT_RISCV_MAX_EXCEPTIONS                (EXCEPT_RISCV_STORE_GUEST_PAGE_FAULT)

+

+///

+/// RISC-V processor exception types for interrupts.

+///

+#define EXCEPT_RISCV_IS_IRQ(x)     ((x & 0x8000000000000000UL) != 0)

+#define EXCEPT_RISCV_IRQ_INDEX(x)  (x & 0x7FFFFFFFFFFFFFFFUL)

+#define EXCEPT_RISCV_IRQ_0                 0x8000000000000000UL

+#define EXCEPT_RISCV_IRQ_SOFT_FROM_SMODE   0x8000000000000001UL

+#define EXCEPT_RISCV_IRQ_SOFT_FROM_VSMODE  0x8000000000000002UL

+#define EXCEPT_RISCV_IRQ_SOFT_FROM_MMODE   0x8000000000000003UL

+#define EXCEPT_RISCV_IRQ_4                 0x8000000000000004UL

+#define EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE  0x8000000000000005UL

+#define EXCEPT_RISCV_MAX_IRQS              (EXCEPT_RISCV_IRQ_INDEX(EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE))

 

 typedef struct {

   UINT64    X0;

@@ -652,6 +675,9 @@ typedef struct {
   UINT64    X29;

   UINT64    X30;

   UINT64    X31;

+  UINT64    SEPC;

+  UINT32    SSTATUS;

+  UINT32    STVAL;

 } EFI_SYSTEM_CONTEXT_RISCV64;

 

 //