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| author | Abner Chang <abner.chang@hpe.com> | 2020-04-07 15:59:20 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-05-07 03:17:15 +0000 |
| commit | 3fd8800954b589cf69e31686f8a6ba6bf200ca3f (patch) | |
| tree | c70ddaf79b71e591cd396408fcbe4ff872bdb141 /MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | |
| parent | 54a3d5ec48e05ae5e5b003d69b1ea55bc09188a9 (diff) | |
| download | edk2-3fd8800954b589cf69e31686f8a6ba6bf200ca3f.tar.gz edk2-3fd8800954b589cf69e31686f8a6ba6bf200ca3f.tar.bz2 edk2-3fd8800954b589cf69e31686f8a6ba6bf200ca3f.zip | |
MdePkg/BaseCpuLib: RISC-V Base CPU library
implementation.
Implement RISC-V CPU related functions in BaseCpuLib.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Diffstat (limited to 'MdePkg/Library/BaseCpuLib/RiscV/Cpu.S')
| -rw-r--r-- | MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S new file mode 100644 index 0000000000..375b91d314 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------------
+//
+// CpuSleep for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+.data
+.align 3
+.section .text
+
+.global ASM_PFX(_CpuSleep)
+
+ASM_PFX(_CpuSleep):
+ wfi
+ ret
+
+
|