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author | Liming Gao <liming.gao@intel.com> | 2018-06-04 13:26:22 +0800 |
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committer | Liming Gao <liming.gao@intel.com> | 2018-06-07 15:26:27 +0800 |
commit | 13688930ae9ad5101f10d28f650382058e449616 (patch) | |
tree | 5c92889eecac2dfe02d0580ea8cbc100eecebdb8 /MdePkg/Library/BaseLib/Ia32/EnableCache.asm | |
parent | b20085454e91bb1ded87009722c9994b4684472c (diff) | |
download | edk2-13688930ae9ad5101f10d28f650382058e449616.tar.gz edk2-13688930ae9ad5101f10d28f650382058e449616.tar.bz2 edk2-13688930ae9ad5101f10d28f650382058e449616.zip |
MdePkg: Remove X86 ASM and S files
NASM has replaced ASM and S files.
1. Remove ASM from all modules.
2. Remove S files from the drivers only.
3. https://bugzilla.tianocore.org/show_bug.cgi?id=881
After NASM is updated, S files can be removed from Library.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Diffstat (limited to 'MdePkg/Library/BaseLib/Ia32/EnableCache.asm')
-rw-r--r-- | MdePkg/Library/BaseLib/Ia32/EnableCache.asm | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.asm b/MdePkg/Library/BaseLib/Ia32/EnableCache.asm deleted file mode 100644 index 238431c071..0000000000 --- a/MdePkg/Library/BaseLib/Ia32/EnableCache.asm +++ /dev/null @@ -1,45 +0,0 @@ -;------------------------------------------------------------------------------
-;
-; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-; This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php.
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-; Module Name:
-;
-; EnableCache.Asm
-;
-; Abstract:
-;
-; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
-; the NW bit of CR0 to 0
-;
-; Notes:
-;
-;------------------------------------------------------------------------------
-
- .486p
- .model flat,C
- .code
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; AsmEnableCache (
-; VOID
-; );
-;------------------------------------------------------------------------------
-AsmEnableCache PROC
- wbinvd
- mov eax, cr0
- btr eax, 29
- btr eax, 30
- mov cr0, eax
- ret
-AsmEnableCache ENDP
-
- END
|