summaryrefslogtreecommitdiffstats
path: root/MdePkg/Library/BaseLib/Ia32/LRotU64.c
diff options
context:
space:
mode:
authorMichael Kinney <michael.d.kinney@intel.com>2015-04-27 19:38:39 +0000
committermdkinney <mdkinney@Edk2>2015-04-27 19:38:39 +0000
commit88a75d260cadc67cc0edf6ad5f57241ed89a7d4b (patch)
tree0684c5232be5941ba6ffd0a3f62cec8e1746bfa0 /MdePkg/Library/BaseLib/Ia32/LRotU64.c
parent881813d7a93d9009c873515b043c41c4554779e4 (diff)
downloadedk2-88a75d260cadc67cc0edf6ad5f57241ed89a7d4b.tar.gz
edk2-88a75d260cadc67cc0edf6ad5f57241ed89a7d4b.tar.bz2
edk2-88a75d260cadc67cc0edf6ad5f57241ed89a7d4b.zip
MdePkg/BaseLib: Support IA32 processors without CMOVx
Remove use of CMOVx instruction from IA32 assembly files in BaseLib. This matches compiler flags for all supported C compilers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17213 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/BaseLib/Ia32/LRotU64.c')
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LRotU64.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/MdePkg/Library/BaseLib/Ia32/LRotU64.c b/MdePkg/Library/BaseLib/Ia32/LRotU64.c
index 1c805aad99..2e01ed8bb0 100644
--- a/MdePkg/Library/BaseLib/Ia32/LRotU64.c
+++ b/MdePkg/Library/BaseLib/Ia32/LRotU64.c
@@ -1,7 +1,7 @@
/** @file
64-bit left rotation for Ia32
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -45,9 +45,11 @@ InternalMathLRotU64 (
ror ebx, cl
shld eax, ebx, cl
test cl, 32 ; Count >= 32?
- cmovnz ecx, eax
- cmovnz eax, edx
- cmovnz edx, ecx
+ jz L0
+ mov ecx, eax
+ mov eax, edx
+ mov edx, ecx
+L0:
}
}