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author | Laszlo Ersek <lersek@redhat.com> | 2018-02-01 22:00:40 +0100 |
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committer | Laszlo Ersek <lersek@redhat.com> | 2018-04-04 16:43:58 +0200 |
commit | 8596c140907ebfeabf62427686280666a4e04893 (patch) | |
tree | ce6325ddc65b0a8187f738cf304abe315c19bb16 /MdePkg/Library/BaseLib/X86PatchInstruction.c | |
parent | de4f7f52f2003b854a754e3815f0a0c1c611118f (diff) | |
download | edk2-8596c140907ebfeabf62427686280666a4e04893.tar.gz edk2-8596c140907ebfeabf62427686280666a4e04893.tar.bz2 edk2-8596c140907ebfeabf62427686280666a4e04893.zip |
MdePkg/BaseLib: add PatchInstructionX86()
Some edk2 modules generate X86 machine code at module execution time by:
- compiling "template" code with NASM at module build time,
- linking the object code into the module,
- and patching the immediate (constant) operands of some instructions when
the module is executed.
Add a helper function to BaseLib so that the C code performing the
patching is easier to read and maintain.
The implementation in this patch is taken mainly from Mike Kinney's
mailing list messages at
<http://mid.mail-archive.com/E92EE9817A31E24EB0585FDF735412F5B895C360@ORSMSX113.amr.corp.intel.com>,
<http://mid.mail-archive.com/E92EE9817A31E24EB0585FDF735412F5B898BF66@ORSMSX112.amr.corp.intel.com>.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'MdePkg/Library/BaseLib/X86PatchInstruction.c')
-rw-r--r-- | MdePkg/Library/BaseLib/X86PatchInstruction.c | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseLib/X86PatchInstruction.c b/MdePkg/Library/BaseLib/X86PatchInstruction.c new file mode 100644 index 0000000000..536d47aa49 --- /dev/null +++ b/MdePkg/Library/BaseLib/X86PatchInstruction.c @@ -0,0 +1,89 @@ +/** @file
+ IA-32/x64 PatchInstructionX86()
+
+ Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (C) 2018, Red Hat, Inc.
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+ word, dword or qword operand is encoded at the end of the instruction's
+ binary representation.
+
+ This function should be used to update object code that was compiled with
+ NASM from assembly source code. Example:
+
+ NASM source code:
+
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched
+ ASM_PFX(gPatchCr3):
+ mov cr3, eax
+
+ C source code:
+
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The
+ immediate operand to patch is expected to
+ comprise the trailing bytes of the instruction.
+ If InstructionEnd is closer to address 0 than
+ ValueSize permits, then ASSERT().
+
+ @param[in] PatchValue The constant to write to the immediate operand.
+ The caller is responsible for ensuring that
+ PatchValue can be represented in the byte, word,
+ dword or qword operand (as indicated through
+ ValueSize); otherwise ASSERT().
+
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
+ 4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+PatchInstructionX86 (
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
+ )
+{
+ //
+ // The equality ((UINTN)InstructionEnd == ValueSize) would assume a zero-size
+ // instruction at address 0; forbid it.
+ //
+ ASSERT ((UINTN)InstructionEnd > ValueSize);
+
+ switch (ValueSize) {
+ case 1:
+ ASSERT (PatchValue <= MAX_UINT8);
+ *((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;
+ break;
+
+ case 2:
+ ASSERT (PatchValue <= MAX_UINT16);
+ WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);
+ break;
+
+ case 4:
+ ASSERT (PatchValue <= MAX_UINT32);
+ WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);
+ break;
+
+ case 8:
+ WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);
+ break;
+
+ default:
+ ASSERT (FALSE);
+ }
+}
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