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authorvanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524>2008-07-09 07:21:21 +0000
committervanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524>2008-07-09 07:21:21 +0000
commit5c57f3eaeae2f917891f969ea9509216cf1f6cad (patch)
tree4dee88a505c7bbc2b6c27dc50d126cd4bb36d191 /MdePkg/Library/BasePciExpressLib
parentcbc1082c98f060a07f6d4b6043daa535b9d8f85f (diff)
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1. Update files header.
2. Added missing libraries in inf files. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@5431 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/BasePciExpressLib')
-rw-r--r--MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf6
-rw-r--r--MdePkg/Library/BasePciExpressLib/PciLib.c2
2 files changed, 3 insertions, 5 deletions
diff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
index 0a6e51a6ee..a067844ef3 100644
--- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
@@ -1,9 +1,9 @@
#/** @file
-# Component description file for Base PCI Express Library.
+# This driver implements one PCI Express Library instance.
#
# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
# PCI Configuration cycles. Layers on top of an I/O Library instance.
-# Copyright (c) 2007, Intel Corporation.
+# Copyright (c) 2007 - 2008, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -35,8 +35,8 @@
[Packages]
MdePkg/MdePkg.dec
-
[LibraryClasses]
+ BaseLib
PcdLib
DebugLib
IoLib
diff --git a/MdePkg/Library/BasePciExpressLib/PciLib.c b/MdePkg/Library/BasePciExpressLib/PciLib.c
index 37d8bcd3b5..6bce8f9550 100644
--- a/MdePkg/Library/BasePciExpressLib/PciLib.c
+++ b/MdePkg/Library/BasePciExpressLib/PciLib.c
@@ -1,6 +1,4 @@
/** @file
- PCI Library.
-
Functions in this library instance make use of MMIO functions in IoLib to
access memory mapped PCI configuration space.