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author | mdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524> | 2008-11-24 08:34:06 +0000 |
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committer | mdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524> | 2008-11-24 08:34:06 +0000 |
commit | 3e3ae6345709da38e9a26dffb83a47cc47d7b0e5 (patch) | |
tree | c78f28eb59f0d3e51e3de330d0294984830bb87f /MdePkg/Library/PeiPciSegmentLibPciCfg2 | |
parent | 0a559bb9b2a6d2834f13a5eefd02289d9e10f2c1 (diff) | |
download | edk2-3e3ae6345709da38e9a26dffb83a47cc47d7b0e5.tar.gz edk2-3e3ae6345709da38e9a26dffb83a47cc47d7b0e5.tar.bz2 edk2-3e3ae6345709da38e9a26dffb83a47cc47d7b0e5.zip |
Add runtime registration function to all PCI Libs
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6708 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/PeiPciSegmentLibPciCfg2')
-rw-r--r-- | MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c index 54ff1cbe65..453f2ded0f 100644 --- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c +++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c @@ -160,6 +160,33 @@ PeiPciSegmentLibPciCfg2WriteWorker ( }
/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ return RETURN_UNSUPPORTED;
+}
+
+/**
Reads an 8-bit PCI configuration register.
Reads and returns the 8-bit PCI configuration register specified by Address.
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