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| author | Antoine Coeur <coeur@gmx.fr> | 2020-02-07 02:07:39 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-02-10 22:30:07 +0000 |
| commit | fae43d06dd83d4af35d9d0bd261ab212a2b8b17e (patch) | |
| tree | 8c5d8cffccce151c3c44c9595dc012154d311147 /MdePkg/Library/SmmPciLibPciRootBridgeIo | |
| parent | a8ecf980c01bbab3f94bb40bf88a174ec655b687 (diff) | |
| download | edk2-fae43d06dd83d4af35d9d0bd261ab212a2b8b17e.tar.gz edk2-fae43d06dd83d4af35d9d0bd261ab212a2b8b17e.tar.bz2 edk2-fae43d06dd83d4af35d9d0bd261ab212a2b8b17e.zip | |
MdePkg/Library/Smm: Fix various typos
Fix various typos in comments and documentation.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Antoine Coeur <coeur@gmx.fr>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com>
Message-Id: <20200207010831.9046-27-philmd@redhat.com>
Diffstat (limited to 'MdePkg/Library/SmmPciLibPciRootBridgeIo')
| -rw-r--r-- | MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c index c9660f48d7..49ea99ce1f 100644 --- a/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c +++ b/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c @@ -35,7 +35,7 @@ ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
//
-// Global varible to cache pointer to PCI Root Bridge I/O protocol.
+// Global variable to cache pointer to PCI Root Bridge I/O protocol.
//
EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL *mSmmPciRootBridgeIo = NULL;
@@ -1238,7 +1238,7 @@ PciBitFieldAndThenOr32 ( Size into the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be read. Size is
returned. When possible 32-bit PCI configuration read cycles are used to read
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
@@ -1336,7 +1336,7 @@ PciReadBuffer ( Size from the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be written. Size is
returned. When possible 32-bit PCI configuration write cycles are used to
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.
|