Refine new library instances according to review comments.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6692 6f19259b-4bc3-4df7-8a09-765794883524

13 files changed, 77 insertions, 77 deletions

diff --git a/MdePkg/Library/DxePciLibPciRootBridgeIo/DxePciLibPciRootBridgeIo.inf b/MdePkg/Library/DxePciLibPciRootBridgeIo/DxePciLibPciRootBridgeIo.inf
index 31df9a80f9..9c6f35d9dd 100644
--- a/MdePkg/Library/DxePciLibPciRootBridgeIo/DxePciLibPciRootBridgeIo.inf
+++ b/MdePkg/Library/DxePciLibPciRootBridgeIo/DxePciLibPciRootBridgeIo.inf
@@ -1,5 +1,5 @@
 # @file

-# Component description file for PCI Lib using PCI Root Bridge I/O Protocol

+# PCI Library that layers on top of the PCI Root Bridge I/O Protocol.

 #

 # This library produces the APIs from the PCI Library and implements these APIs

 #  by calling into the PCI Root Bridge I/O Protocol. The PCI Root Bridge I/O Protocol is

@@ -7,7 +7,7 @@
 #  This library binds to the first PCI Root Bridge I/O Protocol in the platform. As a result,

 #  it should only be used on platforms that contain a single PCI root bridge.

 #

-# Copyright (c) 2007, Intel Corporation.

+# Copyright (c) 2007 - 2008, Intel Corporation.

 #

 #  All rights reserved. This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

diff --git a/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c
index 3c690aa70a..a408b0a0f1 100644
--- a/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c
+++ b/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c
@@ -34,14 +34,14 @@
   ASSERT (((A) & (~0xfffffff | (M))) == 0)

 

 /**

-  Translate PCI Lib address into format of PCI CFG2 PPI.

+  Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.

 

   @param  A  Address that encodes the PCI Bus, Device, Function and

              Register.

 

 **/

-#define PCI_TO_PCICFG2_ADDRESS(A) \

-  (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)

+#define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \

+  ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))

 

 //

 // Global varible to cache pointer to PCI Root Bridge I/O protocol.

@@ -101,7 +101,7 @@ DxePciLibPciRootBridgeIoReadWorker (
   mPciRootBridgeIo->Pci.Read (

                           mPciRootBridgeIo,

                           Width,

-                          PCI_TO_PCICFG2_ADDRESS (Address),

+                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),

                           1,

                           &Data

                           );

@@ -135,7 +135,7 @@ DxePciLibPciRootBridgeIoWriteWorker (
   mPciRootBridgeIo->Pci.Write (

                           mPciRootBridgeIo,

                           Width,

-                          PCI_TO_PCICFG2_ADDRESS (Address),

+                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),

                           1,

                           &Data

                           );

@@ -1228,7 +1228,7 @@ PciReadBuffer (
   UINTN                             ReturnValue;

 

   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);

-  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);

+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);

 

   if (Size == 0) {

     return Size;

@@ -1241,7 +1241,7 @@ PciReadBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Read a byte if StartAddress is byte aligned

     //

@@ -1251,7 +1251,7 @@ PciReadBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Read a word if StartAddress is word aligned

     //

@@ -1326,7 +1326,7 @@ PciWriteBuffer (
   UINTN                             ReturnValue;

 

   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);

-  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);

+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);

 

   if (Size == 0) {

     return 0;

@@ -1339,7 +1339,7 @@ PciWriteBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Write a byte if StartAddress is byte aligned

     //

@@ -1349,7 +1349,7 @@ PciWriteBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Write a word if StartAddress is word aligned

     //

diff --git a/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/DxePciSegmentLibPciRootBridgeIo.inf b/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/DxePciSegmentLibPciRootBridgeIo.inf
index f30247b38d..abb442f8f6 100644
--- a/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/DxePciSegmentLibPciRootBridgeIo.inf
+++ b/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/DxePciSegmentLibPciRootBridgeIo.inf
@@ -1,5 +1,5 @@
 # @file

-# Component description file for PCI Segment Lib using PCI Root Bridge I/O Protocol

+# PCI Segment Library that layers on top of the PCI Root Bridge I/O Protocol.

 #

 # This library produces the APIs from the PCI Library and implements these APIs

 #  by calling into the PCI Root Bridge I/O Protocols that are present in the platform.

@@ -7,7 +7,7 @@
 #  This library binds to all of the PCI Root Bridge I/O Protocols in the platform and handles

 #  the translation from a PCI segment number into a specific PCI Root Bridge I/O Protocol.

 #

-# Copyright (c) 2007, Intel Corporation.

+# Copyright (c) 2007 - 2008, Intel Corporation.

 #

 #  All rights reserved. This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

diff --git a/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.c
index 705ec526bd..058d2debc6 100644
--- a/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.c
+++ b/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.c
@@ -1,5 +1,5 @@
 /** @file

-  Functions accessing PCI configuration registers on any supported PCI segment

+  PCI Segment Library implementation using PCI Root Bridge I/O Protocol.

 

   Copyright (c) 2007 - 2008, Intel Corporation All rights

   reserved. This program and the accompanying materials are

@@ -96,8 +96,7 @@ PciSegmentLibConstructor (
     ASSERT (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR);

   }

 

-  Status = gBS->FreePool(HandleBuffer);

-  ASSERT_EFI_ERROR (Status);

+  FreePool(HandleBuffer);

 

   return EFI_SUCCESS;

 }

@@ -194,7 +193,7 @@ DxePciSegmentLibPciRootBridgeIoReadWorker (
   PciRootBridgeIo->Pci.Read (

                          PciRootBridgeIo,

                          Width,

-                         PCI_TO_PCICFG2_ADDRESS (Address),

+                         PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),

                          1,

                          &Data

                          );

@@ -233,7 +232,7 @@ DxePciSegmentLibPciRootBridgeIoWriteWorker (
   PciRootBridgeIo->Pci.Write (

                          PciRootBridgeIo,

                          Width,

-                         PCI_TO_PCICFG2_ADDRESS (Address),

+                         PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),

                          1,

                          &Data

                          );

@@ -1288,7 +1287,7 @@ PciSegmentBitFieldAndThenOr32 (
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().

   If Size > 0 and Buffer is NULL, then ASSERT().

 

-  @param  StartAddress  Starting Address that encodes the PCI Segment, Bus, Device,

+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,

                         Function and Register.

   @param  Size          Size in bytes of the transfer.

   @param  Buffer        Pointer to a buffer receiving the data read.

@@ -1320,7 +1319,7 @@ PciSegmentReadBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Read a byte if StartAddress is byte aligned

     //

@@ -1330,7 +1329,7 @@ PciSegmentReadBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Read a word if StartAddress is word aligned

     //

@@ -1386,7 +1385,7 @@ PciSegmentReadBuffer (
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().

   If Size > 0 and Buffer is NULL, then ASSERT().

 

-  @param  StartAddress  Starting Address that encodes the PCI Segment, Bus, Device,

+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,

                         Function and Register.

   @param  Size          Size in bytes of the transfer.

   @param  Buffer        Pointer to a buffer containing the data to write.

@@ -1418,7 +1417,7 @@ PciSegmentWriteBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Write a byte if StartAddress is byte aligned

     //

@@ -1428,7 +1427,7 @@ PciSegmentWriteBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Write a word if StartAddress is word aligned

     //

diff --git a/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.h b/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.h
index 2ed7dfe0a8..00129edea6 100644
--- a/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.h
+++ b/MdePkg/Library/DxePciSegmentLibPciRootBridgeIo/PciSegmentLib.h
@@ -47,13 +47,13 @@ typedef struct {
   ASSERT (((A) & (0xf0000000 | (M))) == 0)

 

 /**

-  Translate PCI Lib address into format of PCI CFG2 PPI.

+  Translate PCI Lib address into format of PCI Root Bridge I/O Protocol

 

   @param  A  Address that encodes the PCI Bus, Device, Function and

              Register.

 

 **/

-#define PCI_TO_PCICFG2_ADDRESS(A) \

-  (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)

+#define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \

+  ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))

 

 #endif

diff --git a/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c b/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
index d3d96790c5..63b1b9fc17 100644
--- a/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
+++ b/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
@@ -42,7 +42,7 @@
 

 **/

 #define PCI_TO_PCICFG2_ADDRESS(A) \

-  (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)

+  ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))

 

 /**

   Internal worker function to read a PCI configuration register.

@@ -1210,7 +1210,7 @@ PciReadBuffer (
   UINTN                             ReturnValue;

 

   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);

-  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);

+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);

 

   if (Size == 0) {

     return Size;

@@ -1223,7 +1223,7 @@ PciReadBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Read a byte if StartAddress is byte aligned

     //

@@ -1233,7 +1233,7 @@ PciReadBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Read a word if StartAddress is word aligned

     //

@@ -1308,7 +1308,7 @@ PciWriteBuffer (
   UINTN                             ReturnValue;

 

   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);

-  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);

+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);

 

   if (Size == 0) {

     return 0;

@@ -1321,7 +1321,7 @@ PciWriteBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Write a byte if StartAddress is byte aligned

     //

@@ -1331,7 +1331,7 @@ PciWriteBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Write a word if StartAddress is word aligned

     //

diff --git a/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf b/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
index 3fce912cf7..5abfff9f46 100644
--- a/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
+++ b/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
@@ -1,5 +1,5 @@
 # @file

-# Component description file for PCI Lib using PCI CFG2 PPI

+# PCI Library that layers on top of the PCI CFG2 PPI.

 #

 # This library produces the APIs from the PCI Library and implements

 #  these APIs by calling into the EFI_PEI_PCI CFG2 PPI. One or more EFI_PEI_PCI CFG2

@@ -7,7 +7,7 @@
 #  the first PPI found, so this library instance should only be used platforms

 #  with a single PCI segment.

 #

-# Copyright (c) 2007, Intel Corporation.

+# Copyright (c) 2007 - 2008, Intel Corporation.

 #

 #  All rights reserved. This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -25,7 +25,7 @@
   FILE_GUID                      = FA3AD693-D58A-4619-960B-8EE85C914870

   MODULE_TYPE                    = PEIM

   VERSION_STRING                 = 1.0

-  LIBRARY_CLASS                  = PciLib|PEIM

+  LIBRARY_CLASS                  = PciLib|PEIM SEC PEI_CORE

   EDK_RELEASE_VERSION            = 0x00020000

   EFI_SPECIFICATION_VERSION      = 0x00020000

 

@@ -33,7 +33,7 @@
 #

 # The following information is for reference only and not required by the build tools.

 #

-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC

+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC (EBC is for build only)

 #

 

 [Sources.common]

diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
index 92f0846e29..54ff1cbe65 100644
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
@@ -42,7 +42,7 @@
 

 **/

 #define PCI_TO_PCICFG2_ADDRESS(A) \

-  (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)

+  ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))

 

 /**

   Gets PCI CFG2 PPI.

@@ -1206,7 +1206,7 @@ PciSegmentBitFieldAndThenOr32 (
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().

   If Size > 0 and Buffer is NULL, then ASSERT().

 

-  @param  StartAddress  Starting Address that encodes the PCI Segment, Bus, Device,

+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,

                         Function and Register.

   @param  Size          Size in bytes of the transfer.

   @param  Buffer        Pointer to a buffer receiving the data read.

@@ -1238,7 +1238,7 @@ PciSegmentReadBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Read a byte if StartAddress is byte aligned

     //

@@ -1248,7 +1248,7 @@ PciSegmentReadBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Read a word if StartAddress is word aligned

     //

@@ -1304,7 +1304,7 @@ PciSegmentReadBuffer (
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().

   If Size > 0 and Buffer is NULL, then ASSERT().

 

-  @param  StartAddress  Starting Address that encodes the PCI Segment, Bus, Device,

+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,

                         Function and Register.

   @param  Size          Size in bytes of the transfer.

   @param  Buffer        Pointer to a buffer containing the data to write.

@@ -1336,7 +1336,7 @@ PciSegmentWriteBuffer (
   //

   ReturnValue = Size;

 

-  if ((StartAddress & 1) != 0) {

+  if ((StartAddress & BIT0) != 0) {

     //

     // Write a byte if StartAddress is byte aligned

     //

@@ -1346,7 +1346,7 @@ PciSegmentWriteBuffer (
     Buffer = (UINT8*)Buffer + 1;

   }

 

-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {

+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {

     //

     // Write a word if StartAddress is word aligned

     //

diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
index 85a1231511..938610b045 100644
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
@@ -1,5 +1,5 @@
 # @file

-# This driver implements PCI Segment Lib using PCI CFG2 PPI.

+# PCI Segment Library that layers on top of the PCI CFG2 PPI.

 #

 # This library produces the APIs from the PCI Segment Library and

 #  implements these APIs by calling into the EFI_PEI_PCI CFG2 PPI. One or more

@@ -24,7 +24,7 @@
   FILE_GUID                      = 254901AD-7DB7-45f8-93C8-93D579398D9F

   MODULE_TYPE                    = PEIM

   VERSION_STRING                 = 1.0

-  LIBRARY_CLASS                  = PciSegmentLib|PEIM

+  LIBRARY_CLASS                  = PciLib|PEIM SEC PEI_CORE

   EDK_RELEASE_VERSION            = 0x00020000

   EFI_SPECIFICATION_VERSION      = 0x00020000

 

@@ -32,7 +32,7 @@
 #

 # The following information is for reference only and not required by the build tools.

 #

-#  VALID_ARCHITECTURES           = IA32 X64 IPF

+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC (EBC is for build only)

 #

 

 [Sources.common]

diff --git a/MdePkg/Library/UefiPalLib/UefiPalLib.c b/MdePkg/Library/UefiPalLib/UefiPalLib.c
index e2550387ba..f646fd40f8 100644
--- a/MdePkg/Library/UefiPalLib/UefiPalLib.c
+++ b/MdePkg/Library/UefiPalLib/UefiPalLib.c
@@ -1,5 +1,6 @@
 /** @file

-  PAL Library implementation built upon UEFI.

+  PAL Library implementation retrieving the PAL Entry Point from the SAL System Table

+  register in the EFI System Confguration Table.

 

   Copyright (c) 2007 - 2008, Intel Corporation All rights

   reserved. This program and the accompanying materials are

@@ -41,12 +42,12 @@ UINT64               mPalProcEntry;
   returned or undefined result may occur during the execution of the procedure.

   This function is only available on IPF.

 

-  @param Index - The PAL procedure Index number.

-  @param Arg2  - The 2nd parameter for PAL procedure calls.

-  @param Arg3  - The 3rd parameter for PAL procedure calls.

-  @param Arg4  - The 4th parameter for PAL procedure calls.

+  @param  Index  The PAL procedure Index number.

+  @param  Arg2   The 2nd parameter for PAL procedure calls.

+  @param  Arg3   The 3rd parameter for PAL procedure calls.

+  @param  Arg4   The 4th parameter for PAL procedure calls.

 

-  @return structure returned from the PAL Call procedure, including the status and return value.

+  @return Structure returned from the PAL Call procedure, including the status and return value.

 

 **/

 PAL_CALL_RETURN

@@ -76,7 +77,7 @@ PalCall (
 

   The constructor function looks up the SAL System Table in the EFI System Configuration

   Table. Once the SAL System Table is found, the PAL Entry Point in the SAL System Table

-  will be derived and stored inot a global variable for library usage.

+  will be derived and stored into a global variable for library usage.

   It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System

   Table is not the valid data.

 

@@ -105,9 +106,9 @@ UefiPalLibConstructor (
   ASSERT_EFI_ERROR (Status);

 

   //

-  // Move the SAL System Table point to the first Entry

-  // Due to the SAL Entry is in ascending order with the Entry type,

-  // the type 0 Entry should be the first if exist.

+  // Check the first entry of SAL System Table,

+  // because the SAL entry is in ascending order with the entry type,

+  // the type 0 entry should be the first if exist.

   //

   SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);

 

diff --git a/MdePkg/Library/UefiPalLib/UefiPalLib.inf b/MdePkg/Library/UefiPalLib/UefiPalLib.inf
index ae2a564472..61cf6b0f9a 100644
--- a/MdePkg/Library/UefiPalLib/UefiPalLib.inf
+++ b/MdePkg/Library/UefiPalLib/UefiPalLib.inf
@@ -1,10 +1,10 @@
 # @file

-# Uefi Instance of PAL Library Class

+# UEFI Instance of PAL Library Class.

 #

-# This library implements the PAL Library Class by getting the PAL entry from SAL System

-# Table, and use AsmPalCall to produce the Pal Call.

+# This instance of PAL library retrieves the PAL Entry Point from the SAL System Table

+# register in the EFI System Confguration Table.

 #

-# Copyright (c) 2007, Intel Corporation.

+# Copyright (c) 2007 - 2008, Intel Corporation.

 #

 #  All rights reserved. This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -21,7 +21,7 @@
   BASE_NAME                      = UefiPalLib

   FILE_GUID                      = B7F30170-9E5F-482a-B553-A145A5787003

   MODULE_TYPE                    = UEFI_DRIVER

-  VERSION_STRING                 = 1.04

+  VERSION_STRING                 = 1.0

   LIBRARY_CLASS                  = PalLib|UEFI_DRIVER UEFI_APPLICATION

   EDK_RELEASE_VERSION            = 0x00020000

   EFI_SPECIFICATION_VERSION      = 0x00020000

diff --git a/MdePkg/Library/UefiSalLib/UefiSalLib.c b/MdePkg/Library/UefiSalLib/UefiSalLib.c
index e41cc0d980..f4319ed11c 100644
--- a/MdePkg/Library/UefiSalLib/UefiSalLib.c
+++ b/MdePkg/Library/UefiSalLib/UefiSalLib.c
@@ -1,5 +1,6 @@
 /** @file

-  SAL Library implementation built upon UEFI.

+  SAL Library implementation retrieving the SAL Entry Point from the SAL System Table

+  register in the EFI System Confguration Table.

 

   Copyright (c) 2007 - 2008, Intel Corporation All rights

   reserved. This program and the accompanying materials are

@@ -85,7 +86,7 @@ SalCall (
 

   The constructor function looks up the SAL System Table in the EFI System Configuration

   Table. Once the SAL System Table is found, the SAL Entry Point in the SAL System Table

-  will be derived and stored inot a global variable for library usage.

+  will be derived and stored into a global variable for library usage.

   It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System

   Table is not the valid data.

 

@@ -114,9 +115,9 @@ UefiSalLibConstructor (
   ASSERT_EFI_ERROR (Status);

 

   //

-  // Move the SAL System Table point to the first Entry

-  // Due to the SAL Entry is in ascending order with the Entry type,

-  // the type 0 Entry should be the first if exist.

+  // Check the first entry of SAL System Table,

+  // because the SAL entry is in ascending order with the entry type,

+  // the type 0 entry should be the first if exist.

   //

   SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);

 

@@ -128,7 +129,7 @@ UefiSalLibConstructor (
   mPlabel.EntryPoint = SalStEntryDes->SalProcEntry;

   mPlabel.GP = SalStEntryDes->SalGlobalDataPointer;

   //

-  // Make sure the EntryPoint has the real value

+  // Make sure the EntryPoint has the valid value

   //

   ASSERT ((mPlabel.EntryPoint != 0) && (mPlabel.GP != 0));

 

diff --git a/MdePkg/Library/UefiSalLib/UefiSalLib.inf b/MdePkg/Library/UefiSalLib/UefiSalLib.inf
index 60fe4eae00..54fff89f27 100644
--- a/MdePkg/Library/UefiSalLib/UefiSalLib.inf
+++ b/MdePkg/Library/UefiSalLib/UefiSalLib.inf
@@ -1,10 +1,10 @@
 # @file

-# The library implements the UEFI SAL Library Class.

+# UEFI Instance of SAL Library Class.

 #

-# The library implements the UEFI SAL Library Class.

-#  This library is for boot service only modules.

+# This instance of SAL library retrieves the SAL Entry Point from the SAL System Table

+# register in the EFI System Confguration Table.

 #

-# Copyright (c) 2007, Intel Corporation.

+# Copyright (c) 2007 - 2008, Intel Corporation.

 #

 #  All rights reserved. This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -21,7 +21,7 @@
   BASE_NAME                      = UefiSalLib

   FILE_GUID                      = 4ABCFD77-4A33-4089-B003-5F09BCA940A2

   MODULE_TYPE                    = UEFI_DRIVER

-  VERSION_STRING                 = 1.04

+  VERSION_STRING                 = 1.0

   LIBRARY_CLASS                  = SalLib|UEFI_DRIVER UEFI_APPLICATION

   EDK_RELEASE_VERSION            = 0x00020000

   EFI_SPECIFICATION_VERSION      = 0x00020000

@@ -41,5 +41,4 @@
 

 [LibraryClasses]

   UefiLib

-  BaseLib

   DebugLib