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authorxli24 <xli24@6f19259b-4bc3-4df7-8a09-765794883524>2009-05-14 03:13:31 +0000
committerxli24 <xli24@6f19259b-4bc3-4df7-8a09-765794883524>2009-05-14 03:13:31 +0000
commit59ceeabe504f4c7814f9560c411690a1ffdc31b2 (patch)
tree07838aa3ccbe32341dffa18d8b2f5ecc50ecbda0 /MdePkg/Library
parentc40a1556902e65bf4e998fad0c9a34684e84da10 (diff)
downloadedk2-59ceeabe504f4c7814f9560c411690a1ffdc31b2.tar.gz
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1. Add address check for "RegisterForRuntime" APIs of PciLib, PciCf8Lib, PciExpressLib, and PciSegmentLib.
2. Update ASSERT condition for PciCf8Lib, and PciSegmentLib class. 3. According to MDE Lib Spec, add check for reserved bit field 63..48 for PCI segment address. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8311 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library')
-rw-r--r--MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c4
-rw-r--r--MdePkg/Library/BasePciExpressLib/PciExpressLib.c3
-rw-r--r--MdePkg/Library/PeiPciLibPciCfg2/PciLib.c3
-rw-r--r--MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c15
-rw-r--r--MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c3
-rw-r--r--MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c11
-rw-r--r--MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h6
7 files changed, 26 insertions, 19 deletions
diff --git a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
index a9af173783..f0a23c3605 100644
--- a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
+++ b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
@@ -2,7 +2,7 @@
PCI CF8 Library functions that use I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.
Layers on top of an I/O Library instance.
- Copyright (c) 2006 - 2008, Intel Corporation<BR>
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -68,6 +68,7 @@
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@@ -87,6 +88,7 @@ PciCf8RegisterForRuntimeAccess (
IN UINTN Address
)
{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return RETURN_SUCCESS;
}
diff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
index f74410a565..2220c9a4f9 100644
--- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
+++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
@@ -5,7 +5,7 @@
All assertions for I/O operations are handled in MMIO functions in the IoLib
Library.
- Copyright (c) 2006 - 2008, Intel Corporation<BR>
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -64,6 +64,7 @@ PciExpressRegisterForRuntimeAccess (
IN UINTN Address
)
{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
return RETURN_UNSUPPORTED;
}
diff --git a/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c b/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
index 1406813f43..01306b7b92 100644
--- a/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
+++ b/MdePkg/Library/PeiPciLibPciCfg2/PciLib.c
@@ -1,7 +1,7 @@
/** @file
PCI Library using PCI CFG2 PPI.
- Copyright (c) 2007 - 2008, Intel Corporation All rights
+ Copyright (c) 2007 - 2009, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -155,6 +155,7 @@ PciRegisterForRuntimeAccess (
IN UINTN Address
)
{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return RETURN_UNSUPPORTED;
}
diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
index 6c327e2eb9..332d2a9b45 100644
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
@@ -1,7 +1,7 @@
/** @file
PCI Segment Library implementation using PCI CFG2 PPI.
- Copyright (c) 2007 - 2008, Intel Corporation All rights
+ Copyright (c) 2007 - 2009, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -25,14 +25,14 @@
/**
Assert the validity of a PCI Segment address.
- A valid PCI Segment address should not contain 1's in bits 31:28
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
@param A The address to validate.
@param M Additional bits to assert to be zero.
**/
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
- ASSERT (((A) & (0xf0000000 | (M))) == 0)
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
/**
Translate PCI Lib address into format of PCI CFG2 PPI.
@@ -165,7 +165,7 @@ PeiPciSegmentLibPciCfg2WriteWorker (
Register a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
- If Address > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@@ -185,6 +185,7 @@ PciSegmentRegisterForRuntimeAccess (
IN UINTN Address
)
{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
return RETURN_UNSUPPORTED;
}
@@ -218,7 +219,7 @@ PciSegmentRead8 (
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
- If Address > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@@ -1208,7 +1209,7 @@ PciSegmentBitFieldAndThenOr32 (
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
- If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
@@ -1307,7 +1308,7 @@ PciSegmentReadBuffer (
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.
- If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
diff --git a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
index ff95ec7862..1f23675364 100644
--- a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
+++ b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
@@ -1,7 +1,7 @@
/** @file
PCI Library using PCI Root Bridge I/O Protocol.
- Copyright (c) 2007 - 2008, Intel Corporation All rights
+ Copyright (c) 2007 - 2009, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -169,6 +169,7 @@ PciRegisterForRuntimeAccess (
IN UINTN Address
)
{
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return RETURN_UNSUPPORTED;
}
diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
index beb8b64adf..97fd240a0e 100644
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
@@ -1,7 +1,7 @@
/** @file
PCI Segment Library implementation using PCI Root Bridge I/O Protocol.
- Copyright (c) 2007 - 2008, Intel Corporation All rights
+ Copyright (c) 2007 - 2009, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -244,7 +244,7 @@ DxePciSegmentLibPciRootBridgeIoWriteWorker (
Register a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
- If Address > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@@ -264,6 +264,7 @@ PciSegmentRegisterForRuntimeAccess (
IN UINTN Address
)
{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
return RETURN_UNSUPPORTED;
}
@@ -297,7 +298,7 @@ PciSegmentRead8 (
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
- If Address > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@@ -1287,7 +1288,7 @@ PciSegmentBitFieldAndThenOr32 (
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
- If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
@@ -1385,7 +1386,7 @@ PciSegmentReadBuffer (
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.
- If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h
index ea9fe6665e..2633b6d3c5 100644
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.h
@@ -1,7 +1,7 @@
/** @file
Include file of PciSegmentPciRootBridgeIo Library.
- Copyright (c) 2007 - 2008, Intel Corporation All rights
+ Copyright (c) 2007 - 2009, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -37,14 +37,14 @@ typedef struct {
/**
Assert the validity of a PCI Segment address.
- A valid PCI address should not contain 1's in bits 31:28
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
@param A The address to validate.
@param M Additional bits to assert to be zero.
**/
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
- ASSERT (((A) & (0xf0000000 | (M))) == 0)
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
/**
Translate PCI Lib address into format of PCI Root Bridge I/O Protocol