Add Reserve Interrupt and Exception Vectors definition defined in PI 1.2.1.

Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14882 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 13 insertions, 6 deletions

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index b02cf0b28c..dc7e63b209 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -607,6 +607,9 @@
   ## Include/Guid/FirmwareContentsSigned.h

   gEfiFirmwareContentsSignedGuid    = { 0xf9d89e8, 0x9259, 0x4f76, { 0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf }}

 

+  ## Include/Guid/VectorHandoffTable.h

+  gEfiVectorHandoffTableGuid        = { 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }}

+

 [Guids.IA32, Guids.X64]

   ## Include/Guid/Cper.h

   gEfiIa32X64ErrorTypeCacheCheckGuid = { 0xA55701F5, 0xE3EF, 0x43de, { 0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C }}

@@ -710,6 +713,16 @@
   gEfiTemporaryRamDonePpiGuid        = { 0xceab683c, 0xec56, 0x4a2d, { 0xa9, 0x6, 0x40, 0x53, 0xfa, 0x4e, 0x9c, 0x16 } }

 

   #

+  # PPIs defined in PI 1.2.1.

+  #

+

+  ## Include/Ppi/PiPcdInfo.h

+  gEfiGetPcdInfoPpiGuid              = { 0xa60c6b59, 0xe459, 0x425d, { 0x9c, 0x69,  0xb, 0xcc, 0x9c, 0xb2, 0x7d, 0x81 } }

+

+  ## Include/Ppi/VectorHandoffInfo.h

+  gEfiVectorHandoffInfoPpiGuid       = { 0x3cd652b4, 0x6d33, 0x4dce, { 0x89, 0xdb, 0x83, 0xdf, 0x97, 0x66, 0xfc, 0xca }}

+

+  #

   # PPIs defined in PI 1.3.

   #

   

@@ -720,12 +733,6 @@
   gEfiPeiFirmwareVolumeInfo2PpiGuid  = { 0xea7ca24b, 0xded5, 0x4dad, { 0xa3, 0x89, 0xbf, 0x82, 0x7e, 0x8f, 0x9b, 0x38 } }

 

 

-  #

-  # PPIs defined in PI 1.2.1.

-  #

-

-  ## Include/Ppi/PiPcdInfo.h

-  gEfiGetPcdInfoPpiGuid              = { 0xa60c6b59, 0xe459, 0x425d, { 0x9c, 0x69,  0xb, 0xcc, 0x9c, 0xb2, 0x7d, 0x81 } }

 

 [Protocols]

   ## Include/Protocol/Pcd.h