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| author | Antoine Coeur <coeur@gmx.fr> | 2020-02-07 02:07:41 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-02-10 22:30:07 +0000 |
| commit | 788421d5a766a4ce216e99e2277bb11c54e7d0f6 (patch) | |
| tree | 771f85642208bd79aafbf641d8f02d9d4da50fac /MdePkg | |
| parent | 43516263a833d34ceb68b2d6c2ca2006ae684b36 (diff) | |
| download | edk2-788421d5a766a4ce216e99e2277bb11c54e7d0f6.tar.gz edk2-788421d5a766a4ce216e99e2277bb11c54e7d0f6.tar.bz2 edk2-788421d5a766a4ce216e99e2277bb11c54e7d0f6.zip | |
MdePkg/Register: Fix various typos
Fix various typos in comments and documentation.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Antoine Coeur <coeur@gmx.fr>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com>
Message-Id: <20200207010831.9046-29-philmd@redhat.com>
Diffstat (limited to 'MdePkg')
| -rw-r--r-- | MdePkg/Include/Register/Amd/Cpuid.h | 8 | ||||
| -rw-r--r-- | MdePkg/Include/Register/Amd/Fam17Msr.h | 2 | ||||
| -rw-r--r-- | MdePkg/Include/Register/Amd/Msr.h | 2 | ||||
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h | 2 | ||||
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h | 2 | ||||
| -rw-r--r-- | MdePkg/Include/Register/Intel/StmResourceDescriptor.h | 2 |
6 files changed, 9 insertions, 9 deletions
diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/Amd/Cpuid.h index ad1ba4d016..8e91e84b76 100644 --- a/MdePkg/Include/Register/Amd/Cpuid.h +++ b/MdePkg/Include/Register/Amd/Cpuid.h @@ -11,7 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
- AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
+ AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
**/
@@ -364,7 +364,7 @@ typedef union { ///
UINT32 Page1GB:1;
///
- /// [Bit 27] RDTSCP intructions.
+ /// [Bit 27] RDTSCP instructions.
///
UINT32 RDTSCP:1;
///
@@ -513,9 +513,9 @@ typedef union { @retval EAX Extended APIC ID described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
- @retval EBX Core Indentifiers described by the type
+ @retval EBX Core Identifiers described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
- @retval ECX Node Indentifiers described by the type
+ @retval ECX Node Identifiers described by the type
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
@retval EDX Reserved.
**/
diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h index 37b935dcdb..6ef45a9b21 100644 --- a/MdePkg/Include/Register/Amd/Fam17Msr.h +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
- AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
+ AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
**/
diff --git a/MdePkg/Include/Register/Amd/Msr.h b/MdePkg/Include/Register/Amd/Msr.h index e74de7a1df..084eb892cd 100644 --- a/MdePkg/Include/Register/Amd/Msr.h +++ b/MdePkg/Include/Register/Amd/Msr.h @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
- AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
+ AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
**/
diff --git a/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h b/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h index 2edc1363b7..c56d20df66 100644 --- a/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h @@ -1,5 +1,5 @@ /** @file
- MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.
+ MSR Definitions for Intel Atom processors based on the Goldmont Plus microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
diff --git a/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h b/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h index 30f96f0e82..03cac77c19 100644 --- a/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h @@ -1,5 +1,5 @@ /** @file
- MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
+ MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
diff --git a/MdePkg/Include/Register/Intel/StmResourceDescriptor.h b/MdePkg/Include/Register/Intel/StmResourceDescriptor.h index da4c91d0f4..3e426701e8 100644 --- a/MdePkg/Include/Register/Intel/StmResourceDescriptor.h +++ b/MdePkg/Include/Register/Intel/StmResourceDescriptor.h @@ -179,7 +179,7 @@ typedef struct { } STM_RSC_ALL_RESOURCES_DESC;
/**
- STM Register Volation Descriptor
+ STM Register Violation Descriptor
**/
typedef struct {
STM_RSC_DESC_HEADER Hdr;
|