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| author | Javeed, Ashraf <ashraf.javeed@intel.com> | 2020-03-17 16:04:13 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-03-19 00:48:02 +0000 |
| commit | 1b6b4a83e1d85e48837068dfe409f5557b50d71d (patch) | |
| tree | 0353db7522e0c140a9f94e33ea9302991f0b6d69 /MdePkg | |
| parent | 01ce872739d2f0cd3a8917be2180381db5f0391e (diff) | |
| download | edk2-1b6b4a83e1d85e48837068dfe409f5557b50d71d.tar.gz edk2-1b6b4a83e1d85e48837068dfe409f5557b50d71d.tar.bz2 edk2-1b6b4a83e1d85e48837068dfe409f5557b50d71d.zip | |
MdePkg/PciExpress40.h: DVSEC definition missing
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'MdePkg')
| -rw-r--r-- | MdePkg/Include/IndustryStandard/PciExpress40.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h index 9d9b272546..0564d72861 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress40.h +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard. This header file may not define all structures. Please extend as required.
Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -78,6 +79,33 @@ typedef struct { } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
///@}
+/// The Designated Vendor Specific Capability definitions
+/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
+typedef union {
+ struct {
+ UINT32 DvsecVendorId : 16; //bit 0..15
+ UINT32 DvsecRevision : 4; //bit 16..19
+ UINT32 DvsecLength : 12; //bit 20..31
+ }Bits;
+ UINT32 Uint32;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+ struct {
+ UINT16 DvsecId : 16; //bit 0..15
+ }Bits;
+ UINT16 Uint16;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
+ UINT8 DesignatedVendorSpecific[1];
+}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+///@}
+
#pragma pack()
#endif
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