diff options
| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-08-04 13:02:14 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-08-28 16:47:03 +0800 |
| commit | c9c270193a8f1d64d9664bd191ab57e217206996 (patch) | |
| tree | fd027eab1a8883542c5ef137bcc28a0c3c87913e /MdePkg | |
| parent | ebdde8ff266872632bd6400adcd96d21294e32de (diff) | |
| download | edk2-c9c270193a8f1d64d9664bd191ab57e217206996.tar.gz edk2-c9c270193a8f1d64d9664bd191ab57e217206996.tar.bz2 edk2-c9c270193a8f1d64d9664bd191ab57e217206996.zip | |
MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS
The patch adds new macro PCI_ECAM_ADDRESS into PciExpress21.h,
to align to the PCIE spec, and also update PciExpressLib.h to
redirect PCI_EXPRESS_LIB_ADDRESS to the new macro.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'MdePkg')
| -rw-r--r-- | MdePkg/Include/IndustryStandard/PciExpress21.h | 19 | ||||
| -rw-r--r-- | MdePkg/Include/Library/PciExpressLib.h | 5 |
2 files changed, 20 insertions, 4 deletions
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h index 175c82c88e..ce9c06a7c6 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -1,7 +1,7 @@ /** @file
Support for the latest PCI standard.
- Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -18,6 +18,23 @@ #include <IndustryStandard/Pci30.h>
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
+ of Bus, Device, Function and Register are stripped prior to the generation of
+ the address.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..4095.
+
+ @return The encode ECAM address.
+
+**/
+#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
+ (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
#pragma pack(1)
///
/// PCI Express Capability Structure
diff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Library/PciExpressLib.h index e312d57528..f65b44384f 100644 --- a/MdePkg/Include/Library/PciExpressLib.h +++ b/MdePkg/Include/Library/PciExpressLib.h @@ -5,7 +5,7 @@ configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
is defined by PcdPciExpressBaseAddress.
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -35,8 +35,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. @return The encode PCI address.
**/
-#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
- (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
/**
Registers a PCI device so PCI configuration registers may be accessed after
|