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| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-06 12:52:01 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-06 12:52:01 +0000 |
| commit | 570d030a61101e98e80a05c3b642573b5a1b6c92 (patch) | |
| tree | d6e73384dc73dc14e6634c476e74efd752cd97be /Omap35xxPkg | |
| parent | 284ee2e829ab2453293b7dc4539727ad6c047163 (diff) | |
| download | edk2-570d030a61101e98e80a05c3b642573b5a1b6c92.tar.gz edk2-570d030a61101e98e80a05c3b642573b5a1b6c92.tar.bz2 edk2-570d030a61101e98e80a05c3b642573b5a1b6c92.zip | |
Omap35xxPkg/Omap35xxTimerLib: Create a TimerConstructor in the TimerLib
This constructor should be explicitely called by the Sec or PrePi phase
to initialize the OMAP353x timers.
This function is a copy of the Timer initialization function in BeagleBoardPkg/Sec.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11988 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'Omap35xxPkg')
| -rw-r--r-- | Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c b/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c index efd3d1a223..0b61020805 100644 --- a/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c +++ b/Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c @@ -12,7 +12,7 @@ **/
-#include <Base.h>
+#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/TimerLib.h>
@@ -23,6 +23,37 @@ #include <Omap3530/Omap3530.h>
+RETURN_STATUS
+EFIAPI
+TimerConstructor (
+ VOID
+ )
+{
+ UINTN Timer = PcdGet32(PcdOmap35xxFreeTimer);
+ UINT32 TimerBaseAddress = TimerBase(Timer);
+
+ if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
+ // Set source clock for GPT3 & GPT4 to SYS_CLK
+ MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
+
+ // Set count & reload registers
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
+
+ // Disable interrupts
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
+
+ // Start Timer
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
+
+ // Disable OMAP Watchdog timer (WDT2)
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
+ DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
+ }
+ return EFI_SUCCESS;
+}
+
UINTN
EFIAPI
MicroSecondDelay (
|