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author | Laszlo Ersek <lersek@redhat.com> | 2017-09-19 15:50:39 +0200 |
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committer | Laszlo Ersek <lersek@redhat.com> | 2017-09-20 20:24:26 +0200 |
commit | ba1d245f1d3d40c7d87db57dae76e19cbf289718 (patch) | |
tree | 093105fef1268b4725a81e2deb58ac04c6744761 /OvmfPkg/Include | |
parent | b68c793144e8f239cf59fcc34ee6e35c1fdcd8a6 (diff) | |
download | edk2-ba1d245f1d3d40c7d87db57dae76e19cbf289718.tar.gz edk2-ba1d245f1d3d40c7d87db57dae76e19cbf289718.tar.bz2 edk2-ba1d245f1d3d40c7d87db57dae76e19cbf289718.zip |
OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
* Introduce the PIIX4_PAM* and MCH_PAM* macros under
"OvmfPkg/Include/IndustryStandard". These macros capture the PAM
register offsets (in PCI config space) on the respective Memory
Controller B/D/F, from the respective data sheets.
* Under IndustryStandard, introduce the PMC_REGISTER_PIIX4() macro for
PIIX4. (For Q35, we already have DRAMC_REGISTER_Q35().) In both cases,
the B/D/F is 0/0/0.
* Under CsmSupportLib, replace the "PAMRegOffset" field (UINT8) in the
PAM_REGISTER_VALUE structure with "PAMRegPciLibAddress" (UINTN). The new
field contains the return value of the PCI_LIB_ADDRESS() macro.
* Under CsmSupportLib, replace the "mRegisterValues440" elements as
follows:
REG_PAMx_OFFSET_440, ReadEnableData, WriteEnableData
-->
PMC_REGISTER_PIIX4 (PIIX4_PAMx), ReadEnableData, WriteEnableData
* Under CsmSupportLib, replace the "mRegisterValuesQ35" elements as
follows:
REG_PAMx_OFFSET_Q35, ReadEnableData, WriteEnableData
-->
DRAMC_REGISTER_Q35 (MCH_PAMx), ReadEnableData, WriteEnableData
* Under CsmSupportLib, update the register address calculations as follows
(for all of PciOr8(), PciAnd8() and PciRead8()):
PCI_LIB_ADDRESS (
PAM_PCI_BUS,
PAM_PCI_DEV,
PAM_PCI_FUNC,
mRegisterValues[Index].PAMRegOffset
)
-->
mRegisterValues[Index].PAMRegPciLibAddress
* Under CsmSupportLib, remove the PAM_PCI_* and REG_PAM*_OFFSET_* macros.
Technically speaking, these changes could be split into three patches
(IndustryStandard macro additions, CsmSupportLib code updates,
CsmSupportLib macro removals). However, the patch is not big, and in this
case it is actually helpful to present the code movement / refactoring in
one step, for easier verification.
Cc: Aleksei Kovura <alex3kov@zoho.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugs.launchpad.net/qemu/+bug/1715700
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Aleksei Kovura <alex3kov@zoho.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'OvmfPkg/Include')
-rw-r--r-- | OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 | ||||
-rw-r--r-- | OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 8 |
2 files changed, 21 insertions, 0 deletions
diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h index baa4c063f1..efe6e5c278 100644 --- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h +++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h @@ -28,6 +28,19 @@ #define INTEL_82441_DEVICE_ID 0x1237
//
+// B/D/F/Type: 0/0/0/PCI
+//
+#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
+
+#define PIIX4_PAM0 0x59
+#define PIIX4_PAM1 0x5A
+#define PIIX4_PAM2 0x5B
+#define PIIX4_PAM3 0x5C
+#define PIIX4_PAM4 0x5D
+#define PIIX4_PAM5 0x5E
+#define PIIX4_PAM6 0x5F
+
+//
// B/D/F/Type: 0/1/3/PCI
//
#define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index 68485bec71..193a262e5b 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -47,6 +47,14 @@ #define MCH_PCIEXBAR_HIGH 0x64
#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
+#define MCH_PAM0 0x90
+#define MCH_PAM1 0x91
+#define MCH_PAM2 0x92
+#define MCH_PAM3 0x93
+#define MCH_PAM4 0x94
+#define MCH_PAM5 0x95
+#define MCH_PAM6 0x96
+
#define MCH_SMRAM 0x9D
#define MCH_SMRAM_D_LCK BIT4
#define MCH_SMRAM_G_SMRAME BIT3
|