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authorLaszlo Ersek <lersek@redhat.com>2016-02-02 15:30:27 +0000
committerlersek <lersek@Edk2>2016-02-02 15:30:27 +0000
commitd7c0dfaef26ca1693529360ed6c6de0021e19595 (patch)
tree5f9631dba3fc2c65d8998e81897385f4755b0328 /OvmfPkg/Library/QemuBootOrderLib
parent8ae3832df9985f5285aa59102c94d14ba952844b (diff)
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OvmfPkg: QemuBootOrderLib: recognize NVMe devices
This patch enables QemuBootOrderLib to parse OFW device paths formatted by QEMU commit a907ec52cc1a: nvme: generate OpenFirmware device path in the "bootorder" fw_cfg file With both patches applied, OVMF will honor the bootindex=N property of the NVMe device: -drive id=drive0,if=none,format=FORMAT,file=PATHNAME \ -device nvme,drive=drive0,serial=SERIAL,bootindex=N ^^^^^^^^^^^ Cc: Vladislav Vovchenko <vladislav.vovchenko@sk.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Reference: https://github.com/tianocore/edk2/issues/48 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Vladislav Vovchenko <vladislav.vovchenko@sk.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19792 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'OvmfPkg/Library/QemuBootOrderLib')
-rw-r--r--OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c55
1 files changed, 55 insertions, 0 deletions
diff --git a/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c b/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c
index 43dbaffaa4..15065b7c3d 100644
--- a/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c
+++ b/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c
@@ -931,6 +931,61 @@ TranslatePciOfwNodes (
TargetLun[0],
TargetLun[1]
);
+ } else if (NumNodes >= FirstNonBridge + 2 &&
+ SubstringEq (OfwNode[FirstNonBridge + 0].DriverName, "pci8086,5845") &&
+ SubstringEq (OfwNode[FirstNonBridge + 1].DriverName, "namespace")
+ ) {
+ //
+ // OpenFirmware device path (NVMe device):
+ //
+ // /pci@i0cf8/pci8086,5845@6[,1]/namespace@1,0
+ // ^ ^ ^ ^ ^
+ // | | | | Extended Unique Identifier
+ // | | | | (EUI-64), big endian interp.
+ // | | | namespace ID
+ // | PCI slot & function holding NVMe controller
+ // PCI root at system bus port, PIO
+ //
+ // UEFI device path:
+ //
+ // PciRoot(0x0)/Pci(0x6,0x1)/NVMe(0x1,00-00-00-00-00-00-00-00)
+ // ^ ^
+ // | octets of the EUI-64
+ // | in address order
+ // namespace ID
+ //
+ UINT64 Namespace[2];
+ UINTN RequiredEntries;
+ UINT8 *Eui64;
+
+ RequiredEntries = sizeof (Namespace) / sizeof (Namespace[0]);
+ NumEntries = RequiredEntries;
+ if (ParseUnitAddressHexList (
+ OfwNode[FirstNonBridge + 1].UnitAddress,
+ Namespace,
+ &NumEntries
+ ) != RETURN_SUCCESS ||
+ NumEntries != RequiredEntries ||
+ Namespace[0] == 0 ||
+ Namespace[0] >= MAX_UINT32
+ ) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ Eui64 = (UINT8 *)&Namespace[1];
+ Written = UnicodeSPrintAsciiFormat (
+ Translated,
+ *TranslatedSize * sizeof (*Translated), // BufferSize in bytes
+ "PciRoot(0x%x)%s/Pci(0x%Lx,0x%Lx)/"
+ "NVMe(0x%Lx,%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x)",
+ PciRoot,
+ Bridges,
+ PciDevFun[0],
+ PciDevFun[1],
+ Namespace[0],
+ Eui64[7], Eui64[6], Eui64[5], Eui64[4],
+ Eui64[3], Eui64[2], Eui64[1], Eui64[0]
+ );
} else {
//
// Generic OpenFirmware device path for PCI devices: