OvmfPkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the OvmfPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>

1 files changed, 203 insertions, 151 deletions

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index d736b85e0d..3f59a1ac79 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -39,24 +39,24 @@ Module Name:
 #include "Platform.h"

 #include "Cmos.h"

 

-UINT8 mPhysMemAddressWidth;

+UINT8  mPhysMemAddressWidth;

 

-STATIC UINT32 mS3AcpiReservedMemoryBase;

-STATIC UINT32 mS3AcpiReservedMemorySize;

+STATIC UINT32  mS3AcpiReservedMemoryBase;

+STATIC UINT32  mS3AcpiReservedMemorySize;

 

-STATIC UINT16 mQ35TsegMbytes;

+STATIC UINT16  mQ35TsegMbytes;

 

-BOOLEAN mQ35SmramAtDefaultSmbase;

+BOOLEAN  mQ35SmramAtDefaultSmbase;

 

-UINT32 mQemuUc32Base;

+UINT32  mQemuUc32Base;

 

 VOID

 Q35TsegMbytesInitialization (

   VOID

   )

 {

-  UINT16        ExtendedTsegMbytes;

-  RETURN_STATUS PcdStatus;

+  UINT16         ExtendedTsegMbytes;

+  RETURN_STATUS  PcdStatus;

 

   ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);

 

@@ -94,46 +94,53 @@ Q35TsegMbytesInitialization (
   mQ35TsegMbytes = ExtendedTsegMbytes;

 }

 

-

 VOID

 Q35SmramAtDefaultSmbaseInitialization (

   VOID

   )

 {

-  RETURN_STATUS PcdStatus;

+  RETURN_STATUS  PcdStatus;

 

   ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);

 

   mQ35SmramAtDefaultSmbase = FALSE;

   if (FeaturePcdGet (PcdCsmEnable)) {

-    DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE not checked due to CSM\n",

-      __FUNCTION__));

+    DEBUG ((

+      DEBUG_INFO,

+      "%a: SMRAM at default SMBASE not checked due to CSM\n",

+      __FUNCTION__

+      ));

   } else {

-    UINTN CtlReg;

-    UINT8 CtlRegVal;

+    UINTN  CtlReg;

+    UINT8  CtlRegVal;

 

     CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);

     PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);

-    CtlRegVal = PciRead8 (CtlReg);

+    CtlRegVal                = PciRead8 (CtlReg);

     mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==

                                          MCH_DEFAULT_SMBASE_IN_RAM);

-    DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__,

-      mQ35SmramAtDefaultSmbase ? "found" : "not found"));

+    DEBUG ((

+      DEBUG_INFO,

+      "%a: SMRAM at default SMBASE %a\n",

+      __FUNCTION__,

+      mQ35SmramAtDefaultSmbase ? "found" : "not found"

+      ));

   }

 

-  PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,

-                mQ35SmramAtDefaultSmbase);

+  PcdStatus = PcdSetBoolS (

+                PcdQ35SmramAtDefaultSmbase,

+                mQ35SmramAtDefaultSmbase

+                );

   ASSERT_RETURN_ERROR (PcdStatus);

 }

 

-

 VOID

 QemuUc32BaseInitialization (

   VOID

   )

 {

-  UINT32 LowerMemorySize;

-  UINT32 Uc32Size;

+  UINT32  LowerMemorySize;

+  UINT32  Uc32Size;

 

   if (mHostBridgeDevId == 0xffff /* microvm */) {

     return;

@@ -159,8 +166,8 @@ QemuUc32BaseInitialization (
   // while keeping the end affixed to 4GB. This will round the base up.

   //

   LowerMemorySize = GetSystemMemorySizeBelow4gb ();

-  Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));

-  mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);

+  Uc32Size        = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));

+  mQemuUc32Base   = (UINT32)(SIZE_4GB - Uc32Size);

   //

   // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.

   // Therefore mQemuUc32Base is at least 2GB.

@@ -168,13 +175,18 @@ QemuUc32BaseInitialization (
   ASSERT (mQemuUc32Base >= BASE_2GB);

 

   if (mQemuUc32Base != LowerMemorySize) {

-    DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "

-      "an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, mQemuUc32Base,

-      Uc32Size));

+    DEBUG ((

+      DEBUG_VERBOSE,

+      "%a: rounded UC32 base from 0x%x up to 0x%x, for "

+      "an UC32 size of 0x%x\n",

+      __FUNCTION__,

+      LowerMemorySize,

+      mQemuUc32Base,

+      Uc32Size

+      ));

   }

 }

 

-

 /**

   Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside

   of the 32-bit address range.

@@ -204,19 +216,20 @@ QemuUc32BaseInitialization (
 STATIC

 EFI_STATUS

 ScanOrAdd64BitE820Ram (

-  OUT UINT64 *MaxAddress OPTIONAL

+  OUT UINT64  *MaxAddress OPTIONAL

   )

 {

-  EFI_STATUS           Status;

-  FIRMWARE_CONFIG_ITEM FwCfgItem;

-  UINTN                FwCfgSize;

-  EFI_E820_ENTRY64     E820Entry;

-  UINTN                Processed;

+  EFI_STATUS            Status;

+  FIRMWARE_CONFIG_ITEM  FwCfgItem;

+  UINTN                 FwCfgSize;

+  EFI_E820_ENTRY64      E820Entry;

+  UINTN                 Processed;

 

   Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);

   if (EFI_ERROR (Status)) {

     return Status;

   }

+

   if (FwCfgSize % sizeof E820Entry != 0) {

     return EFI_PROTOCOL_ERROR;

   }

@@ -236,18 +249,19 @@ ScanOrAdd64BitE820Ram (
       E820Entry.Length,

       E820Entry.Type

       ));

-    if (E820Entry.Type == EfiAcpiAddressRangeMemory &&

-        E820Entry.BaseAddr >= BASE_4GB) {

+    if ((E820Entry.Type == EfiAcpiAddressRangeMemory) &&

+        (E820Entry.BaseAddr >= BASE_4GB))

+    {

       if (MaxAddress == NULL) {

-        UINT64 Base;

-        UINT64 End;

+        UINT64  Base;

+        UINT64  End;

 

         //

         // Round up the start address, and round down the end address.

         //

         Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);

-        End = (E820Entry.BaseAddr + E820Entry.Length) &

-              ~(UINT64)EFI_PAGE_MASK;

+        End  = (E820Entry.BaseAddr + E820Entry.Length) &

+               ~(UINT64)EFI_PAGE_MASK;

         if (Base < End) {

           AddMemoryRangeHob (Base, End);

           DEBUG ((

@@ -259,7 +273,7 @@ ScanOrAdd64BitE820Ram (
             ));

         }

       } else {

-        UINT64 Candidate;

+        UINT64  Candidate;

 

         Candidate = E820Entry.BaseAddr + E820Entry.Length;

         if (Candidate > *MaxAddress) {

@@ -274,17 +288,17 @@ ScanOrAdd64BitE820Ram (
       }

     }

   }

+

   return EFI_SUCCESS;

 }

 

-

 UINT32

 GetSystemMemorySizeBelow4gb (

   VOID

   )

 {

-  UINT8 Cmos0x34;

-  UINT8 Cmos0x35;

+  UINT8  Cmos0x34;

+  UINT8  Cmos0x35;

 

   //

   // CMOS 0x34/0x35 specifies the system memory above 16 MB.

@@ -295,20 +309,19 @@ GetSystemMemorySizeBelow4gb (
   //   into the calculation to get the total memory size.

   //

 

-  Cmos0x34 = (UINT8) CmosRead8 (0x34);

-  Cmos0x35 = (UINT8) CmosRead8 (0x35);

+  Cmos0x34 = (UINT8)CmosRead8 (0x34);

+  Cmos0x35 = (UINT8)CmosRead8 (0x35);

 

-  return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);

+  return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);

 }

 

-

 STATIC

 UINT64

 GetSystemMemorySizeAbove4gb (

   )

 {

-  UINT32 Size;

-  UINTN  CmosIndex;

+  UINT32  Size;

+  UINTN   CmosIndex;

 

   //

   // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.

@@ -320,13 +333,12 @@ GetSystemMemorySizeAbove4gb (
 

   Size = 0;

   for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {

-    Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);

+    Size = (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex);

   }

 

   return LShiftU64 (Size, 16);

 }

 

-

 /**

   Return the highest address that DXE could possibly use, plus one.

 **/

@@ -336,14 +348,14 @@ GetFirstNonAddress (
   VOID

   )

 {

-  UINT64               FirstNonAddress;

-  UINT64               Pci64Base, Pci64Size;

-  UINT32               FwCfgPciMmio64Mb;

-  EFI_STATUS           Status;

-  FIRMWARE_CONFIG_ITEM FwCfgItem;

-  UINTN                FwCfgSize;

-  UINT64               HotPlugMemoryEnd;

-  RETURN_STATUS        PcdStatus;

+  UINT64                FirstNonAddress;

+  UINT64                Pci64Base, Pci64Size;

+  UINT32                FwCfgPciMmio64Mb;

+  EFI_STATUS            Status;

+  FIRMWARE_CONFIG_ITEM  FwCfgItem;

+  UINTN                 FwCfgSize;

+  UINT64                HotPlugMemoryEnd;

+  RETURN_STATUS         PcdStatus;

 

   //

   // set FirstNonAddress to suppress incorrect compiler/analyzer warnings

@@ -367,11 +379,12 @@ GetFirstNonAddress (
   // resources to 32-bit anyway. See DegradeResource() in

   // "PciResourceSupport.c".

   //

-#ifdef MDE_CPU_IA32

+ #ifdef MDE_CPU_IA32

   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {

     return FirstNonAddress;

   }

-#endif

+

+ #endif

 

   //

   // Otherwise, in order to calculate the highest address plus one, we must

@@ -386,31 +399,40 @@ GetFirstNonAddress (
   // As signaled by the "X-" prefix, this knob is experimental, and might go

   // away at any time.

   //

-  Status = QemuFwCfgParseUint32 ("opt/ovmf/X-PciMmio64Mb", FALSE,

-             &FwCfgPciMmio64Mb);

+  Status = QemuFwCfgParseUint32 (

+             "opt/ovmf/X-PciMmio64Mb",

+             FALSE,

+             &FwCfgPciMmio64Mb

+             );

   switch (Status) {

-  case EFI_UNSUPPORTED:

-  case EFI_NOT_FOUND:

-    break;

-  case EFI_SUCCESS:

-    if (FwCfgPciMmio64Mb <= 0x1000000) {

-      Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);

+    case EFI_UNSUPPORTED:

+    case EFI_NOT_FOUND:

       break;

-    }

+    case EFI_SUCCESS:

+      if (FwCfgPciMmio64Mb <= 0x1000000) {

+        Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);

+        break;

+      }

+

     //

     // fall through

     //

-  default:

-    DEBUG ((DEBUG_WARN,

-      "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",

-      __FUNCTION__));

-    break;

+    default:

+      DEBUG ((

+        DEBUG_WARN,

+        "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",

+        __FUNCTION__

+        ));

+      break;

   }

 

   if (Pci64Size == 0) {

     if (mBootMode != BOOT_ON_S3_RESUME) {

-      DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",

-        __FUNCTION__));

+      DEBUG ((

+        DEBUG_INFO,

+        "%a: disabling 64-bit PCI host aperture\n",

+        __FUNCTION__

+        ));

       PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);

       ASSERT_RETURN_ERROR (PcdStatus);

     }

@@ -429,13 +451,20 @@ GetFirstNonAddress (
   // starts right at the end of the memory above 4GB. The 64-bit PCI host

   // aperture must be placed above it.

   //

-  Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,

-             &FwCfgSize);

-  if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {

+  Status = QemuFwCfgFindFile (

+             "etc/reserved-memory-end",

+             &FwCfgItem,

+             &FwCfgSize

+             );

+  if (!EFI_ERROR (Status) && (FwCfgSize == sizeof HotPlugMemoryEnd)) {

     QemuFwCfgSelectItem (FwCfgItem);

     QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);

-    DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,

-      HotPlugMemoryEnd));

+    DEBUG ((

+      DEBUG_VERBOSE,

+      "%a: HotPlugMemoryEnd=0x%Lx\n",

+      __FUNCTION__,

+      HotPlugMemoryEnd

+      ));

 

     ASSERT (HotPlugMemoryEnd >= FirstNonAddress);

     FirstNonAddress = HotPlugMemoryEnd;

@@ -467,8 +496,13 @@ GetFirstNonAddress (
     PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);

     ASSERT_RETURN_ERROR (PcdStatus);

 

-    DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",

-      __FUNCTION__, Pci64Base, Pci64Size));

+    DEBUG ((

+      DEBUG_INFO,

+      "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",

+      __FUNCTION__,

+      Pci64Base,

+      Pci64Size

+      ));

   }

 

   //

@@ -478,7 +512,6 @@ GetFirstNonAddress (
   return FirstNonAddress;

 }

 

-

 /**

   Initialize the mPhysMemAddressWidth variable, based on guest RAM size.

 **/

@@ -487,7 +520,7 @@ AddressWidthInitialization (
   VOID

   )

 {

-  UINT64 FirstNonAddress;

+  UINT64  FirstNonAddress;

 

   //

   // As guest-physical memory size grows, the permanent PEI RAM requirements

@@ -515,10 +548,10 @@ AddressWidthInitialization (
   if (mPhysMemAddressWidth <= 36) {

     mPhysMemAddressWidth = 36;

   }

+

   ASSERT (mPhysMemAddressWidth <= 48);

 }

 

-

 /**

   Calculate the cap for the permanent PEI memory.

 **/

@@ -528,21 +561,22 @@ GetPeiMemoryCap (
   VOID

   )

 {

-  BOOLEAN Page1GSupport;

-  UINT32  RegEax;

-  UINT32  RegEdx;

-  UINT32  Pml4Entries;

-  UINT32  PdpEntries;

-  UINTN   TotalPages;

+  BOOLEAN  Page1GSupport;

+  UINT32   RegEax;

+  UINT32   RegEdx;

+  UINT32   Pml4Entries;

+  UINT32   PdpEntries;

+  UINTN    TotalPages;

 

   //

   // If DXE is 32-bit, then just return the traditional 64 MB cap.

   //

-#ifdef MDE_CPU_IA32

+ #ifdef MDE_CPU_IA32

   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {

     return SIZE_64MB;

   }

-#endif

+

+ #endif

 

   //

   // Dependent on physical address width, PEI memory allocations can be

@@ -563,7 +597,7 @@ GetPeiMemoryCap (
 

   if (mPhysMemAddressWidth <= 39) {

     Pml4Entries = 1;

-    PdpEntries = 1 << (mPhysMemAddressWidth - 30);

+    PdpEntries  = 1 << (mPhysMemAddressWidth - 30);

     ASSERT (PdpEntries <= 0x200);

   } else {

     Pml4Entries = 1 << (mPhysMemAddressWidth - 39);

@@ -572,7 +606,7 @@ GetPeiMemoryCap (
   }

 

   TotalPages = Page1GSupport ? Pml4Entries + 1 :

-                               (PdpEntries + 1) * Pml4Entries + 1;

+               (PdpEntries + 1) * Pml4Entries + 1;

   ASSERT (TotalPages <= 0x40201);

 

   //

@@ -583,7 +617,6 @@ GetPeiMemoryCap (
   return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);

 }

 

-

 /**

   Publish PEI core memory

 

@@ -595,11 +628,11 @@ PublishPeiMemory (
   VOID

   )

 {

-  EFI_STATUS                  Status;

-  EFI_PHYSICAL_ADDRESS        MemoryBase;

-  UINT64                      MemorySize;

-  UINT32                      LowerMemorySize;

-  UINT32                      PeiMemoryCap;

+  EFI_STATUS            Status;

+  EFI_PHYSICAL_ADDRESS  MemoryBase;

+  UINT64                MemorySize;

+  UINT32                LowerMemorySize;

+  UINT32                PeiMemoryCap;

 

   LowerMemorySize = GetSystemMemorySizeBelow4gb ();

   if (FeaturePcdGet (PcdSmmSmramRequire)) {

@@ -616,10 +649,10 @@ PublishPeiMemory (
   //

   if (mS3Supported) {

     mS3AcpiReservedMemorySize = SIZE_512KB +

-      mMaxCpuCount *

-      PcdGet32 (PcdCpuApStackSize);

+                                mMaxCpuCount *

+                                PcdGet32 (PcdCpuApStackSize);

     mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;

-    LowerMemorySize = mS3AcpiReservedMemoryBase;

+    LowerMemorySize           = mS3AcpiReservedMemoryBase;

   }

 

   if (mBootMode == BOOT_ON_S3_RESUME) {

@@ -627,8 +660,13 @@ PublishPeiMemory (
     MemorySize = mS3AcpiReservedMemorySize;

   } else {

     PeiMemoryCap = GetPeiMemoryCap ();

-    DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",

-      __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));

+    DEBUG ((

+      DEBUG_INFO,

+      "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",

+      __FUNCTION__,

+      mPhysMemAddressWidth,

+      PeiMemoryCap >> 10

+      ));

 

     //

     // Determine the range of memory to use during PEI

@@ -641,8 +679,8 @@ PublishPeiMemory (
     // shouldn't overlap with that HOB.

     //

     MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?

-      PcdGet32 (PcdOvmfDecompressionScratchEnd) :

-      PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);

+                 PcdGet32 (PcdOvmfDecompressionScratchEnd) :

+                 PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);

     MemorySize = LowerMemorySize - MemoryBase;

     if (MemorySize > PeiMemoryCap) {

       MemoryBase = LowerMemorySize - PeiMemoryCap;

@@ -662,13 +700,12 @@ PublishPeiMemory (
   //

   // Publish this memory to the PEI Core

   //

-  Status = PublishSystemMemory(MemoryBase, MemorySize);

+  Status = PublishSystemMemory (MemoryBase, MemorySize);

   ASSERT_EFI_ERROR (Status);

 

   return Status;

 }

 

-

 STATIC

 VOID

 QemuInitializeRamBelow1gb (

@@ -677,20 +714,24 @@ QemuInitializeRamBelow1gb (
 {

   if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {

     AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);

-    AddReservedMemoryBaseSizeHob (SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE,

-      TRUE /* Cacheable */);

+    AddReservedMemoryBaseSizeHob (

+      SMM_DEFAULT_SMBASE,

+      MCH_DEFAULT_SMBASE_SIZE,

+      TRUE /* Cacheable */

+      );

     STATIC_ASSERT (

       SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,

       "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"

       );

-    AddMemoryRangeHob (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,

-      BASE_512KB + BASE_128KB);

+    AddMemoryRangeHob (

+      SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,

+      BASE_512KB + BASE_128KB

+      );

   } else {

     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);

   }

 }

 

-

 /**

   Peform Memory Detection for QEMU / KVM

 

@@ -701,10 +742,10 @@ QemuInitializeRam (
   VOID

   )

 {

-  UINT64                      LowerMemorySize;

-  UINT64                      UpperMemorySize;

-  MTRR_SETTINGS               MtrrSettings;

-  EFI_STATUS                  Status;

+  UINT64         LowerMemorySize;

+  UINT64         UpperMemorySize;

+  MTRR_SETTINGS  MtrrSettings;

+  EFI_STATUS     Status;

 

   DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));

 

@@ -743,12 +784,15 @@ QemuInitializeRam (
     QemuInitializeRamBelow1gb ();

 

     if (FeaturePcdGet (PcdSmmSmramRequire)) {

-      UINT32 TsegSize;

+      UINT32  TsegSize;

 

       TsegSize = mQ35TsegMbytes * SIZE_1MB;

       AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);

-      AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,

-        TRUE);

+      AddReservedMemoryBaseSizeHob (

+        LowerMemorySize - TsegSize,

+        TsegSize,

+        TRUE

+        );

     } else {

       AddMemoryRangeHob (BASE_1MB, LowerMemorySize);

     }

@@ -759,7 +803,7 @@ QemuInitializeRam (
     // memory size read from the CMOS.

     //

     Status = ScanOrAdd64BitE820Ram (NULL);

-    if (EFI_ERROR (Status) && UpperMemorySize != 0) {

+    if (EFI_ERROR (Status) && (UpperMemorySize != 0)) {

       AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);

     }

   }

@@ -796,16 +840,22 @@ QemuInitializeRam (
     //

     // Set memory range from 640KB to 1MB to uncacheable

     //

-    Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,

-               BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);

+    Status = MtrrSetMemoryAttribute (

+               BASE_512KB + BASE_128KB,

+               BASE_1MB - (BASE_512KB + BASE_128KB),

+               CacheUncacheable

+               );

     ASSERT_EFI_ERROR (Status);

 

     //

     // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI

     // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.

     //

-    Status = MtrrSetMemoryAttribute (mQemuUc32Base, SIZE_4GB - mQemuUc32Base,

-               CacheUncacheable);

+    Status = MtrrSetMemoryAttribute (

+               mQemuUc32Base,

+               SIZE_4GB - mQemuUc32Base,

+               CacheUncacheable

+               );

     ASSERT_EFI_ERROR (Status);

   }

 }

@@ -821,7 +871,7 @@ InitializeRamRegions (
 {

   QemuInitializeRam ();

 

-  if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {

+  if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {

     //

     // This is the memory range that will be used for PEI on S3 resume

     //

@@ -851,7 +901,7 @@ InitializeRamRegions (
       EfiACPIMemoryNVS

       );

 

-#ifdef MDE_CPU_X64

+ #ifdef MDE_CPU_X64

     //

     // Reserve the initial page tables built by the reset vector code.

     //

@@ -859,8 +909,8 @@ InitializeRamRegions (
     // resume, it must be reserved as ACPI NVS.

     //

     BuildMemoryAllocationHob (

-      (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),

-      (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),

+      (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),

+      (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),

       EfiACPIMemoryNVS

       );

 

@@ -875,22 +925,23 @@ InitializeRamRegions (
       // resume, it must be reserved as ACPI NVS.

       //

       BuildMemoryAllocationHob (

-        (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableBase),

-        (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableSize),

+        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase),

+        (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize),

         EfiACPIMemoryNVS

         );

       BuildMemoryAllocationHob (

-        (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBase),

-        (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbSize),

+        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase),

+        (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize),

         EfiACPIMemoryNVS

         );

       BuildMemoryAllocationHob (

-        (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBackupBase),

-        (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbBackupSize),

+        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase),

+        (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize),

         EfiACPIMemoryNVS

         );

     }

-#endif

+

+ #endif

   }

 

   if (mBootMode != BOOT_ON_S3_RESUME) {

@@ -906,18 +957,18 @@ InitializeRamRegions (
       // such that they would overlap the LockBox storage.

       //

       ZeroMem (

-        (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),

-        (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)

+        (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),

+        (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)

         );

       BuildMemoryAllocationHob (

-        (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),

-        (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),

+        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),

+        (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),

         mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData

         );

     }

 

     if (FeaturePcdGet (PcdSmmSmramRequire)) {

-      UINT32 TsegSize;

+      UINT32  TsegSize;

 

       //

       // Make sure the TSEG area that we reported as a reserved memory resource

@@ -925,7 +976,7 @@ InitializeRamRegions (
       //

       TsegSize = mQ35TsegMbytes * SIZE_1MB;

       BuildMemoryAllocationHob (

-        GetSystemMemorySizeBelow4gb() - TsegSize,

+        GetSystemMemorySizeBelow4gb () - TsegSize,

         TsegSize,

         EfiReservedMemoryType

         );

@@ -942,7 +993,7 @@ InitializeRamRegions (
       }

     }

 

-#ifdef MDE_CPU_X64

+ #ifdef MDE_CPU_X64

     if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) {

       //

       // Reserve the work area.

@@ -955,11 +1006,12 @@ InitializeRamRegions (
       // such that they would overlap the work area.

       //

       BuildMemoryAllocationHob (

-        (EFI_PHYSICAL_ADDRESS)(UINTN) FixedPcdGet32 (PcdOvmfWorkAreaBase),

-        (UINT64)(UINTN) FixedPcdGet32 (PcdOvmfWorkAreaSize),

+        (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),

+        (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),

         mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData

         );

     }

-#endif

+

+ #endif

   }

 }