OvmfPkg/PlatformInitLib: Add hob functions

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

In this patch of PlatformInitLib, below hob functions are introduced:
 - PlatformAddIoMemoryBaseSizeHob
 - PlatformAddIoMemoryRangeHob
 - PlatformAddMemoryBaseSizeHob
 - PlatformAddMemoryRangeHob
 - PlatformAddReservedMemoryBaseSizeHob

They correspond the below functions in OvmfPkg/PlatformPei:
 - AddIoMemoryBaseSizeHob
 - AddIoMemoryRangeHob
 - AddMemoryBaseSizeHob
 - AddMemoryRangeHob
 - AddReservedMemoryBaseSizeHob

After above hob functions are introduced in PlatformInitLib,
OvmfPkg/PlatformPei is refactored with this library.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>

3 files changed, 21 insertions, 131 deletions

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 9c5bf240e3..e5e105f377 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -275,10 +275,10 @@ ScanOrAdd64BitE820Ram (
         End  = (E820Entry.BaseAddr + E820Entry.Length) &

                ~(UINT64)EFI_PAGE_MASK;

         if (Base < End) {

-          AddMemoryRangeHob (Base, End);

+          PlatformAddMemoryRangeHob (Base, End);

           DEBUG ((

             DEBUG_VERBOSE,

-            "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",

+            "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",

             __FUNCTION__,

             Base,

             End

@@ -816,8 +816,8 @@ QemuInitializeRamBelow1gb (
   )

 {

   if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {

-    AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);

-    AddReservedMemoryBaseSizeHob (

+    PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);

+    PlatformAddReservedMemoryBaseSizeHob (

       SMM_DEFAULT_SMBASE,

       MCH_DEFAULT_SMBASE_SIZE,

       TRUE /* Cacheable */

@@ -826,12 +826,12 @@ QemuInitializeRamBelow1gb (
       SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,

       "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"

       );

-    AddMemoryRangeHob (

+    PlatformAddMemoryRangeHob (

       SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,

       BASE_512KB + BASE_128KB

       );

   } else {

-    AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);

+    PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB);

   }

 }

 

@@ -889,14 +889,14 @@ QemuInitializeRam (
       UINT32  TsegSize;

 

       TsegSize = mQ35TsegMbytes * SIZE_1MB;

-      AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);

-      AddReservedMemoryBaseSizeHob (

+      PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);

+      PlatformAddReservedMemoryBaseSizeHob (

         LowerMemorySize - TsegSize,

         TsegSize,

         TRUE

         );

     } else {

-      AddMemoryRangeHob (BASE_1MB, LowerMemorySize);

+      PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize);

     }

 

     //

@@ -908,7 +908,7 @@ QemuInitializeRam (
     if (EFI_ERROR (Status)) {

       UpperMemorySize = GetSystemMemorySizeAbove4gb ();

       if (UpperMemorySize != 0) {

-        AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);

+        PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);

       }

     }

   }

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 5948917864..62480c3c40 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -58,85 +58,6 @@ BOOLEAN  mS3Supported = FALSE;
 UINT32  mMaxCpuCount;

 

 VOID

-AddIoMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  UINT64                MemorySize

-  )

-{

-  BuildResourceDescriptorHob (

-    EFI_RESOURCE_MEMORY_MAPPED_IO,

-    EFI_RESOURCE_ATTRIBUTE_PRESENT     |

-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

-    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

-    EFI_RESOURCE_ATTRIBUTE_TESTED,

-    MemoryBase,

-    MemorySize

-    );

-}

-

-VOID

-AddReservedMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  UINT64                MemorySize,

-  BOOLEAN               Cacheable

-  )

-{

-  BuildResourceDescriptorHob (

-    EFI_RESOURCE_MEMORY_RESERVED,

-    EFI_RESOURCE_ATTRIBUTE_PRESENT     |

-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

-    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

-    (Cacheable ?

-     EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |

-     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |

-     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :

-     0

-    ) |

-    EFI_RESOURCE_ATTRIBUTE_TESTED,

-    MemoryBase,

-    MemorySize

-    );

-}

-

-VOID

-AddIoMemoryRangeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  EFI_PHYSICAL_ADDRESS  MemoryLimit

-  )

-{

-  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));

-}

-

-VOID

-AddMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  UINT64                MemorySize

-  )

-{

-  BuildResourceDescriptorHob (

-    EFI_RESOURCE_SYSTEM_MEMORY,

-    EFI_RESOURCE_ATTRIBUTE_PRESENT |

-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

-    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

-    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |

-    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |

-    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |

-    EFI_RESOURCE_ATTRIBUTE_TESTED,

-    MemoryBase,

-    MemorySize

-    );

-}

-

-VOID

-AddMemoryRangeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  EFI_PHYSICAL_ADDRESS  MemoryLimit

-  )

-{

-  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));

-}

-

-VOID

 MemMapInitialization (

   VOID

   )

@@ -155,12 +76,12 @@ MemMapInitialization (
   //

   // Video memory + Legacy BIOS region

   //

-  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);

+  PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);

 

   if (mHostBridgeDevId == 0xffff /* microvm */) {

-    AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);

-    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */

-    AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */

+    PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);

+    PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */

+    PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */

     return;

   }

 

@@ -194,20 +115,20 @@ MemMapInitialization (
   // 0xFEE00000    LAPIC                          1 MB

   //

   PciSize = 0xFC000000 - PciBase;

-  AddIoMemoryBaseSizeHob (PciBase, PciSize);

+  PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);

   PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);

   ASSERT_RETURN_ERROR (PcdStatus);

   PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);

   ASSERT_RETURN_ERROR (PcdStatus);

 

-  AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);

-  AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);

+  PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);

+  PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);

   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {

-    AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);

+    PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);

     //

     // Note: there should be an

     //

-    //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);

+    //   PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);

     //

     // call below, just like the one above for RCBA. However, Linux insists

     // that the MMCONFIG area be marked in the E820 or UEFI memory map as

@@ -225,7 +146,7 @@ MemMapInitialization (
     // is most definitely not RAM; so, as an exception, cover it with

     // uncacheable reserved memory right here.

     //

-    AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);

+    PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);

     BuildMemoryAllocationHob (

       PciExBarBase,

       SIZE_256MB,

@@ -233,7 +154,7 @@ MemMapInitialization (
       );

   }

 

-  AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);

+  PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);

 

   //

   // On Q35, the IO Port space is available for PCI resource allocations from

diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index 24e4da4e1d..f193ff7365 100644
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -12,37 +12,6 @@
 #include <IndustryStandard/E820.h>

 

 VOID

-AddIoMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  UINT64                MemorySize

-  );

-

-VOID

-AddIoMemoryRangeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  EFI_PHYSICAL_ADDRESS  MemoryLimit

-  );

-

-VOID

-AddMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  UINT64                MemorySize

-  );

-

-VOID

-AddMemoryRangeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  EFI_PHYSICAL_ADDRESS  MemoryLimit

-  );

-

-VOID

-AddReservedMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS  MemoryBase,

-  UINT64                MemorySize,

-  BOOLEAN               Cacheable

-  );

-

-VOID

 AddressWidthInitialization (

   VOID

   );