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author | Brijesh Singh via groups.io <brijesh.singh=amd.com@groups.io> | 2021-12-09 11:27:34 +0800 |
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committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-09 06:28:10 +0000 |
commit | cca9cd3dd6bfb95ed59c398b8e578d8ffd3437f1 (patch) | |
tree | 0119132e0ea207dbe4624d17c25a4921a792b305 /OvmfPkg/ResetVector | |
parent | 707c71a01b9d00e0e40db500edb288e6cecdc032 (diff) | |
download | edk2-cca9cd3dd6bfb95ed59c398b8e578d8ffd3437f1.tar.gz edk2-cca9cd3dd6bfb95ed59c398b8e578d8ffd3437f1.tar.bz2 edk2-cca9cd3dd6bfb95ed59c398b8e578d8ffd3437f1.zip |
OvmfPkg: reserve CPUID page
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
Platform features and capabilities are traditionally discovered via the
CPUID instruction. Hypervisors typically trap and emulate the CPUID
instruction for a variety of reasons. There are some cases where incorrect
CPUID information can potentially lead to a security issue. The SEV-SNP
firmware provides a feature to filter the CPUID results through the PSP.
The filtered CPUID values are saved on a special page for the guest to
consume. Reserve a page in MEMFD that will contain the results of
filtered CPUID values.
Cc: Michael Roth <michael.roth@amd.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Diffstat (limited to 'OvmfPkg/ResetVector')
-rw-r--r-- | OvmfPkg/ResetVector/ResetVector.inf | 2 | ||||
-rw-r--r-- | OvmfPkg/ResetVector/ResetVector.nasmb | 2 | ||||
-rw-r--r-- | OvmfPkg/ResetVector/X64/OvmfSevMetadata.asm | 16 |
3 files changed, 20 insertions, 0 deletions
diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/ResetVector.inf index fcbc25d0ce..1c5d84184e 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -55,6 +55,8 @@ gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize
[FixedPcd]
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize
gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase
gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretSize
gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase
diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb index 4e685ef236..fbaeab5f51 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -105,6 +105,8 @@ %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
%define SEV_SNP_SECRETS_BASE (FixedPcdGet32 (PcdOvmfSnpSecretsBase))
%define SEV_SNP_SECRETS_SIZE (FixedPcdGet32 (PcdOvmfSnpSecretsSize))
+ %define CPUID_BASE (FixedPcdGet32 (PcdOvmfCpuidBase))
+ %define CPUID_SIZE (FixedPcdGet32 (PcdOvmfCpuidSize))
%include "X64/IntelTdxMetadata.asm"
%include "Ia32/Flat32ToFlat64.asm"
diff --git a/OvmfPkg/ResetVector/X64/OvmfSevMetadata.asm b/OvmfPkg/ResetVector/X64/OvmfSevMetadata.asm index 2bc7790bd8..0cc12ad347 100644 --- a/OvmfPkg/ResetVector/X64/OvmfSevMetadata.asm +++ b/OvmfPkg/ResetVector/X64/OvmfSevMetadata.asm @@ -17,6 +17,16 @@ BITS 64 ; AMD SEV-SNP specific sections
%define OVMF_SECTION_TYPE_SNP_SECRETS 0x2
+;
+; The section contains the hypervisor pre-populated CPUID values.
+; In the case of SEV-SNP, the CPUID values are filtered and measured by
+; the SEV-SNP firmware.
+; The CPUID format is documented in SEV-SNP firmware spec 0.9 section 7.1
+; (CPUID function structure).
+;
+%define OVMF_SECTION_TYPE_CPUID 0x3
+
+
ALIGN 16
TIMES (15 - ((OvmfSevGuidedStructureEnd - OvmfSevGuidedStructureStart + 15) % 16)) DB 0
@@ -39,5 +49,11 @@ SevSnpSecrets: DD SEV_SNP_SECRETS_SIZE
DD OVMF_SECTION_TYPE_SNP_SECRETS
+; CPUID values
+CpuidSec:
+ DD CPUID_BASE
+ DD CPUID_SIZE
+ DD OVMF_SECTION_TYPE_CPUID
+
OvmfSevGuidedStructureEnd:
ALIGN 16
|