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| author | Andrei Warkentin <andrei.warkentin@intel.com> | 2023-03-01 10:48:17 -0600 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-05-17 23:47:20 +0000 |
| commit | 0abfb0be6cf78a8e962383e85cec57851ddae5bc (patch) | |
| tree | cafe81565583677d632029ca70f413350f83bc96 /OvmfPkg/RiscVVirt/Sec/SecMain.c | |
| parent | 45da4e313579f0bcea42062c675c8333d3bad050 (diff) | |
| download | edk2-0abfb0be6cf78a8e962383e85cec57851ddae5bc.tar.gz edk2-0abfb0be6cf78a8e962383e85cec57851ddae5bc.tar.bz2 edk2-0abfb0be6cf78a8e962383e85cec57851ddae5bc.zip | |
OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec
If the SerialPortLib had any initialization needed, this
would be skipped in the RiscVVirt Sec. Follow the example
seen elsewhere (ArmVirtPkg PrePi).
Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec,
yet using DBCN elsewhere.
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Diffstat (limited to 'OvmfPkg/RiscVVirt/Sec/SecMain.c')
| -rw-r--r-- | OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c index b052048178..6db39b9401 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file
RISC-V SEC phase module for Qemu Virt.
- Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -57,6 +57,8 @@ SecStartup ( UINT64 StackBase;
UINT32 StackSize;
+ SerialPortInitialize ();
+
//
// Report Status Code to indicate entering SEC core
//
|