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| author | Brijesh Singh <brijesh.singh@amd.com> | 2022-02-21 22:59:13 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-02-28 02:46:08 +0000 |
| commit | 63c50d3ff2854a76432b752af4f2a76f33ff1974 (patch) | |
| tree | 1b186c1460932d5db0a075b6c6ed328386112f4b /OvmfPkg/Sec | |
| parent | de463163d9f6d3c5dc6b55ff35d1e5676e0e1b9f (diff) | |
| download | edk2-63c50d3ff2854a76432b752af4f2a76f33ff1974.tar.gz edk2-63c50d3ff2854a76432b752af4f2a76f33ff1974.tar.bz2 edk2-63c50d3ff2854a76432b752af4f2a76f33ff1974.zip | |
OvmfPkg/ResetVector: cache the SEV status MSR value in workarea
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3582
In order to probe the SEV feature the BaseMemEncryptLib and Reset vector
reads the SEV_STATUS MSR. Cache the value on the first read in the
workarea. In the next patches the value saved in the workarea will
be used by the BaseMemEncryptLib. This not only eliminates the extra
MSR reads it also helps cleaning up the code in BaseMemEncryptLib.
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Diffstat (limited to 'OvmfPkg/Sec')
| -rw-r--r-- | OvmfPkg/Sec/AmdSev.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/OvmfPkg/Sec/AmdSev.c b/OvmfPkg/Sec/AmdSev.c index 499d0c27d8..d8fd35650d 100644 --- a/OvmfPkg/Sec/AmdSev.c +++ b/OvmfPkg/Sec/AmdSev.c @@ -278,7 +278,7 @@ SevEsIsEnabled ( SevEsWorkArea = (SEC_SEV_ES_WORK_AREA *)FixedPcdGet32 (PcdSevEsWorkAreaBase);
- return (SevEsWorkArea->SevEsEnabled != 0);
+ return ((SevEsWorkArea->SevStatusMsrValue & BIT1) != 0);
}
/**
|