diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:09 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | ac0a286f4d747a4c6c603a7b225917293cbe1e9f (patch) | |
| tree | 32654f2b35755afc961e2c97296b2dec5762da75 /OvmfPkg/SmmAccess/SmramInternal.c | |
| parent | d1050b9dff1cace252aff86630bfdb59dff5f507 (diff) | |
| download | edk2-ac0a286f4d747a4c6c603a7b225917293cbe1e9f.tar.gz edk2-ac0a286f4d747a4c6c603a7b225917293cbe1e9f.tar.bz2 edk2-ac0a286f4d747a4c6c603a7b225917293cbe1e9f.zip | |
OvmfPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the OvmfPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
Diffstat (limited to 'OvmfPkg/SmmAccess/SmramInternal.c')
| -rw-r--r-- | OvmfPkg/SmmAccess/SmramInternal.c | 63 |
1 files changed, 35 insertions, 28 deletions
diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInternal.c index 0b07dc667b..d391ddc9ae 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.c +++ b/OvmfPkg/SmmAccess/SmramInternal.c @@ -19,13 +19,13 @@ //
// The value of PcdQ35TsegMbytes is saved into this variable at module startup.
//
-UINT16 mQ35TsegMbytes;
+UINT16 mQ35TsegMbytes;
//
// The value of PcdQ35SmramAtDefaultSmbase is saved into this variable at
// module startup.
//
-STATIC BOOLEAN mQ35SmramAtDefaultSmbase;
+STATIC BOOLEAN mQ35SmramAtDefaultSmbase;
/**
Save PcdQ35TsegMbytes into mQ35TsegMbytes.
@@ -65,11 +65,11 @@ InitQ35SmramAtDefaultSmbase ( **/
VOID
GetStates (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
-)
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
+ )
{
- UINT8 SmramVal, EsmramcVal;
+ UINT8 SmramVal, EsmramcVal;
SmramVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_SMRAM));
EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
@@ -91,27 +91,30 @@ GetStates ( EFI_STATUS
SmramAccessOpen (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
)
{
//
// Open TSEG by clearing T_EN.
//
- PciAnd8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC),
- (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff));
+ PciAnd8 (
+ DRAMC_REGISTER_Q35 (MCH_ESMRAMC),
+ (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff)
+ );
GetStates (LockState, OpenState);
if (!*OpenState) {
return EFI_DEVICE_ERROR;
}
+
return EFI_SUCCESS;
}
EFI_STATUS
SmramAccessClose (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
)
{
//
@@ -123,13 +126,14 @@ SmramAccessClose ( if (*OpenState) {
return EFI_DEVICE_ERROR;
}
+
return EFI_SUCCESS;
}
EFI_STATUS
SmramAccessLock (
- OUT BOOLEAN *LockState,
- IN OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ IN OUT BOOLEAN *OpenState
)
{
if (*OpenState) {
@@ -140,35 +144,38 @@ SmramAccessLock ( // Close & lock TSEG by setting T_EN and D_LCK.
//
PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);
- PciOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM), MCH_SMRAM_D_LCK);
+ PciOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM), MCH_SMRAM_D_LCK);
//
// Close & lock the SMRAM at the default SMBASE, if it exists.
//
if (mQ35SmramAtDefaultSmbase) {
- PciWrite8 (DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL),
- MCH_DEFAULT_SMBASE_LCK);
+ PciWrite8 (
+ DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL),
+ MCH_DEFAULT_SMBASE_LCK
+ );
}
GetStates (LockState, OpenState);
if (*OpenState || !*LockState) {
return EFI_DEVICE_ERROR;
}
+
return EFI_SUCCESS;
}
EFI_STATUS
SmramAccessGetCapabilities (
- IN BOOLEAN LockState,
- IN BOOLEAN OpenState,
- IN OUT UINTN *SmramMapSize,
- IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ IN BOOLEAN LockState,
+ IN BOOLEAN OpenState,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
)
{
- UINTN OriginalSize;
- UINT32 TsegMemoryBaseMb, TsegMemoryBase;
- UINT64 CommonRegionState;
- UINT8 TsegSizeBits;
+ UINTN OriginalSize;
+ UINT32 TsegMemoryBaseMb, TsegMemoryBase;
+ UINT64 CommonRegionState;
+ UINT8 TsegSizeBits;
OriginalSize = *SmramMapSize;
*SmramMapSize = DescIdxCount * sizeof *SmramMap;
@@ -180,7 +187,7 @@ SmramAccessGetCapabilities ( // Read the TSEG Memory Base register.
//
TsegMemoryBaseMb = PciRead32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB));
- TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;
+ TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;
//
// Precompute the region state bits that will be set for all regions.
@@ -198,7 +205,7 @@ SmramAccessGetCapabilities ( SmramMap[DescIdxSmmS3ResumeState].CpuStart = TsegMemoryBase;
SmramMap[DescIdxSmmS3ResumeState].PhysicalSize =
EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE)));
- SmramMap[DescIdxSmmS3ResumeState].RegionState =
+ SmramMap[DescIdxSmmS3ResumeState].RegionState =
CommonRegionState | EFI_ALLOCATED;
//
@@ -213,7 +220,7 @@ SmramAccessGetCapabilities ( SmramMap[DescIdxMain].PhysicalStart =
SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +
SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
- SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
+ SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
SmramMap[DescIdxMain].PhysicalSize =
(TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
|